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Differential D24480 Diff 71070 test/Transforms/InstCombine/zext-bool-add-sub.ll

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test/Transforms/InstCombine/zext-bool-add-sub.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -instcombine -S | FileCheck %s ; RUN: opt < %s -instcombine -S | FileCheck %s
; rdar://11748024 ; rdar://11748024
define i32 @a(i1 zeroext %x, i1 zeroext %y) { define i32 @a(i1 zeroext %x, i1 zeroext %y) {
; CHECK-LABEL: @a( ; CHECK-LABEL: @a(
; CHECK-NEXT: [[CONV:%.*]] = zext i1 %x to i32
; CHECK-NEXT: [[CONV3_NEG:%.*]] = sext i1 %y to i32 ; CHECK-NEXT: [[CONV3_NEG:%.*]] = sext i1 %y to i32
; CHECK-NEXT: [[SUB:%.*]] = select i1 %x, i32 2, i32 1 ; CHECK-NEXT: [[SUB:%.*]] = add nuw nsw i32 [[CONV]], 1
; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[SUB]], [[CONV3_NEG]] ; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[SUB]], [[CONV3_NEG]]
; CHECK-NEXT: ret i32 [[ADD]] ; CHECK-NEXT: ret i32 [[ADD]]
; ;
%conv = zext i1 %x to i32 %conv = zext i1 %x to i32
%conv3 = zext i1 %y to i32 %conv3 = zext i1 %y to i32
%conv3.neg = sub i32 0, %conv3 %conv3.neg = sub i32 0, %conv3
%sub = add i32 %conv, 1 %sub = add i32 %conv, 1
%add = add i32 %sub, %conv3.neg %add = add i32 %sub, %conv3.neg
Show All 24 Lines;
%conv3 = zext i1 %b to i32 %conv3 = zext i1 %b to i32
%add = add nuw nsw i32 %conv3, %conv %add = add nuw nsw i32 %conv3, %conv
ret i32 %add ret i32 %add
} }
define i32 @PR30273_three_bools(i1 %x, i1 %y, i1 %z) { define i32 @PR30273_three_bools(i1 %x, i1 %y, i1 %z) {
; CHECK-LABEL: @PR30273_three_bools( ; CHECK-LABEL: @PR30273_three_bools(
; CHECK-NEXT: [[FROMBOOL:%.*]] = zext i1 %x to i32 ; CHECK-NEXT: [[FROMBOOL:%.*]] = zext i1 %x to i32
; CHECK-NEXT: [[ADD1:%.*]] = select i1 %x, i32 2, i32 1 ; CHECK-NEXT: [[ADD1:%.*]] = zext i1 %y to i32
; CHECK-NEXT: [[SEL1:%.*]] = select i1 %y, i32 [[ADD1]], i32 [[FROMBOOL]] ; CHECK-NEXT: [[SEL1:%.*]] = add nuw nsw i32 [[FROMBOOL]], [[ADD1]]
; CHECK-NEXT: [[ADD2:%.*]] = zext i1 %z to i32 ; CHECK-NEXT: [[ADD2:%.*]] = zext i1 %z to i32
; CHECK-NEXT: [[SEL2:%.*]] = add nuw nsw i32 [[SEL1]], [[ADD2]] ; CHECK-NEXT: [[SEL2:%.*]] = add nuw nsw i32 [[SEL1]], [[ADD2]]
; CHECK-NEXT: ret i32 [[SEL2]] ; CHECK-NEXT: ret i32 [[SEL2]]
; ;
%frombool = zext i1 %x to i32 %frombool = zext i1 %x to i32
%add1 = add nsw i32 %frombool, 1 %add1 = add nsw i32 %frombool, 1
%sel1 = select i1 %y, i32 %add1, i32 %frombool %sel1 = select i1 %y, i32 %add1, i32 %frombool
%add2 = add nsw i32 %sel1, 1 %add2 = add nsw i32 %sel1, 1
%sel2 = select i1 %z, i32 %add2, i32 %sel1 %sel2 = select i1 %z, i32 %add2, i32 %sel1
ret i32 %sel2 ret i32 %sel2
} }