Differential D23795 Diff 69866 lib/Target/Mips/MipsFastISel.cpp

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lib/Target/Mips/MipsFastISel.cpp

Show First 20 Lines • Show All 970 Lines • ▼ Show 20 Lines	bool MipsFastISel::selectFPExt(const Instruction *I) {
emitInst(Mips::CVT_D32_S, DestReg).addReg(SrcReg);		emitInst(Mips::CVT_D32_S, DestReg).addReg(SrcReg);
updateValueMap(I, DestReg);		updateValueMap(I, DestReg);
return true;		return true;
}		}

bool MipsFastISel::selectSelect(const Instruction *I) {		bool MipsFastISel::selectSelect(const Instruction *I) {
assert(isa<SelectInst>(I) && "Expected a select instruction.");		assert(isa<SelectInst>(I) && "Expected a select instruction.");

		DEBUG(dbgs() << "selectSelect\n");

MVT VT;		MVT VT;
if (!isTypeSupported(I->getType(), VT))		if (!isTypeSupported(I->getType(), VT) \|\| UnsupportedFPMode) {
		DEBUG(dbgs() << ".. .. gave up (!isTypeSupported \|\| UnsupportedFPMode)\n");
return false;		return false;
		}

unsigned CondMovOpc;		unsigned CondMovOpc;
const TargetRegisterClass *RC;		const TargetRegisterClass *RC;

if (VT.isInteger() && !VT.isVector() && VT.getSizeInBits() <= 32) {		if (VT.isInteger() && !VT.isVector() && VT.getSizeInBits() <= 32) {
CondMovOpc = Mips::MOVN_I_I;		CondMovOpc = Mips::MOVN_I_I;
RC = &Mips::GPR32RegClass;		RC = &Mips::GPR32RegClass;
} else if (VT == MVT::f32) {		} else if (VT == MVT::f32) {
▲ Show 20 Lines • Show All 381 Lines • ▼ Show 20 Lines	case MVT::f32:
// ABI rules require us to skip the corresponding GPR32.		// ABI rules require us to skip the corresponding GPR32.
if (NextGPR32 != GPR32ArgRegs.end())		if (NextGPR32 != GPR32ArgRegs.end())
NextGPR32++;		NextGPR32++;
if (NextAFGR64 != AFGR64ArgRegs.end())		if (NextAFGR64 != AFGR64ArgRegs.end())
NextAFGR64++;		NextAFGR64++;
break;		break;

case MVT::f64:		case MVT::f64:
		if (UnsupportedFPMode) {
		DEBUG(dbgs() << ".. .. gave up (UnsupportedFPMode\n");
		return false;
		}
if (NextAFGR64 == AFGR64ArgRegs.end()) {		if (NextAFGR64 == AFGR64ArgRegs.end()) {
DEBUG(dbgs() << ".. .. gave up (ran out of AFGR64 arguments)\n");		DEBUG(dbgs() << ".. .. gave up (ran out of AFGR64 arguments)\n");
return false;		return false;
}		}
DEBUG(dbgs() << ".. .. AFGR64(" << *NextAFGR64 << ")\n");		DEBUG(dbgs() << ".. .. AFGR64(" << *NextAFGR64 << ")\n");
Allocation.emplace_back(&Mips::AFGR64RegClass, *NextAFGR64++);		Allocation.emplace_back(&Mips::AFGR64RegClass, *NextAFGR64++);
// Allocating an FGR32 also allocates the super-register AFGR64, and		// Allocating an FGR32 also allocates the super-register AFGR64, and
// ABI rules require us to skip the corresponding GPR32 pair.		// ABI rules require us to skip the corresponding GPR32 pair.
▲ Show 20 Lines • Show All 225 Lines • ▼ Show 20 Lines	bool MipsFastISel::fastLowerIntrinsicCall(const IntrinsicInst *II) {
}		}
return false;		return false;
}		}

bool MipsFastISel::selectRet(const Instruction *I) {		bool MipsFastISel::selectRet(const Instruction *I) {
const Function &F = *I->getParent()->getParent();		const Function &F = *I->getParent()->getParent();
const ReturnInst *Ret = cast<ReturnInst>(I);		const ReturnInst *Ret = cast<ReturnInst>(I);

		DEBUG(dbgs() << "selectRet\n");

if (!FuncInfo.CanLowerReturn)		if (!FuncInfo.CanLowerReturn)
return false;		return false;

// Build a list of return value registers.		// Build a list of return value registers.
SmallVector<unsigned, 4> RetRegs;		SmallVector<unsigned, 4> RetRegs;

if (Ret->getNumOperands() > 0) {		if (Ret->getNumOperands() > 0) {
CallingConv::ID CC = F.getCallingConv();		CallingConv::ID CC = F.getCallingConv();
▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines	if (Ret->getNumOperands() > 0) {

if (RVEVT.isVector())		if (RVEVT.isVector())
return false;		return false;

MVT RVVT = RVEVT.getSimpleVT();		MVT RVVT = RVEVT.getSimpleVT();
if (RVVT == MVT::f128)		if (RVVT == MVT::f128)
return false;		return false;

		// Do not handle FGR64 returns for now.
		if (RVVT == MVT::f64 && UnsupportedFPMode) {
		DEBUG(dbgs() << ".. .. gave up (UnsupportedFPMode\n");
		return false;
		}

MVT DestVT = VA.getValVT();		MVT DestVT = VA.getValVT();
// Special handling for extended integers.		// Special handling for extended integers.
if (RVVT != DestVT) {		if (RVVT != DestVT) {
if (RVVT != MVT::i1 && RVVT != MVT::i8 && RVVT != MVT::i16)		if (RVVT != MVT::i1 && RVVT != MVT::i8 && RVVT != MVT::i16)
return false;		return false;

if (Outs[0].Flags.isZExt() \|\| Outs[0].Flags.isSExt()) {		if (Outs[0].Flags.isZExt() \|\| Outs[0].Flags.isSExt()) {
bool IsZExt = Outs[0].Flags.isZExt();		bool IsZExt = Outs[0].Flags.isZExt();
▲ Show 20 Lines • Show All 393 Lines • Show Last 20 Lines