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clang/include/clang/Basic/Attr.td
| Show First 20 Lines • Show All 1,865 Lines • ▼ Show 20 Lines | def RISCVInterrupt : InheritableAttr, TargetSpecificAttr<TargetRISCV> { | ||||
| let Args = [EnumArgument<"Interrupt", "InterruptType", | let Args = [EnumArgument<"Interrupt", "InterruptType", | ||||
| ["supervisor", "machine"], | ["supervisor", "machine"], | ||||
| ["supervisor", "machine"], | ["supervisor", "machine"], | ||||
| 1>]; | 1>]; | ||||
| let ParseKind = "Interrupt"; | let ParseKind = "Interrupt"; | ||||
| let Documentation = [RISCVInterruptDocs]; | let Documentation = [RISCVInterruptDocs]; | ||||
| } | } | ||||
| def RISCVRVVVectorBits : TypeAttr { | |||||
| let Spellings = [GNU<"riscv_rvv_vector_bits">]; | |||||
| let Subjects = SubjectList<[TypedefName], ErrorDiag>; | |||||
| let Args = [UnsignedArgument<"NumBits">]; | |||||
| let Documentation = [RISCVRVVVectorBitsDocs]; | |||||
| let PragmaAttributeSupport = 0; | |||||
| // Represented as VectorType instead. | |||||
| let ASTNode = 0; | |||||
| } | |||||
| // This is not a TargetSpecificAttr so that is silently accepted and | // This is not a TargetSpecificAttr so that is silently accepted and | ||||
| // ignored on other targets as encouraged by the OpenCL spec. | // ignored on other targets as encouraged by the OpenCL spec. | ||||
| // | // | ||||
| // See OpenCL 1.2 6.11.5: "It is our intention that a particular | // See OpenCL 1.2 6.11.5: "It is our intention that a particular | ||||
| // implementation of OpenCL be free to ignore all attributes and the | // implementation of OpenCL be free to ignore all attributes and the | ||||
| // resulting executable binary will produce the same result." | // resulting executable binary will produce the same result." | ||||
| // | // | ||||
| // However, only AMD GPU targets will emit the corresponding IR | // However, only AMD GPU targets will emit the corresponding IR | ||||
| ▲ Show 20 Lines • Show All 2,279 Lines • Show Last 20 Lines | |||||