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Differential D145088 Diff 518072 clang/docs/ReleaseNotes.rst

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clang/docs/ReleaseNotes.rst

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	- Added ``-mrvv-vector-bits=`` option to give an upper and lower bound on vector			- Added ``-mrvv-vector-bits=`` option to give an upper and lower bound on vector
	length. Valid values are powers of 2 between 64 and 65536. A value of 32			length. Valid values are powers of 2 between 64 and 65536. A value of 32
	should eventually be supported. We also accept "zvl" to use the Zvl*b			should eventually be supported. We also accept "zvl" to use the Zvl*b
	extension from ``-march`` or ``-mcpu`` to the be the upper and lower bound.			extension from ``-march`` or ``-mcpu`` to the be the upper and lower bound.
	- Fixed incorrect ABI lowering of ``_Float16`` in the case of structs			- Fixed incorrect ABI lowering of ``_Float16`` in the case of structs
	containing ``_Float16`` that are eligible for passing via GPR+FPR or			containing ``_Float16`` that are eligible for passing via GPR+FPR or
	FPR+FPR.			FPR+FPR.
	- Removed support for ``__attribute__((interrupt("user")))``. User-level			- Removed support for ``__attribute__((interrupt("user")))``. User-level
	interrupts are not in version 1.12 of the privileged specification.			interrupts are not in version 1.12 of the privileged specification.
				erichkeaneUnsubmitted Not Done Reply Inline Actions Would love it if we defined "RVV" here. erichkeane: Would love it if we defined "RVV" here.
				- Added ``attribute(riscv_rvv_vector_bits(__riscv_v_fixed_vlen))`` to allow
				the size of a RVV (RISC-V Vector) scalable type to be specified. This allows
				RVV scalable vector types to be used in structs or in global variables.

	CUDA/HIP Language Changes			CUDA/HIP Language Changes
	^^^^^^^^^^^^^^^^^^^^^^^^^			^^^^^^^^^^^^^^^^^^^^^^^^^

	CUDA Support			CUDA Support
	^^^^^^^^^^^^			^^^^^^^^^^^^

	AIX Support			AIX Support
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