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llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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| Show First 20 Lines • Show All 1,127 Lines • ▼ Show 20 Lines | MVT RISCVTargetLowering::getVPExplicitVectorLengthTy() const { | ||||
| return Subtarget.getXLenVT(); | return Subtarget.getXLenVT(); | ||||
| } | } | ||||
| bool RISCVTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, | bool RISCVTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, | ||||
| const CallInst &I, | const CallInst &I, | ||||
| MachineFunction &MF, | MachineFunction &MF, | ||||
| unsigned Intrinsic) const { | unsigned Intrinsic) const { | ||||
| auto &DL = I.getModule()->getDataLayout(); | auto &DL = I.getModule()->getDataLayout(); | ||||
| auto SetRVVLoadStoreInfo = [&](unsigned PtrOp, bool IsStore, | |||||
| bool IsUnitStrided) { | |||||
| Info.opc = IsStore ? ISD::INTRINSIC_VOID : ISD::INTRINSIC_W_CHAIN; | |||||
| Info.ptrVal = I.getArgOperand(PtrOp); | |||||
| Type *MemTy; | |||||
| if (IsStore) { | |||||
| // Store value is the first operand. | |||||
| MemTy = I.getArgOperand(0)->getType(); | |||||
| } else { | |||||
| // Use return type. If it's segment load, return type is a struct. | |||||
| MemTy = I.getType(); | |||||
| if (MemTy->isStructTy()) | |||||
| MemTy = MemTy->getStructElementType(0); | |||||
| } | |||||
| if (!IsUnitStrided) | |||||
| MemTy = MemTy->getScalarType(); | |||||
| Info.memVT = getValueType(DL, MemTy); | |||||
| Info.align = Align(DL.getTypeSizeInBits(MemTy->getScalarType()) / 8); | |||||
| Info.size = MemoryLocation::UnknownSize; | |||||
| Info.flags |= | |||||
| IsStore ? MachineMemOperand::MOStore : MachineMemOperand::MOLoad; | |||||
| return true; | |||||
| }; | |||||
| if (I.getMetadata(LLVMContext::MD_nontemporal) != nullptr) | |||||
| Info.flags |= MachineMemOperand::MONonTemporal; | |||||
| Info.flags |= RISCVTargetLowering::getTargetMMOFlags(I); | |||||
| switch (Intrinsic) { | switch (Intrinsic) { | ||||
| default: | default: | ||||
| return false; | return false; | ||||
| case Intrinsic::riscv_masked_atomicrmw_xchg_i32: | case Intrinsic::riscv_masked_atomicrmw_xchg_i32: | ||||
| case Intrinsic::riscv_masked_atomicrmw_add_i32: | case Intrinsic::riscv_masked_atomicrmw_add_i32: | ||||
| case Intrinsic::riscv_masked_atomicrmw_sub_i32: | case Intrinsic::riscv_masked_atomicrmw_sub_i32: | ||||
| case Intrinsic::riscv_masked_atomicrmw_nand_i32: | case Intrinsic::riscv_masked_atomicrmw_nand_i32: | ||||
| case Intrinsic::riscv_masked_atomicrmw_max_i32: | case Intrinsic::riscv_masked_atomicrmw_max_i32: | ||||
| case Intrinsic::riscv_masked_atomicrmw_min_i32: | case Intrinsic::riscv_masked_atomicrmw_min_i32: | ||||
| case Intrinsic::riscv_masked_atomicrmw_umax_i32: | case Intrinsic::riscv_masked_atomicrmw_umax_i32: | ||||
| case Intrinsic::riscv_masked_atomicrmw_umin_i32: | case Intrinsic::riscv_masked_atomicrmw_umin_i32: | ||||
| case Intrinsic::riscv_masked_cmpxchg_i32: | case Intrinsic::riscv_masked_cmpxchg_i32: | ||||
| Info.opc = ISD::INTRINSIC_W_CHAIN; | Info.opc = ISD::INTRINSIC_W_CHAIN; | ||||
| Info.memVT = MVT::i32; | Info.memVT = MVT::i32; | ||||
| Info.ptrVal = I.getArgOperand(0); | Info.ptrVal = I.getArgOperand(0); | ||||
| Info.offset = 0; | Info.offset = 0; | ||||
| Info.align = Align(4); | Info.align = Align(4); | ||||
| Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore | | Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore | | ||||
| MachineMemOperand::MOVolatile; | MachineMemOperand::MOVolatile; | ||||
| return true; | return true; | ||||
| case Intrinsic::riscv_masked_strided_load: | case Intrinsic::riscv_masked_strided_load: | ||||
| Info.opc = ISD::INTRINSIC_W_CHAIN; | return SetRVVLoadStoreInfo(/*PtrOp*/ 1, /*IsStore*/ false, | ||||
| Info.ptrVal = I.getArgOperand(1); | /*IsUnitStrided*/ false); | ||||
| Info.memVT = getValueType(DL, I.getType()->getScalarType()); | |||||
| Info.align = Align(DL.getTypeSizeInBits(I.getType()->getScalarType()) / 8); | |||||
| Info.size = MemoryLocation::UnknownSize; | |||||
| Info.flags |= MachineMemOperand::MOLoad; | |||||
| return true; | |||||
| case Intrinsic::riscv_masked_strided_store: | case Intrinsic::riscv_masked_strided_store: | ||||
| Info.opc = ISD::INTRINSIC_VOID; | return SetRVVLoadStoreInfo(/*PtrOp*/ 1, /*IsStore*/ true, | ||||
| Info.ptrVal = I.getArgOperand(1); | /*IsUnitStrided*/ false); | ||||
| Info.memVT = | |||||
| getValueType(DL, I.getArgOperand(0)->getType()->getScalarType()); | |||||
| Info.align = Align( | |||||
| DL.getTypeSizeInBits(I.getArgOperand(0)->getType()->getScalarType()) / | |||||
| 8); | |||||
| Info.size = MemoryLocation::UnknownSize; | |||||
| Info.flags |= MachineMemOperand::MOStore; | |||||
| return true; | |||||
| case Intrinsic::riscv_seg2_load: | case Intrinsic::riscv_seg2_load: | ||||
| case Intrinsic::riscv_seg3_load: | case Intrinsic::riscv_seg3_load: | ||||
| case Intrinsic::riscv_seg4_load: | case Intrinsic::riscv_seg4_load: | ||||
| case Intrinsic::riscv_seg5_load: | case Intrinsic::riscv_seg5_load: | ||||
| case Intrinsic::riscv_seg6_load: | case Intrinsic::riscv_seg6_load: | ||||
| case Intrinsic::riscv_seg7_load: | case Intrinsic::riscv_seg7_load: | ||||
| case Intrinsic::riscv_seg8_load: | case Intrinsic::riscv_seg8_load: | ||||
| Info.opc = ISD::INTRINSIC_W_CHAIN; | return SetRVVLoadStoreInfo(/*PtrOp*/ 0, /*IsStore*/ false, | ||||
| Info.ptrVal = I.getArgOperand(0); | /*IsUnitStrided*/ false); | ||||
| Info.memVT = | |||||
| getValueType(DL, I.getType()->getStructElementType(0)->getScalarType()); | |||||
| Info.align = | |||||
| Align(DL.getTypeSizeInBits( | |||||
| I.getType()->getStructElementType(0)->getScalarType()) / | |||||
| 8); | |||||
| Info.size = MemoryLocation::UnknownSize; | |||||
| Info.flags |= MachineMemOperand::MOLoad; | |||||
| return true; | |||||
| case Intrinsic::riscv_seg2_store: | case Intrinsic::riscv_seg2_store: | ||||
| case Intrinsic::riscv_seg3_store: | case Intrinsic::riscv_seg3_store: | ||||
| case Intrinsic::riscv_seg4_store: | case Intrinsic::riscv_seg4_store: | ||||
| case Intrinsic::riscv_seg5_store: | case Intrinsic::riscv_seg5_store: | ||||
| case Intrinsic::riscv_seg6_store: | case Intrinsic::riscv_seg6_store: | ||||
| case Intrinsic::riscv_seg7_store: | case Intrinsic::riscv_seg7_store: | ||||
| case Intrinsic::riscv_seg8_store: | case Intrinsic::riscv_seg8_store: | ||||
| Info.opc = ISD::INTRINSIC_VOID; | |||||
| // Operands are (vec, ..., vec, ptr, vl, int_id) | // Operands are (vec, ..., vec, ptr, vl, int_id) | ||||
| Info.ptrVal = I.getArgOperand(I.getNumOperands() - 3); | return SetRVVLoadStoreInfo(/*PtrOp*/ I.getNumOperands() - 3, | ||||
| Info.memVT = | /*IsStore*/ true, | ||||
| getValueType(DL, I.getArgOperand(0)->getType()->getScalarType()); | /*IsUnitStrided*/ false); | ||||
| Info.align = Align( | |||||
| DL.getTypeSizeInBits(I.getArgOperand(0)->getType()->getScalarType()) / | |||||
| 8); | |||||
| Info.size = MemoryLocation::UnknownSize; | |||||
| Info.flags |= MachineMemOperand::MOStore; | |||||
| return true; | |||||
| } | } | ||||
| } | } | ||||
| bool RISCVTargetLowering::isLegalAddressingMode(const DataLayout &DL, | bool RISCVTargetLowering::isLegalAddressingMode(const DataLayout &DL, | ||||
| const AddrMode &AM, Type *Ty, | const AddrMode &AM, Type *Ty, | ||||
| unsigned AS, | unsigned AS, | ||||
| Instruction *I) const { | Instruction *I) const { | ||||
| // No global is ever allowed as a base. | // No global is ever allowed as a base. | ||||
| ▲ Show 20 Lines • Show All 13,843 Lines • Show Last 20 Lines | |||||