Page MenuHomePhabricator

Please use GitHub pull requests for new patches. Phabricator shutdown timeline

Differential D145510 Diff 505003 llvm/test/Transforms/IndVarSimplify/pr60944.ll

Changeset View

Standalone View

View Options

llvm/test/Transforms/IndVarSimplify/pr60944.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2
; RUN: opt -S -passes=indvars < %s | FileCheck %s ; RUN: opt -S -passes=indvars < %s | FileCheck %s
@x = global i32 0 @x = global i32 0
; FIXME: This is a miscompile.
; %loop2 is never entered and we cannot derive any fact about %iv from it. ; %loop2 is never entered and we cannot derive any fact about %iv from it.
define i32 @main(i32 %iv.start, i32 %arg2) mustprogress { define i32 @main(i32 %iv.start, i32 %arg2) mustprogress {
; CHECK-LABEL: define i32 @main ; CHECK-LABEL: define i32 @main
; CHECK-SAME: (i32 [[IV_START:%.*]], i32 [[ARG2:%.*]]) #[[ATTR0:[0-9]+]] { ; CHECK-SAME: (i32 [[IV_START:%.*]], i32 [[ARG2:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: br label [[LOOP:%.*]] ; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop: ; CHECK: loop:
; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[IV_NEXT:%.*]], [[LOOP_LATCH:%.*]] ], [ [[IV_START]], [[ENTRY:%.*]] ] ; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[IV_NEXT:%.*]], [[LOOP_LATCH:%.*]] ], [ [[IV_START]], [[ENTRY:%.*]] ]
; CHECK-NEXT: br i1 false, label [[LOOP2_PREHEADER:%.*]], label [[LOOP_LATCH]] ; CHECK-NEXT: br i1 false, label [[LOOP2_PREHEADER:%.*]], label [[LOOP_LATCH]]
; CHECK: loop2.preheader: ; CHECK: loop2.preheader:
; CHECK-NEXT: br label [[LOOP2:%.*]] ; CHECK-NEXT: br label [[LOOP2:%.*]]
; CHECK: loop2: ; CHECK: loop2:
; CHECK-NEXT: br i1 true, label [[LOOP2_EXIT:%.*]], label [[LOOP2]] ; CHECK-NEXT: br i1 true, label [[LOOP2_EXIT:%.*]], label [[LOOP2]]
; CHECK: loop2.exit: ; CHECK: loop2.exit:
; CHECK-NEXT: br label [[LOOP_LATCH]] ; CHECK-NEXT: br label [[LOOP_LATCH]]
; CHECK: loop.latch: ; CHECK: loop.latch:
; CHECK-NEXT: [[IV_NEXT]] = sdiv i32 [[ARG2]], [[IV]] ; CHECK-NEXT: [[IV_NEXT]] = sdiv i32 [[ARG2]], [[IV]]
; CHECK-NEXT: br i1 false, label [[LOOP_EXIT:%.*]], label [[LOOP]] ; CHECK-NEXT: [[CMP2:%.*]] = icmp eq i32 [[IV]], -1
; CHECK-NEXT: br i1 [[CMP2]], label [[LOOP_EXIT:%.*]], label [[LOOP]]
; CHECK: loop.exit: ; CHECK: loop.exit:
; CHECK-NEXT: [[IV_NEXT_LCSSA:%.*]] = phi i32 [ [[IV_NEXT]], [[LOOP_LATCH]] ] ; CHECK-NEXT: [[IV_NEXT_LCSSA:%.*]] = phi i32 [ [[IV_NEXT]], [[LOOP_LATCH]] ]
; CHECK-NEXT: ret i32 [[IV_NEXT_LCSSA]] ; CHECK-NEXT: ret i32 [[IV_NEXT_LCSSA]]
; ;
entry: entry:
br label %loop br label %loop
loop: loop:
Show All 23 Lines