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Differential D142313 Diff 500443 llvm/lib/Target/PowerPC/PPCInstrVSX.td

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llvm/lib/Target/PowerPC/PPCInstrVSX.td

Show First 20 Lines • Show All 70 Lines • ▼ Show 20 Linesdef SDT_PPCstxvd2x : SDTypeProfile<0, 2, [
SDTCisVT<0, v2f64>, SDTCisPtrTy<1> SDTCisVT<0, v2f64>, SDTCisPtrTy<1>
]>; ]>;
def SDT_PPCxxswapd : SDTypeProfile<1, 1, [ def SDT_PPCxxswapd : SDTypeProfile<1, 1, [
SDTCisSameAs<0, 1> SDTCisSameAs<0, 1>
]>; ]>;
def SDTVecConv : SDTypeProfile<1, 2, [ def SDTVecConv : SDTypeProfile<1, 2, [
SDTCisVec<0>, SDTCisVec<1>, SDTCisPtrTy<2> SDTCisVec<0>, SDTCisVec<1>, SDTCisPtrTy<2>
]>; ]>;
def SDTVabsd : SDTypeProfile<1, 3, [
SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisVT<3, i32>
]>;
def SDT_PPCld_vec_be : SDTypeProfile<1, 1, [ def SDT_PPCld_vec_be : SDTypeProfile<1, 1, [
SDTCisVec<0>, SDTCisPtrTy<1> SDTCisVec<0>, SDTCisPtrTy<1>
]>; ]>;
def SDT_PPCst_vec_be : SDTypeProfile<0, 2, [ def SDT_PPCst_vec_be : SDTypeProfile<0, 2, [
SDTCisVec<0>, SDTCisPtrTy<1> SDTCisVec<0>, SDTCisPtrTy<1>
]>; ]>;
def SDT_PPCxxperm : SDTypeProfile<1, 3, [ def SDT_PPCxxperm : SDTypeProfile<1, 3, [
Show All 10 Linesdef PPCst_vec_be : SDNode<"PPCISD::STORE_VEC_BE", SDT_PPCst_vec_be,
[SDNPHasChain, SDNPMayStore]>; [SDNPHasChain, SDNPMayStore]>;
def PPCxxswapd : SDNode<"PPCISD::XXSWAPD", SDT_PPCxxswapd, [SDNPHasChain]>; def PPCxxswapd : SDNode<"PPCISD::XXSWAPD", SDT_PPCxxswapd, [SDNPHasChain]>;
def PPCmfvsr : SDNode<"PPCISD::MFVSR", SDTUnaryOp, []>; def PPCmfvsr : SDNode<"PPCISD::MFVSR", SDTUnaryOp, []>;
def PPCmtvsra : SDNode<"PPCISD::MTVSRA", SDTUnaryOp, []>; def PPCmtvsra : SDNode<"PPCISD::MTVSRA", SDTUnaryOp, []>;
def PPCmtvsrz : SDNode<"PPCISD::MTVSRZ", SDTUnaryOp, []>; def PPCmtvsrz : SDNode<"PPCISD::MTVSRZ", SDTUnaryOp, []>;
def PPCsvec2fp : SDNode<"PPCISD::SINT_VEC_TO_FP", SDTVecConv, []>; def PPCsvec2fp : SDNode<"PPCISD::SINT_VEC_TO_FP", SDTVecConv, []>;
def PPCuvec2fp: SDNode<"PPCISD::UINT_VEC_TO_FP", SDTVecConv, []>; def PPCuvec2fp: SDNode<"PPCISD::UINT_VEC_TO_FP", SDTVecConv, []>;
def PPCswapNoChain : SDNode<"PPCISD::SWAP_NO_CHAIN", SDT_PPCxxswapd>; def PPCswapNoChain : SDNode<"PPCISD::SWAP_NO_CHAIN", SDT_PPCxxswapd>;
def PPCvabsd : SDNode<"PPCISD::VABSD", SDTVabsd, []>;
def PPCfpexth : SDNode<"PPCISD::FP_EXTEND_HALF", SDT_PPCfpexth, []>; def PPCfpexth : SDNode<"PPCISD::FP_EXTEND_HALF", SDT_PPCfpexth, []>;
def PPCldvsxlh : SDNode<"PPCISD::LD_VSX_LH", SDT_PPCldvsxlh, def PPCldvsxlh : SDNode<"PPCISD::LD_VSX_LH", SDT_PPCldvsxlh,
[SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
def PPCldsplat : SDNode<"PPCISD::LD_SPLAT", SDT_PPCldsplat, def PPCldsplat : SDNode<"PPCISD::LD_SPLAT", SDT_PPCldsplat,
[SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
def PPCzextldsplat : SDNode<"PPCISD::ZEXT_LD_SPLAT", SDT_PPCldsplat, def PPCzextldsplat : SDNode<"PPCISD::ZEXT_LD_SPLAT", SDT_PPCldsplat,
[SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
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// Unsiged int in vsx register -> QP // Unsiged int in vsx register -> QP
def : Pat<(f128 (uint_to_fp (i32 (PPCmfvsr f64:$src)))), def : Pat<(f128 (uint_to_fp (i32 (PPCmfvsr f64:$src)))),
(f128 (XSCVUDQP (f128 (XSCVUDQP
(XXEXTRACTUW (SUBREG_TO_REG (i64 1), $src, sub_64), 8)))>; (XXEXTRACTUW (SUBREG_TO_REG (i64 1), $src, sub_64), 8)))>;
} // HasVSX, HasP9Vector, IsLittleEndian } // HasVSX, HasP9Vector, IsLittleEndian
// Any Power9 VSX subtarget that supports Power9 Altivec. // Any Power9 VSX subtarget that supports Power9 Altivec.
let Predicates = [HasVSX, HasP9Altivec] in { let Predicates = [HasVSX, HasP9Altivec] in {
// Put this P9Altivec related definition here since it's possible to be // Unsigned absolute-difference.
// selected to VSX instruction xvnegsp, avoid possible undef. def : Pat<(v4i32 (abdu v4i32:$A, v4i32:$B)),
def : Pat<(v4i32 (PPCvabsd v4i32:$A, v4i32:$B, (i32 0))),
(v4i32 (VABSDUW $A, $B))>; (v4i32 (VABSDUW $A, $B))>;
def : Pat<(v8i16 (PPCvabsd v8i16:$A, v8i16:$B, (i32 0))), def : Pat<(v8i16 (abdu v8i16:$A, v8i16:$B)),
(v8i16 (VABSDUH $A, $B))>; (v8i16 (VABSDUH $A, $B))>;
def : Pat<(v16i8 (PPCvabsd v16i8:$A, v16i8:$B, (i32 0))), def : Pat<(v16i8 (abdu v16i8:$A, v16i8:$B)),
(v16i8 (VABSDUB $A, $B))>; (v16i8 (VABSDUB $A, $B))>;
// As PPCVABSD description, the last operand indicates whether do the // Signed absolute-difference.
// sign bit flip. // Power9 VABSD* instructions are designed to support unsigned integer
def : Pat<(v4i32 (PPCvabsd v4i32:$A, v4i32:$B, (i32 1))), // vectors (byte/halfword/word), if we want to make use of them for signed
// integer vectors, we have to flip their sign bits first. To flip sign bit
// for byte/halfword integer vector would become inefficient, but for word
// integer vector, we can leverage XVNEGSP to make it efficiently.
def : Pat<(v4i32 (abds v4i32:$A, v4i32:$B)),
(v4i32 (VABSDUW (XVNEGSP $A), (XVNEGSP $B)))>; (v4i32 (VABSDUW (XVNEGSP $A), (XVNEGSP $B)))>;
} // HasVSX, HasP9Altivec } // HasVSX, HasP9Altivec
// Big endian Power9 64Bit VSX subtargets with P9 Altivec support. // Big endian Power9 64Bit VSX subtargets with P9 Altivec support.
let Predicates = [HasVSX, HasP9Altivec, IsBigEndian, IsPPC64] in { let Predicates = [HasVSX, HasP9Altivec, IsBigEndian, IsPPC64] in {
def : Pat<(i64 (anyext (i32 (vector_extract v16i8:$S, i64:$Idx)))), def : Pat<(i64 (anyext (i32 (vector_extract v16i8:$S, i64:$Idx)))),
(VEXTUBLX $Idx, $S)>; (VEXTUBLX $Idx, $S)>;
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