Differential D19474 Diff 54954 llvm/trunk/lib/Target/PowerPC/PPCScheduleA2.td

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Show First 20 Lines • Show All 154 Lines • ▼ Show 20 Lines	InstrItinData<IIC_FPRes, [InstrStage<1, [A2_FU]>],
[6, 0]>		[6, 0]>
]>;		]>;

// ===---------------------------------------------------------------------===//		// ===---------------------------------------------------------------------===//
// A2 machine model for scheduling and other instruction cost heuristics.		// A2 machine model for scheduling and other instruction cost heuristics.

def PPCA2Model : SchedMachineModel {		def PPCA2Model : SchedMachineModel {
let IssueWidth = 1; // 1 instruction is dispatched per cycle.		let IssueWidth = 1; // 1 instruction is dispatched per cycle.
let MinLatency = -1; // OperandCycles are interpreted as MinLatency.
let LoadLatency = 6; // Optimistic load latency assuming bypass.		let LoadLatency = 6; // Optimistic load latency assuming bypass.
// This is overriden by OperandCycles if the		// This is overriden by OperandCycles if the
// Itineraries are queried instead.		// Itineraries are queried instead.
let MispredictPenalty = 13;		let MispredictPenalty = 13;

let CompleteModel = 0;		let CompleteModel = 0;

let Itineraries = PPCA2Itineraries;		let Itineraries = PPCA2Itineraries;
}		}