Differential D19474 Diff 54954 llvm/trunk/lib/Target/PowerPC/PPCScheduleE500mc.td

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Show First 20 Lines • Show All 305 Lines • ▼ Show 20 Lines	InstrItinData<IIC_FPRes, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
[E500_FPR_Bypass, E500_FPR_Bypass]>		[E500_FPR_Bypass, E500_FPR_Bypass]>
]>;		]>;

// ===---------------------------------------------------------------------===//		// ===---------------------------------------------------------------------===//
// e500mc machine model for scheduling and other instruction cost heuristics.		// e500mc machine model for scheduling and other instruction cost heuristics.

def PPCE500mcModel : SchedMachineModel {		def PPCE500mcModel : SchedMachineModel {
let IssueWidth = 2; // 2 micro-ops are dispatched per cycle.		let IssueWidth = 2; // 2 micro-ops are dispatched per cycle.
let MinLatency = -1; // OperandCycles are interpreted as MinLatency.
let LoadLatency = 5; // Optimistic load latency assuming bypass.		let LoadLatency = 5; // Optimistic load latency assuming bypass.
// This is overriden by OperandCycles if the		// This is overriden by OperandCycles if the
// Itineraries are queried instead.		// Itineraries are queried instead.

let CompleteModel = 0;		let CompleteModel = 0;

let Itineraries = PPCE500mcItineraries;		let Itineraries = PPCE500mcItineraries;
}		}