Differential D19474 Diff 54954 llvm/trunk/lib/Target/PowerPC/PPCScheduleE5500.td

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Show First 20 Lines • Show All 365 Lines • ▼ Show 20 Lines	InstrItinData<IIC_FPRes, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>,
[E5500_FPR_Bypass, E5500_FPR_Bypass]>		[E5500_FPR_Bypass, E5500_FPR_Bypass]>
]>;		]>;

// ===---------------------------------------------------------------------===//		// ===---------------------------------------------------------------------===//
// e5500 machine model for scheduling and other instruction cost heuristics.		// e5500 machine model for scheduling and other instruction cost heuristics.

def PPCE5500Model : SchedMachineModel {		def PPCE5500Model : SchedMachineModel {
let IssueWidth = 2; // 2 micro-ops are dispatched per cycle.		let IssueWidth = 2; // 2 micro-ops are dispatched per cycle.
let MinLatency = -1; // OperandCycles are interpreted as MinLatency.
let LoadLatency = 6; // Optimistic load latency assuming bypass.		let LoadLatency = 6; // Optimistic load latency assuming bypass.
// This is overriden by OperandCycles if the		// This is overriden by OperandCycles if the
// Itineraries are queried instead.		// Itineraries are queried instead.

let CompleteModel = 0;		let CompleteModel = 0;

let Itineraries = PPCE5500Itineraries;		let Itineraries = PPCE5500Itineraries;
}		}