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Differential D140666 Diff 496325 llvm/test/Transforms/InstCombine/icmp-logical.ll

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llvm/test/Transforms/InstCombine/icmp-logical.ll

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%t4 = icmp ne i32 %t3, 8 %t4 = icmp ne i32 %t3, 8
%t5 = select i1 %t4, i1 true, i1 %t2 %t5 = select i1 %t4, i1 true, i1 %t2
ret i1 %t5 ret i1 %t5
} }
define i1 @masked_icmps_bmask_notmixed_or(i32 %A) { define i1 @masked_icmps_bmask_notmixed_or(i32 %A) {
; CHECK-LABEL: @masked_icmps_bmask_notmixed_or( ; CHECK-LABEL: @masked_icmps_bmask_notmixed_or(
; CHECK-NEXT: [[MASK1:%.*]] = and i32 [[A:%.*]], 15 ; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[A:%.*]], 15
; CHECK-NEXT: [[TST1:%.*]] = icmp eq i32 [[MASK1]], 3 ; CHECK-NEXT: [[RES:%.*]] = icmp eq i32 [[TMP1]], 3
; CHECK-NEXT: [[MASK2:%.*]] = and i32 [[A]], 255
; CHECK-NEXT: [[TST2:%.*]] = icmp eq i32 [[MASK2]], 243
; CHECK-NEXT: [[RES:%.*]] = or i1 [[TST1]], [[TST2]]
; CHECK-NEXT: ret i1 [[RES]] ; CHECK-NEXT: ret i1 [[RES]]
; ;
%mask1 = and i32 %A, 15 ; 0x0f %mask1 = and i32 %A, 15 ; 0x0f
%tst1 = icmp eq i32 %mask1, 3 ; 0x03 %tst1 = icmp eq i32 %mask1, 3 ; 0x03
%mask2 = and i32 %A, 255 ; 0xff %mask2 = and i32 %A, 255 ; 0xff
%tst2 = icmp eq i32 %mask2, 243; 0xf3 %tst2 = icmp eq i32 %mask2, 243; 0xf3
%res = or i1 %tst1, %tst2 %res = or i1 %tst1, %tst2
ret i1 %res ret i1 %res
} }
define <2 x i1> @masked_icmps_bmask_notmixed_or_vec(<2 x i8> %A) { define <2 x i1> @masked_icmps_bmask_notmixed_or_vec(<2 x i8> %A) {
; CHECK-LABEL: @masked_icmps_bmask_notmixed_or_vec( ; CHECK-LABEL: @masked_icmps_bmask_notmixed_or_vec(
; CHECK-NEXT: [[MASK1:%.*]] = and <2 x i8> [[A:%.*]], <i8 15, i8 15> ; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i8> [[A:%.*]], <i8 15, i8 15>
; CHECK-NEXT: [[TST1:%.*]] = icmp eq <2 x i8> [[MASK1]], <i8 3, i8 3> ; CHECK-NEXT: [[RES:%.*]] = icmp eq <2 x i8> [[TMP1]], <i8 3, i8 3>
; CHECK-NEXT: [[TST2:%.*]] = icmp eq <2 x i8> [[A]], <i8 -13, i8 -13>
; CHECK-NEXT: [[RES:%.*]] = or <2 x i1> [[TST1]], [[TST2]]
; CHECK-NEXT: ret <2 x i1> [[RES]] ; CHECK-NEXT: ret <2 x i1> [[RES]]
; ;
%mask1 = and <2 x i8> %A, <i8 15, i8 15> ; 0x0f %mask1 = and <2 x i8> %A, <i8 15, i8 15> ; 0x0f
%tst1 = icmp eq <2 x i8> %mask1, <i8 3, i8 3> ; 0x03 %tst1 = icmp eq <2 x i8> %mask1, <i8 3, i8 3> ; 0x03
%mask2 = and <2 x i8> %A, <i8 255, i8 255> ; 0xff %mask2 = and <2 x i8> %A, <i8 255, i8 255> ; 0xff
%tst2 = icmp eq <2 x i8> %mask2, <i8 243, i8 243> ; 0xf3 %tst2 = icmp eq <2 x i8> %mask2, <i8 243, i8 243> ; 0xf3
%res = or <2 x i1> %tst1, %tst2 %res = or <2 x i1> %tst1, %tst2
ret <2 x i1> %res ret <2 x i1> %res
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%mask2 = and i32 %A, 255 ; 0xff %mask2 = and i32 %A, 255 ; 0xff
%tst2 = icmp eq i32 %mask2, 242; 0xf2 %tst2 = icmp eq i32 %mask2, 242; 0xf2
%res = or i1 %tst1, %tst2 %res = or i1 %tst1, %tst2
ret i1 %res ret i1 %res
} }
define i1 @masked_icmps_bmask_notmixed_and(i32 %A) { define i1 @masked_icmps_bmask_notmixed_and(i32 %A) {
; CHECK-LABEL: @masked_icmps_bmask_notmixed_and( ; CHECK-LABEL: @masked_icmps_bmask_notmixed_and(
; CHECK-NEXT: [[MASK1:%.*]] = and i32 [[A:%.*]], 15 ; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[A:%.*]], 15
; CHECK-NEXT: [[TST1:%.*]] = icmp ne i32 [[MASK1]], 3 ; CHECK-NEXT: [[RES:%.*]] = icmp ne i32 [[TMP1]], 3
; CHECK-NEXT: [[MASK2:%.*]] = and i32 [[A]], 255
; CHECK-NEXT: [[TST2:%.*]] = icmp ne i32 [[MASK2]], 243
; CHECK-NEXT: [[RES:%.*]] = and i1 [[TST1]], [[TST2]]
; CHECK-NEXT: ret i1 [[RES]] ; CHECK-NEXT: ret i1 [[RES]]
; ;
%mask1 = and i32 %A, 15 ; 0x0f %mask1 = and i32 %A, 15 ; 0x0f
%tst1 = icmp ne i32 %mask1, 3 ; 0x03 %tst1 = icmp ne i32 %mask1, 3 ; 0x03
%mask2 = and i32 %A, 255 ; 0xff %mask2 = and i32 %A, 255 ; 0xff
%tst2 = icmp ne i32 %mask2, 243 ; 0xf3 %tst2 = icmp ne i32 %mask2, 243 ; 0xf3
%res = and i1 %tst1, %tst2 %res = and i1 %tst1, %tst2
ret i1 %res ret i1 %res
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