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llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
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| Show First 20 Lines • Show All 341 Lines • ▼ Show 20 Lines | public: | ||||
| bool isSDWAFP32Operand() const; | bool isSDWAFP32Operand() const; | ||||
| bool isSDWAInt16Operand() const; | bool isSDWAInt16Operand() const; | ||||
| bool isSDWAInt32Operand() const; | bool isSDWAInt32Operand() const; | ||||
| bool isImmTy(ImmTy ImmT) const { | bool isImmTy(ImmTy ImmT) const { | ||||
| return isImm() && Imm.Type == ImmT; | return isImm() && Imm.Type == ImmT; | ||||
| } | } | ||||
| bool isImmLiteral() const { return isImmTy(ImmTyNone); } | |||||
| bool isImmModifier() const { | bool isImmModifier() const { | ||||
| return isImm() && Imm.Type != ImmTyNone; | return isImm() && Imm.Type != ImmTyNone; | ||||
| } | } | ||||
| bool isClampSI() const { return isImmTy(ImmTyClampSI); } | bool isClampSI() const { return isImmTy(ImmTyClampSI); } | ||||
| bool isOModSI() const { return isImmTy(ImmTyOModSI); } | bool isOModSI() const { return isImmTy(ImmTyOModSI); } | ||||
| bool isDMask() const { return isImmTy(ImmTyDMask); } | bool isDMask() const { return isImmTy(ImmTyDMask); } | ||||
| bool isDim() const { return isImmTy(ImmTyDim); } | bool isDim() const { return isImmTy(ImmTyDim); } | ||||
| ▲ Show 20 Lines • Show All 7,577 Lines • ▼ Show 20 Lines | void AMDGPUAsmParser::cvtIntersectRay(MCInst &Inst, | ||||
| Inst.addOperand(MCOperand::createImm(1)); // a16 | Inst.addOperand(MCOperand::createImm(1)); // a16 | ||||
| } | } | ||||
| //===----------------------------------------------------------------------===// | //===----------------------------------------------------------------------===// | ||||
| // smrd | // smrd | ||||
| //===----------------------------------------------------------------------===// | //===----------------------------------------------------------------------===// | ||||
| bool AMDGPUOperand::isSMRDOffset8() const { | bool AMDGPUOperand::isSMRDOffset8() const { | ||||
| return isImm() && isUInt<8>(getImm()); | return isImmLiteral() && isUInt<8>(getImm()); | ||||
| } | } | ||||
| bool AMDGPUOperand::isSMEMOffset() const { | bool AMDGPUOperand::isSMEMOffset() const { | ||||
| return isImmTy(ImmTyNone) || | return isImmTy(ImmTyNone) || | ||||
| isImmTy(ImmTyOffset); // Offset range is checked later by validator. | isImmTy(ImmTyOffset); // Offset range is checked later by validator. | ||||
| } | } | ||||
| bool AMDGPUOperand::isSMRDLiteralOffset() const { | bool AMDGPUOperand::isSMRDLiteralOffset() const { | ||||
| // 32-bit literals are only supported on CI and we only want to use them | // 32-bit literals are only supported on CI and we only want to use them | ||||
| // when the offset is > 8-bits. | // when the offset is > 8-bits. | ||||
| return isImm() && !isUInt<8>(getImm()) && isUInt<32>(getImm()); | return isImmLiteral() && !isUInt<8>(getImm()) && isUInt<32>(getImm()); | ||||
| } | } | ||||
| AMDGPUOperand::Ptr AMDGPUAsmParser::defaultSMRDOffset8() const { | AMDGPUOperand::Ptr AMDGPUAsmParser::defaultSMRDOffset8() const { | ||||
| return AMDGPUOperand::CreateImm(this, 0, SMLoc(), AMDGPUOperand::ImmTyOffset); | return AMDGPUOperand::CreateImm(this, 0, SMLoc(), AMDGPUOperand::ImmTyOffset); | ||||
| } | } | ||||
| AMDGPUOperand::Ptr AMDGPUAsmParser::defaultSMEMOffset() const { | AMDGPUOperand::Ptr AMDGPUAsmParser::defaultSMEMOffset() const { | ||||
| return AMDGPUOperand::CreateImm(this, 0, SMLoc(), AMDGPUOperand::ImmTyOffset); | return AMDGPUOperand::CreateImm(this, 0, SMLoc(), AMDGPUOperand::ImmTyOffset); | ||||
| ▲ Show 20 Lines • Show All 471 Lines • ▼ Show 20 Lines | bool AMDGPUOperand::isCBSZ() const { | ||||
| return isImm() && getImmTy() == ImmTyCBSZ && isUInt<3>(getImm()); | return isImm() && getImmTy() == ImmTyCBSZ && isUInt<3>(getImm()); | ||||
| } | } | ||||
| bool AMDGPUOperand::isABID() const { | bool AMDGPUOperand::isABID() const { | ||||
| return isImm() && getImmTy() == ImmTyABID && isUInt<4>(getImm()); | return isImm() && getImmTy() == ImmTyABID && isUInt<4>(getImm()); | ||||
| } | } | ||||
| bool AMDGPUOperand::isS16Imm() const { | bool AMDGPUOperand::isS16Imm() const { | ||||
| return isImm() && (isInt<16>(getImm()) || isUInt<16>(getImm())); | return isImmLiteral() && (isInt<16>(getImm()) || isUInt<16>(getImm())); | ||||
| } | } | ||||
| bool AMDGPUOperand::isU16Imm() const { | bool AMDGPUOperand::isU16Imm() const { | ||||
| return isImm() && isUInt<16>(getImm()); | return isImmLiteral() && isUInt<16>(getImm()); | ||||
| } | } | ||||
| //===----------------------------------------------------------------------===// | //===----------------------------------------------------------------------===// | ||||
| // dim | // dim | ||||
| //===----------------------------------------------------------------------===// | //===----------------------------------------------------------------------===// | ||||
| bool AMDGPUAsmParser::parseDimId(unsigned &Encoding) { | bool AMDGPUAsmParser::parseDimId(unsigned &Encoding) { | ||||
| // We want to allow "dim:1D" etc., | // We want to allow "dim:1D" etc., | ||||
| ▲ Show 20 Lines • Show All 807 Lines • Show Last 20 Lines | |||||