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Differential D143252 Diff 495466 llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp

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llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp

Show First 20 Lines • Show All 753 Lines • ▼ Show 20 Lines if (!MO.isReg())
return true; return true;
Register Reg = MO.getReg(); Register Reg = MO.getReg();
Register PhysReg = Reg.isPhysical() ? Reg : Register(VRM->getPhys(Reg)); Register PhysReg = Reg.isPhysical() ? Reg : Register(VRM->getPhys(Reg));
return PhysReg && RISCV::GPRCRegClass.contains(PhysReg); return PhysReg && RISCV::GPRCRegClass.contains(PhysReg);
}; };
for (auto &MO : MRI->reg_nodbg_operands(VirtReg)) { for (auto &MO : MRI->reg_nodbg_operands(VirtReg)) {
const MachineInstr &MI = *MO.getParent(); const MachineInstr &MI = *MO.getParent();
unsigned OpIdx = MI.getOperandNo(&MO); unsigned OpIdx = MO.getOperandNo();
bool NeedGPRC; bool NeedGPRC;
if (isCompressible(MI, NeedGPRC)) { if (isCompressible(MI, NeedGPRC)) {
if (OpIdx == 0 && MI.getOperand(1).isReg()) { if (OpIdx == 0 && MI.getOperand(1).isReg()) {
if (!NeedGPRC || isCompressibleOpnd(MI.getOperand(2))) if (!NeedGPRC || isCompressibleOpnd(MI.getOperand(2)))
tryAddHint(MO, MI.getOperand(1), NeedGPRC); tryAddHint(MO, MI.getOperand(1), NeedGPRC);
if (MI.isCommutable() && MI.getOperand(2).isReg() && if (MI.isCommutable() && MI.getOperand(2).isReg() &&
(!NeedGPRC || isCompressibleOpnd(MI.getOperand(1)))) (!NeedGPRC || isCompressibleOpnd(MI.getOperand(1))))
tryAddHint(MO, MI.getOperand(2), NeedGPRC); tryAddHint(MO, MI.getOperand(2), NeedGPRC);
Show All 16 Lines