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Differential D143252 Diff 495466 llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp

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llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp

Show First 20 Lines • Show All 901 Lines • ▼ Show 20 Linesstatic bool producesFalseLanesZero(MachineInstr &MI,
bool AllowScalars = isHorizontalReduction(MI); bool AllowScalars = isHorizontalReduction(MI);
for (auto &MO : MI.operands()) { for (auto &MO : MI.operands()) {
if (!MO.isReg() || !MO.getReg()) if (!MO.isReg() || !MO.getReg())
continue; continue;
if (!isRegInClass(MO, QPRs) && AllowScalars) if (!isRegInClass(MO, QPRs) && AllowScalars)
continue; continue;
// Skip the lr predicate reg // Skip the lr predicate reg
int PIdx = llvm::findFirstVPTPredOperandIdx(MI); int PIdx = llvm::findFirstVPTPredOperandIdx(MI);
if (PIdx != -1 && (int)MI.getOperandNo(&MO) == PIdx + 2) if (PIdx != -1 && (int)MO.getOperandNo() == PIdx + 2)
continue; continue;
// Check that this instruction will produce zeros in its false lanes: // Check that this instruction will produce zeros in its false lanes:
// - If it only consumes false lanes zero or constant 0 (vmov #0) // - If it only consumes false lanes zero or constant 0 (vmov #0)
// - If it's predicated, it only matters that it's def register already has // - If it's predicated, it only matters that it's def register already has
// false lane zeros, so we can ignore the uses. // false lane zeros, so we can ignore the uses.
SmallPtrSet<MachineInstr *, 2> Defs; SmallPtrSet<MachineInstr *, 2> Defs;
RDA.getGlobalReachingDefs(&MI, MO.getReg(), Defs); RDA.getGlobalReachingDefs(&MI, MO.getReg(), Defs);
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