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llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
| Show First 20 Lines • Show All 155 Lines • ▼ Show 20 Lines | if (MO.isReg()) { | ||||
| return false; | return false; | ||||
| } | } | ||||
| } | } | ||||
| return true; | return true; | ||||
| } | } | ||||
| bool SIShrinkInstructions::isKImmOperand(const MachineOperand &Src) const { | bool SIShrinkInstructions::isKImmOperand(const MachineOperand &Src) const { | ||||
| return isInt<16>(Src.getImm()) && | return isInt<16>(Src.getImm()) && | ||||
| !TII->isInlineConstant(*Src.getParent(), | !TII->isInlineConstant(*Src.getParent(), Src.getOperandNo()); | ||||
| Src.getParent()->getOperandNo(&Src)); | |||||
| } | } | ||||
| bool SIShrinkInstructions::isKUImmOperand(const MachineOperand &Src) const { | bool SIShrinkInstructions::isKUImmOperand(const MachineOperand &Src) const { | ||||
| return isUInt<16>(Src.getImm()) && | return isUInt<16>(Src.getImm()) && | ||||
| !TII->isInlineConstant(*Src.getParent(), | !TII->isInlineConstant(*Src.getParent(), Src.getOperandNo()); | ||||
| Src.getParent()->getOperandNo(&Src)); | |||||
| } | } | ||||
| bool SIShrinkInstructions::isKImmOrKUImmOperand(const MachineOperand &Src, | bool SIShrinkInstructions::isKImmOrKUImmOperand(const MachineOperand &Src, | ||||
| bool &IsUnsigned) const { | bool &IsUnsigned) const { | ||||
| if (isInt<16>(Src.getImm())) { | if (isInt<16>(Src.getImm())) { | ||||
| IsUnsigned = false; | IsUnsigned = false; | ||||
| return !TII->isInlineConstant(Src); | return !TII->isInlineConstant(Src); | ||||
| } | } | ||||
| ▲ Show 20 Lines • Show All 839 Lines • Show Last 20 Lines | |||||