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Differential D143252 Diff 495466 llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp

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llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp

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void SIPeepholeSDWA::legalizeScalarOperands(MachineInstr &MI, void SIPeepholeSDWA::legalizeScalarOperands(MachineInstr &MI,
const GCNSubtarget &ST) const { const GCNSubtarget &ST) const {
const MCInstrDesc &Desc = TII->get(MI.getOpcode()); const MCInstrDesc &Desc = TII->get(MI.getOpcode());
unsigned ConstantBusCount = 0; unsigned ConstantBusCount = 0;
for (MachineOperand &Op : MI.explicit_uses()) { for (MachineOperand &Op : MI.explicit_uses()) {
if (!Op.isImm() && !(Op.isReg() && !TRI->isVGPR(*MRI, Op.getReg()))) if (!Op.isImm() && !(Op.isReg() && !TRI->isVGPR(*MRI, Op.getReg())))
continue; continue;
unsigned I = MI.getOperandNo(&Op); unsigned I = Op.getOperandNo();
if (Desc.operands()[I].RegClass == -1 || if (Desc.operands()[I].RegClass == -1 ||
!TRI->isVSSuperClass(TRI->getRegClass(Desc.operands()[I].RegClass))) !TRI->isVSSuperClass(TRI->getRegClass(Desc.operands()[I].RegClass)))
continue; continue;
if (ST.hasSDWAScalar() && ConstantBusCount == 0 && Op.isReg() && if (ST.hasSDWAScalar() && ConstantBusCount == 0 && Op.isReg() &&
TRI->isSGPRReg(*MRI, Op.getReg())) { TRI->isSGPRReg(*MRI, Op.getReg())) {
++ConstantBusCount; ++ConstantBusCount;
continue; continue;
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