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llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
| Show First 20 Lines • Show All 225 Lines • ▼ Show 20 Lines | static bool tryChangeVGPRtoSGPRinCopy(MachineInstr &MI, | ||||
| for (const auto &MO : MRI.reg_nodbg_operands(DstReg)) { | for (const auto &MO : MRI.reg_nodbg_operands(DstReg)) { | ||||
| const auto *UseMI = MO.getParent(); | const auto *UseMI = MO.getParent(); | ||||
| if (UseMI == &MI) | if (UseMI == &MI) | ||||
| continue; | continue; | ||||
| if (MO.isDef() || UseMI->getParent() != MI.getParent() || | if (MO.isDef() || UseMI->getParent() != MI.getParent() || | ||||
| UseMI->getOpcode() <= TargetOpcode::GENERIC_OP_END) | UseMI->getOpcode() <= TargetOpcode::GENERIC_OP_END) | ||||
| return false; | return false; | ||||
| unsigned OpIdx = UseMI->getOperandNo(&MO); | unsigned OpIdx = MO.getOperandNo(); | ||||
| if (OpIdx >= UseMI->getDesc().getNumOperands() || | if (OpIdx >= UseMI->getDesc().getNumOperands() || | ||||
| !TII->isOperandLegal(*UseMI, OpIdx, &Src)) | !TII->isOperandLegal(*UseMI, OpIdx, &Src)) | ||||
| return false; | return false; | ||||
| } | } | ||||
| // Change VGPR to SGPR destination. | // Change VGPR to SGPR destination. | ||||
| MRI.setRegClass(DstReg, TRI->getEquivalentSGPRClass(MRI.getRegClass(DstReg))); | MRI.setRegClass(DstReg, TRI->getEquivalentSGPRClass(MRI.getRegClass(DstReg))); | ||||
| return true; | return true; | ||||
| } | } | ||||
| ▲ Show 20 Lines • Show All 410 Lines • ▼ Show 20 Lines | for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); I != E; | ||||
| if (!MO.isReg() || !MO.getReg().isVirtual()) | if (!MO.isReg() || !MO.getReg().isVirtual()) | ||||
| continue; | continue; | ||||
| const TargetRegisterClass *SrcRC = MRI->getRegClass(MO.getReg()); | const TargetRegisterClass *SrcRC = MRI->getRegClass(MO.getReg()); | ||||
| if (TRI->hasVectorRegisters(SrcRC)) { | if (TRI->hasVectorRegisters(SrcRC)) { | ||||
| const TargetRegisterClass *DestRC = | const TargetRegisterClass *DestRC = | ||||
| TRI->getEquivalentSGPRClass(SrcRC); | TRI->getEquivalentSGPRClass(SrcRC); | ||||
| Register NewDst = MRI->createVirtualRegister(DestRC); | Register NewDst = MRI->createVirtualRegister(DestRC); | ||||
| MachineBasicBlock *BlockToInsertCopy = | MachineBasicBlock *BlockToInsertCopy = | ||||
| MI.isPHI() ? MI.getOperand(MI.getOperandNo(&MO) + 1).getMBB() | MI.isPHI() ? MI.getOperand(MO.getOperandNo() + 1).getMBB() | ||||
| : MBB; | : MBB; | ||||
| MachineBasicBlock::iterator PointToInsertCopy = | MachineBasicBlock::iterator PointToInsertCopy = | ||||
| MI.isPHI() ? BlockToInsertCopy->getFirstInstrTerminator() : I; | MI.isPHI() ? BlockToInsertCopy->getFirstInstrTerminator() : I; | ||||
| MachineInstr *NewCopy = | MachineInstr *NewCopy = | ||||
| BuildMI(*BlockToInsertCopy, PointToInsertCopy, | BuildMI(*BlockToInsertCopy, PointToInsertCopy, | ||||
| PointToInsertCopy->getDebugLoc(), | PointToInsertCopy->getDebugLoc(), | ||||
| TII->get(AMDGPU::COPY), NewDst) | TII->get(AMDGPU::COPY), NewDst) | ||||
| .addReg(MO.getReg()); | .addReg(MO.getReg()); | ||||
| ▲ Show 20 Lines • Show All 437 Lines • Show Last 20 Lines | |||||