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Differential D143256 Diff 495447 llvm/test/CodeGen/ARM/minnum-maxnum-intrinsics.ll

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llvm/test/CodeGen/ARM/minnum-maxnum-intrinsics.ll

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; ARMV8M-NEXT: bx lr ; ARMV8M-NEXT: bx lr
%a = call nnan double @llvm.maxnum.f64(double %x, double 1.0) %a = call nnan double @llvm.maxnum.f64(double %x, double 1.0)
ret double %a ret double %a
} }
define <4 x float> @fminnumv432_intrinsic(<4 x float> %x, <4 x float> %y) { define <4 x float> @fminnumv432_intrinsic(<4 x float> %x, <4 x float> %y) {
; ARMV7-LABEL: fminnumv432_intrinsic: ; ARMV7-LABEL: fminnumv432_intrinsic:
; ARMV7: @ %bb.0: ; ARMV7: @ %bb.0:
; ARMV7-NEXT: vmov d17, r2, r3 ; ARMV7-NEXT: mov r12, sp
; ARMV7-NEXT: vmov d16, r0, r1 ; ARMV7-NEXT: vld1.64 {d0, d1}, [r12]
; ARMV7-NEXT: mov r0, sp ; ARMV7-NEXT: vmov d3, r2, r3
; ARMV7-NEXT: vld1.64 {d18, d19}, [r0] ; ARMV7-NEXT: vmov d2, r0, r1
; ARMV7-NEXT: vmin.f32 q8, q8, q9 ; ARMV7-NEXT: vcmp.f32 s7, s3
; ARMV7-NEXT: vmov r0, r1, d16 ; ARMV7-NEXT: vmrs APSR_nzcv, fpscr
; ARMV7-NEXT: vmov r2, r3, d17 ; ARMV7-NEXT: vcmp.f32 s6, s2
; ARMV7-NEXT: vmovlt.f32 s3, s7
; ARMV7-NEXT: vmrs APSR_nzcv, fpscr
; ARMV7-NEXT: vcmp.f32 s5, s1
; ARMV7-NEXT: vmovlt.f32 s2, s6
; ARMV7-NEXT: vmrs APSR_nzcv, fpscr
; ARMV7-NEXT: vcmp.f32 s4, s0
; ARMV7-NEXT: vmovlt.f32 s1, s5
; ARMV7-NEXT: vmrs APSR_nzcv, fpscr
; ARMV7-NEXT: vmovlt.f32 s0, s4
; ARMV7-NEXT: vmov r2, r3, d1
; ARMV7-NEXT: vmov r0, r1, d0
; ARMV7-NEXT: bx lr ; ARMV7-NEXT: bx lr
; ;
; ARMV8-LABEL: fminnumv432_intrinsic: ; ARMV8-LABEL: fminnumv432_intrinsic:
; ARMV8: @ %bb.0: ; ARMV8: @ %bb.0:
; ARMV8-NEXT: vldr s0, [sp, #4] ; ARMV8-NEXT: vldr s0, [sp, #4]
; ARMV8-NEXT: vmov s12, r1 ; ARMV8-NEXT: vmov s12, r1
; ARMV8-NEXT: vldr s2, [sp, #8] ; ARMV8-NEXT: vldr s2, [sp, #8]
; ARMV8-NEXT: vmov s10, r2 ; ARMV8-NEXT: vmov s10, r2
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; ARMV8M-NEXT: bx lr ; ARMV8M-NEXT: bx lr
%a = call nnan <4 x float> @llvm.minnum.v4f32(<4 x float> %x, <4 x float><float -1.0, float -1.0, float -1.0, float -1.0>) %a = call nnan <4 x float> @llvm.minnum.v4f32(<4 x float> %x, <4 x float><float -1.0, float -1.0, float -1.0, float -1.0>)
ret <4 x float> %a ret <4 x float> %a
} }
define <4 x float> @fminnumv432_one_zero_intrinsic(<4 x float> %x) { define <4 x float> @fminnumv432_one_zero_intrinsic(<4 x float> %x) {
; ARMV7-LABEL: fminnumv432_one_zero_intrinsic: ; ARMV7-LABEL: fminnumv432_one_zero_intrinsic:
; ARMV7: @ %bb.0: ; ARMV7: @ %bb.0:
; ARMV7-NEXT: vmov d17, r2, r3 ; ARMV7-NEXT: vmov d3, r2, r3
; ARMV7-NEXT: vmov d16, r0, r1 ; ARMV7-NEXT: vmov d2, r0, r1
; ARMV7-NEXT: adr r0, .LCPI18_0 ; ARMV7-NEXT: vmov.f32 s0, #-1.000000e+00
; ARMV7-NEXT: vld1.64 {d18, d19}, [r0:128] ; ARMV7-NEXT: vcmp.f32 s5, #0
; ARMV7-NEXT: vmin.f32 q8, q8, q9 ; ARMV7-NEXT: vldr s1, .LCPI18_0
; ARMV7-NEXT: vmov r0, r1, d16 ; ARMV7-NEXT: vmrs APSR_nzcv, fpscr
; ARMV7-NEXT: vmov r2, r3, d17 ; ARMV7-NEXT: vcmp.f32 s7, s0
; ARMV7-NEXT: vmovlt.f32 s1, s5
; ARMV7-NEXT: vmrs APSR_nzcv, fpscr
; ARMV7-NEXT: vmov.f32 s3, s0
; ARMV7-NEXT: vcmp.f32 s6, s0
; ARMV7-NEXT: vmovlt.f32 s3, s7
; ARMV7-NEXT: vmrs APSR_nzcv, fpscr
; ARMV7-NEXT: vmov.f32 s2, s0
; ARMV7-NEXT: vcmp.f32 s4, s0
; ARMV7-NEXT: vmovlt.f32 s2, s6
; ARMV7-NEXT: vmrs APSR_nzcv, fpscr
; ARMV7-NEXT: vmovlt.f32 s0, s4
; ARMV7-NEXT: vmov r2, r3, d1
; ARMV7-NEXT: vmov r0, r1, d0
; ARMV7-NEXT: bx lr ; ARMV7-NEXT: bx lr
; ARMV7-NEXT: .p2align 4 ; ARMV7-NEXT: .p2align 2
; ARMV7-NEXT: @ %bb.1: ; ARMV7-NEXT: @ %bb.1:
; ARMV7-NEXT: .LCPI18_0: ; ARMV7-NEXT: .LCPI18_0:
; ARMV7-NEXT: .long 0xbf800000 @ float -1
; ARMV7-NEXT: .long 0x00000000 @ float 0 ; ARMV7-NEXT: .long 0x00000000 @ float 0
; ARMV7-NEXT: .long 0xbf800000 @ float -1
; ARMV7-NEXT: .long 0xbf800000 @ float -1
; ;
; ARMV8-LABEL: fminnumv432_one_zero_intrinsic: ; ARMV8-LABEL: fminnumv432_one_zero_intrinsic:
; ARMV8: @ %bb.0: ; ARMV8: @ %bb.0:
; ARMV8-NEXT: vldr s0, .LCPI18_0 ; ARMV8-NEXT: vldr s0, .LCPI18_0
; ARMV8-NEXT: vmov s8, r1 ; ARMV8-NEXT: vmov s8, r1
; ARMV8-NEXT: vmov.f32 s2, #-1.000000e+00 ; ARMV8-NEXT: vmov.f32 s2, #-1.000000e+00
; ARMV8-NEXT: vminnm.f32 s0, s8, s0 ; ARMV8-NEXT: vminnm.f32 s0, s8, s0
; ARMV8-NEXT: vmov s6, r2 ; ARMV8-NEXT: vmov s6, r2
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; ARMV8M-NEXT: .long 0xbf800000 @ float -1 ; ARMV8M-NEXT: .long 0xbf800000 @ float -1
%a = call nnan <4 x float> @llvm.minnum.v4f32(<4 x float> %x, <4 x float><float -1.0, float 0.0, float -1.0, float -1.0>) %a = call nnan <4 x float> @llvm.minnum.v4f32(<4 x float> %x, <4 x float><float -1.0, float 0.0, float -1.0, float -1.0>)
ret <4 x float> %a ret <4 x float> %a
} }
define <4 x float> @fmaxnumv432_intrinsic(<4 x float> %x, <4 x float> %y) { define <4 x float> @fmaxnumv432_intrinsic(<4 x float> %x, <4 x float> %y) {
; ARMV7-LABEL: fmaxnumv432_intrinsic: ; ARMV7-LABEL: fmaxnumv432_intrinsic:
; ARMV7: @ %bb.0: ; ARMV7: @ %bb.0:
; ARMV7-NEXT: vmov d17, r2, r3 ; ARMV7-NEXT: mov r12, sp
; ARMV7-NEXT: vmov d16, r0, r1 ; ARMV7-NEXT: vld1.64 {d0, d1}, [r12]
; ARMV7-NEXT: mov r0, sp ; ARMV7-NEXT: vmov d3, r2, r3
; ARMV7-NEXT: vld1.64 {d18, d19}, [r0] ; ARMV7-NEXT: vmov d2, r0, r1
; ARMV7-NEXT: vmax.f32 q8, q8, q9 ; ARMV7-NEXT: vcmp.f32 s7, s3
; ARMV7-NEXT: vmov r0, r1, d16 ; ARMV7-NEXT: vmrs APSR_nzcv, fpscr
; ARMV7-NEXT: vmov r2, r3, d17 ; ARMV7-NEXT: vcmp.f32 s6, s2
; ARMV7-NEXT: vmovgt.f32 s3, s7
; ARMV7-NEXT: vmrs APSR_nzcv, fpscr
; ARMV7-NEXT: vcmp.f32 s5, s1
; ARMV7-NEXT: vmovgt.f32 s2, s6
; ARMV7-NEXT: vmrs APSR_nzcv, fpscr
; ARMV7-NEXT: vcmp.f32 s4, s0
; ARMV7-NEXT: vmovgt.f32 s1, s5
; ARMV7-NEXT: vmrs APSR_nzcv, fpscr
; ARMV7-NEXT: vmovgt.f32 s0, s4
; ARMV7-NEXT: vmov r2, r3, d1
; ARMV7-NEXT: vmov r0, r1, d0
; ARMV7-NEXT: bx lr ; ARMV7-NEXT: bx lr
; ;
; ARMV8-LABEL: fmaxnumv432_intrinsic: ; ARMV8-LABEL: fmaxnumv432_intrinsic:
; ARMV8: @ %bb.0: ; ARMV8: @ %bb.0:
; ARMV8-NEXT: vldr s0, [sp, #4] ; ARMV8-NEXT: vldr s0, [sp, #4]
; ARMV8-NEXT: vmov s12, r1 ; ARMV8-NEXT: vmov s12, r1
; ARMV8-NEXT: vldr s2, [sp, #8] ; ARMV8-NEXT: vldr s2, [sp, #8]
; ARMV8-NEXT: vmov s10, r2 ; ARMV8-NEXT: vmov s10, r2
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; ARMV8M-NEXT: bx lr ; ARMV8M-NEXT: bx lr
%a = call nnan nsz <4 x float> @llvm.maxnum.v4f32(<4 x float> %x, <4 x float> %y) %a = call nnan nsz <4 x float> @llvm.maxnum.v4f32(<4 x float> %x, <4 x float> %y)
ret <4 x float> %a ret <4 x float> %a
} }
define <4 x float> @fmaxnumv432_zero_intrinsic(<4 x float> %x) { define <4 x float> @fmaxnumv432_zero_intrinsic(<4 x float> %x) {
; ARMV7-LABEL: fmaxnumv432_zero_intrinsic: ; ARMV7-LABEL: fmaxnumv432_zero_intrinsic:
; ARMV7: @ %bb.0: ; ARMV7: @ %bb.0:
; ARMV7-NEXT: vmov d19, r2, r3 ; ARMV7-NEXT: vmov d3, r2, r3
; ARMV7-NEXT: vmov.i32 q8, #0x0 ; ARMV7-NEXT: vldr s0, .LCPI21_0
; ARMV7-NEXT: vmov d18, r0, r1 ; ARMV7-NEXT: vmov d2, r0, r1
; ARMV7-NEXT: vmax.f32 q8, q9, q8 ; ARMV7-NEXT: vcmp.f32 s7, #0
; ARMV7-NEXT: vmov r0, r1, d16 ; ARMV7-NEXT: vmrs APSR_nzcv, fpscr
; ARMV7-NEXT: vmov r2, r3, d17 ; ARMV7-NEXT: vmov.f32 s3, s0
; ARMV7-NEXT: vcmp.f32 s6, #0
; ARMV7-NEXT: vmovgt.f32 s3, s7
; ARMV7-NEXT: vmrs APSR_nzcv, fpscr
; ARMV7-NEXT: vmov.f32 s2, s0
; ARMV7-NEXT: vcmp.f32 s5, #0
; ARMV7-NEXT: vmovgt.f32 s2, s6
; ARMV7-NEXT: vmrs APSR_nzcv, fpscr
; ARMV7-NEXT: vmov.f32 s1, s0
; ARMV7-NEXT: vcmp.f32 s4, #0
; ARMV7-NEXT: vmovgt.f32 s1, s5
; ARMV7-NEXT: vmrs APSR_nzcv, fpscr
; ARMV7-NEXT: vmovgt.f32 s0, s4
; ARMV7-NEXT: vmov r2, r3, d1
; ARMV7-NEXT: vmov r0, r1, d0
; ARMV7-NEXT: bx lr ; ARMV7-NEXT: bx lr
; ARMV7-NEXT: .p2align 2
; ARMV7-NEXT: @ %bb.1:
; ARMV7-NEXT: .LCPI21_0:
; ARMV7-NEXT: .long 0x00000000 @ float 0
; ;
; ARMV8-LABEL: fmaxnumv432_zero_intrinsic: ; ARMV8-LABEL: fmaxnumv432_zero_intrinsic:
; ARMV8: @ %bb.0: ; ARMV8: @ %bb.0:
; ARMV8-NEXT: vldr s0, .LCPI21_0 ; ARMV8-NEXT: vldr s0, .LCPI21_0
; ARMV8-NEXT: vmov s4, r2 ; ARMV8-NEXT: vmov s4, r2
; ARMV8-NEXT: vmov s6, r1 ; ARMV8-NEXT: vmov s6, r1
; ARMV8-NEXT: vmov s8, r0 ; ARMV8-NEXT: vmov s8, r0
; ARMV8-NEXT: vmaxnm.f32 s6, s6, s0 ; ARMV8-NEXT: vmaxnm.f32 s6, s6, s0
Show All 22 Lines
; ARMV8M-NEXT: bx lr ; ARMV8M-NEXT: bx lr
%a = call nnan <4 x float> @llvm.maxnum.v4f32(<4 x float> %x, <4 x float><float 0.0, float 0.0, float 0.0, float 0.0>) %a = call nnan <4 x float> @llvm.maxnum.v4f32(<4 x float> %x, <4 x float><float 0.0, float 0.0, float 0.0, float 0.0>)
ret <4 x float> %a ret <4 x float> %a
} }
define <4 x float> @fmaxnumv432_minus_zero_intrinsic(<4 x float> %x) { define <4 x float> @fmaxnumv432_minus_zero_intrinsic(<4 x float> %x) {
; ARMV7-LABEL: fmaxnumv432_minus_zero_intrinsic: ; ARMV7-LABEL: fmaxnumv432_minus_zero_intrinsic:
; ARMV7: @ %bb.0: ; ARMV7: @ %bb.0:
; ARMV7-NEXT: vmov d19, r2, r3 ; ARMV7-NEXT: vldr s0, .LCPI22_0
; ARMV7-NEXT: vmov.i32 q8, #0x80000000 ; ARMV7-NEXT: vmov d3, r2, r3
; ARMV7-NEXT: vmov d18, r0, r1 ; ARMV7-NEXT: vmov d2, r0, r1
; ARMV7-NEXT: vmax.f32 q8, q9, q8 ; ARMV7-NEXT: vcmp.f32 s7, s0
; ARMV7-NEXT: vmov r0, r1, d16 ; ARMV7-NEXT: vmrs APSR_nzcv, fpscr
; ARMV7-NEXT: vmov r2, r3, d17 ; ARMV7-NEXT: vmov.f32 s3, s0
; ARMV7-NEXT: vcmp.f32 s6, s0
; ARMV7-NEXT: vmovgt.f32 s3, s7
; ARMV7-NEXT: vmrs APSR_nzcv, fpscr
; ARMV7-NEXT: vmov.f32 s2, s0
; ARMV7-NEXT: vcmp.f32 s5, s0
; ARMV7-NEXT: vmovgt.f32 s2, s6
; ARMV7-NEXT: vmrs APSR_nzcv, fpscr
; ARMV7-NEXT: vmov.f32 s1, s0
; ARMV7-NEXT: vcmp.f32 s4, s0
; ARMV7-NEXT: vmovgt.f32 s1, s5
; ARMV7-NEXT: vmrs APSR_nzcv, fpscr
; ARMV7-NEXT: vmovgt.f32 s0, s4
; ARMV7-NEXT: vmov r2, r3, d1
; ARMV7-NEXT: vmov r0, r1, d0
; ARMV7-NEXT: bx lr ; ARMV7-NEXT: bx lr
; ARMV7-NEXT: .p2align 2
; ARMV7-NEXT: @ %bb.1:
; ARMV7-NEXT: .LCPI22_0:
; ARMV7-NEXT: .long 0x80000000 @ float -0
; ;
; ARMV8-LABEL: fmaxnumv432_minus_zero_intrinsic: ; ARMV8-LABEL: fmaxnumv432_minus_zero_intrinsic:
; ARMV8: @ %bb.0: ; ARMV8: @ %bb.0:
; ARMV8-NEXT: vldr s0, .LCPI22_0 ; ARMV8-NEXT: vldr s0, .LCPI22_0
; ARMV8-NEXT: vmov s4, r2 ; ARMV8-NEXT: vmov s4, r2
; ARMV8-NEXT: vmov s6, r1 ; ARMV8-NEXT: vmov s6, r1
; ARMV8-NEXT: vmov s8, r0 ; ARMV8-NEXT: vmov s8, r0
; ARMV8-NEXT: vmaxnm.f32 s6, s6, s0 ; ARMV8-NEXT: vmaxnm.f32 s6, s6, s0
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