Please use GitHub pull requests for new patches. Avoid migrating existing patches. Phabricator shutdown timeline

Differential D142891 Diff 494839 clang/unittests/Format/FormatTestVerilog.cpp

Changeset View

Standalone View

clang/unittests/Format/FormatTestVerilog.cpp

Show All 39 Lines	static void verifyFormat(
llvm::StringRef Code,		llvm::StringRef Code,
const FormatStyle &Style = getLLVMStyle(FormatStyle::LK_Verilog)) {		const FormatStyle &Style = getLLVMStyle(FormatStyle::LK_Verilog)) {
EXPECT_EQ(Code.str(), format(Code, Style)) << "Expected code is not stable";		EXPECT_EQ(Code.str(), format(Code, Style)) << "Expected code is not stable";
EXPECT_EQ(Code.str(),		EXPECT_EQ(Code.str(),
format(test::messUp(Code, /HandleHash=/false), Style));		format(test::messUp(Code, /HandleHash=/false), Style));
}		}
};		};

		TEST_F(FormatTestVerilog, Align) {
		FormatStyle Style = getLLVMStyle(FormatStyle::LK_Verilog);
		Style.AlignConsecutiveAssignments.Enabled = true;
		verifyFormat("x <= x;\n"
		"sfdbddfbdfbb <= x;\n"
		"x = x;",
		Style);
		verifyFormat("x = x;\n"
		"sfdbddfbdfbb = x;\n"
		"x = x;",
		Style);
		// Compound assignments are not aligned by default. '<=' is not a compound
		// assignment.
		verifyFormat("x <= x;\n"
		"sfdbddfbdfbb <= x;",
		Style);
		verifyFormat("x += x;\n"
		"sfdbddfbdfbb <= x;",
		Style);
		verifyFormat("x <<= x;\n"
		"sfdbddfbdfbb <= x;",
		Style);
		verifyFormat("x <<<= x;\n"
		"sfdbddfbdfbb <= x;",
		Style);
		verifyFormat("x >>= x;\n"
		"sfdbddfbdfbb <= x;",
		Style);
		verifyFormat("x >>>= x;\n"
		"sfdbddfbdfbb <= x;",
		Style);
		Style.AlignConsecutiveAssignments.AlignCompound = true;
		verifyFormat("x <= x;\n"
		"sfdbddfbdfbb <= x;",
		Style);
		verifyFormat("x += x;\n"
		"sfdbddfbdfbb <= x;",
		Style);
		verifyFormat("x <<= x;\n"
		"sfdbddfbdfbb <= x;",
		Style);
		verifyFormat("x <<<= x;\n"
		"sfdbddfbdfbb <= x;",
		Style);
		verifyFormat("x >>= x;\n"
		"sfdbddfbdfbb <= x;",
		Style);
		verifyFormat("x >>>= x;\n"
		"sfdbddfbdfbb <= x;",
		Style);
		}

TEST_F(FormatTestVerilog, BasedLiteral) {		TEST_F(FormatTestVerilog, BasedLiteral) {
verifyFormat("x = '0;");		verifyFormat("x = '0;");
verifyFormat("x = '1;");		verifyFormat("x = '1;");
verifyFormat("x = 'X;");		verifyFormat("x = 'X;");
verifyFormat("x = 'x;");		verifyFormat("x = 'x;");
verifyFormat("x = 'Z;");		verifyFormat("x = 'Z;");
verifyFormat("x = 'z;");		verifyFormat("x = 'z;");
verifyFormat("x = 659;");		verifyFormat("x = 659;");
▲ Show 20 Lines • Show All 529 Lines • Show Last 20 Lines