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llvm/test/CodeGen/AMDGPU/constrained-shift.ll
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| ; CHECK-NEXT: v_add3_u32 v1, v10, v14, v1 | ; CHECK-NEXT: v_add3_u32 v1, v10, v14, v1 | ||||
| ; CHECK-NEXT: v_add3_u32 v2, v9, v13, v2 | ; CHECK-NEXT: v_add3_u32 v2, v9, v13, v2 | ||||
| ; CHECK-NEXT: v_add3_u32 v3, v8, v12, v3 | ; CHECK-NEXT: v_add3_u32 v3, v8, v12, v3 | ||||
| ; CHECK-NEXT: s_setpc_b64 s[30:31] | ; CHECK-NEXT: s_setpc_b64 s[30:31] | ||||
| ; | ; | ||||
| ; GISEL-LABEL: csh_v4i32: | ; GISEL-LABEL: csh_v4i32: | ||||
| ; GISEL: ; %bb.0: | ; GISEL: ; %bb.0: | ||||
| ; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) | ; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) | ||||
| ; GISEL-NEXT: v_and_b32_e32 v4, 31, v4 | |||||
| ; GISEL-NEXT: v_and_b32_e32 v5, 31, v5 | |||||
| ; GISEL-NEXT: v_and_b32_e32 v6, 31, v6 | |||||
| ; GISEL-NEXT: v_and_b32_e32 v7, 31, v7 | |||||
| ; GISEL-NEXT: v_lshlrev_b32_e32 v8, v4, v0 | ; GISEL-NEXT: v_lshlrev_b32_e32 v8, v4, v0 | ||||
| ; GISEL-NEXT: v_lshlrev_b32_e32 v9, v5, v1 | ; GISEL-NEXT: v_lshlrev_b32_e32 v9, v5, v1 | ||||
| ; GISEL-NEXT: v_lshlrev_b32_e32 v10, v6, v2 | ; GISEL-NEXT: v_lshlrev_b32_e32 v10, v6, v2 | ||||
| ; GISEL-NEXT: v_lshlrev_b32_e32 v11, v7, v3 | ; GISEL-NEXT: v_lshlrev_b32_e32 v11, v7, v3 | ||||
| ; GISEL-NEXT: v_lshrrev_b32_e32 v12, v4, v0 | ; GISEL-NEXT: v_lshrrev_b32_e32 v12, v4, v0 | ||||
| ; GISEL-NEXT: v_lshrrev_b32_e32 v13, v5, v1 | ; GISEL-NEXT: v_lshrrev_b32_e32 v13, v5, v1 | ||||
| ; GISEL-NEXT: v_lshrrev_b32_e32 v14, v6, v2 | ; GISEL-NEXT: v_lshrrev_b32_e32 v14, v6, v2 | ||||
| ; GISEL-NEXT: v_lshrrev_b32_e32 v15, v7, v3 | ; GISEL-NEXT: v_lshrrev_b32_e32 v15, v7, v3 | ||||
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