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Differential D142192 Diff 491241 llvm/test/CodeGen/AMDGPU/bfi_int.ll

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llvm/test/CodeGen/AMDGPU/bfi_int.ll

Show First 20 Lines • Show All 247 Lines • ▼ Show 20 Linesentry:
%1 = and i32 %x, %0 %1 = and i32 %x, %0
%2 = xor i32 %z, %1 %2 = xor i32 %z, %1
ret i32 %2 ret i32 %2
} }
define amdgpu_ps float @v_s_s_bfi_sha256_ch(i32 %x, i32 inreg %y, i32 inreg %z) { define amdgpu_ps float @v_s_s_bfi_sha256_ch(i32 %x, i32 inreg %y, i32 inreg %z) {
; GFX7-LABEL: v_s_s_bfi_sha256_ch: ; GFX7-LABEL: v_s_s_bfi_sha256_ch:
; GFX7: ; %bb.0: ; %entry ; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: v_mov_b32_e32 v1, s1 ; GFX7-NEXT: v_mov_b32_e32 v1, s0
; GFX7-NEXT: v_bfi_b32 v0, v0, s0, v1 ; GFX7-NEXT: v_bfi_b32 v0, v0, v1, s1
; GFX7-NEXT: ; return to shader part epilog ; GFX7-NEXT: ; return to shader part epilog
; ;
; GFX8-LABEL: v_s_s_bfi_sha256_ch: ; GFX8-LABEL: v_s_s_bfi_sha256_ch:
; GFX8: ; %bb.0: ; %entry ; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: v_mov_b32_e32 v1, s1 ; GFX8-NEXT: v_mov_b32_e32 v1, s0
; GFX8-NEXT: v_bfi_b32 v0, v0, s0, v1 ; GFX8-NEXT: v_bfi_b32 v0, v0, v1, s1
; GFX8-NEXT: ; return to shader part epilog ; GFX8-NEXT: ; return to shader part epilog
; ;
; GFX10-LABEL: v_s_s_bfi_sha256_ch: ; GFX10-LABEL: v_s_s_bfi_sha256_ch:
; GFX10: ; %bb.0: ; %entry ; GFX10: ; %bb.0: ; %entry
; GFX10-NEXT: v_bfi_b32 v0, v0, s0, s1 ; GFX10-NEXT: v_bfi_b32 v0, v0, s0, s1
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
; ;
; GFX8-GISEL-LABEL: v_s_s_bfi_sha256_ch: ; GFX8-GISEL-LABEL: v_s_s_bfi_sha256_ch:
Show All 15 Linesentry:
%xor1 = xor i32 %z, %and %xor1 = xor i32 %z, %and
%cast = bitcast i32 %xor1 to float %cast = bitcast i32 %xor1 to float
ret float %cast ret float %cast
} }
define amdgpu_ps float @s_v_s_bfi_sha256_ch(i32 inreg %x, i32 %y, i32 inreg %z) { define amdgpu_ps float @s_v_s_bfi_sha256_ch(i32 inreg %x, i32 %y, i32 inreg %z) {
; GFX7-LABEL: s_v_s_bfi_sha256_ch: ; GFX7-LABEL: s_v_s_bfi_sha256_ch:
; GFX7: ; %bb.0: ; %entry ; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: v_mov_b32_e32 v1, s1 ; GFX7-NEXT: v_mov_b32_e32 v1, s0
; GFX7-NEXT: v_bfi_b32 v0, s0, v0, v1 ; GFX7-NEXT: v_bfi_b32 v0, v1, v0, s1
; GFX7-NEXT: ; return to shader part epilog ; GFX7-NEXT: ; return to shader part epilog
; ;
; GFX8-LABEL: s_v_s_bfi_sha256_ch: ; GFX8-LABEL: s_v_s_bfi_sha256_ch:
; GFX8: ; %bb.0: ; %entry ; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: v_mov_b32_e32 v1, s1 ; GFX8-NEXT: v_mov_b32_e32 v1, s0
; GFX8-NEXT: v_bfi_b32 v0, s0, v0, v1 ; GFX8-NEXT: v_bfi_b32 v0, v1, v0, s1
; GFX8-NEXT: ; return to shader part epilog ; GFX8-NEXT: ; return to shader part epilog
; ;
; GFX10-LABEL: s_v_s_bfi_sha256_ch: ; GFX10-LABEL: s_v_s_bfi_sha256_ch:
; GFX10: ; %bb.0: ; %entry ; GFX10: ; %bb.0: ; %entry
; GFX10-NEXT: v_bfi_b32 v0, s0, v0, s1 ; GFX10-NEXT: v_bfi_b32 v0, s0, v0, s1
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
; ;
; GFX8-GISEL-LABEL: s_v_s_bfi_sha256_ch: ; GFX8-GISEL-LABEL: s_v_s_bfi_sha256_ch:
Show All 15 Linesentry:
%xor1 = xor i32 %z, %and %xor1 = xor i32 %z, %and
%cast = bitcast i32 %xor1 to float %cast = bitcast i32 %xor1 to float
ret float %cast ret float %cast
} }
define amdgpu_ps float @s_s_v_bfi_sha256_ch(i32 inreg %x, i32 inreg %y, i32 %z) { define amdgpu_ps float @s_s_v_bfi_sha256_ch(i32 inreg %x, i32 inreg %y, i32 %z) {
; GFX7-LABEL: s_s_v_bfi_sha256_ch: ; GFX7-LABEL: s_s_v_bfi_sha256_ch:
; GFX7: ; %bb.0: ; %entry ; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: v_mov_b32_e32 v1, s1 ; GFX7-NEXT: v_mov_b32_e32 v1, s0
; GFX7-NEXT: v_bfi_b32 v0, s0, v1, v0 ; GFX7-NEXT: v_bfi_b32 v0, v1, s1, v0
; GFX7-NEXT: ; return to shader part epilog ; GFX7-NEXT: ; return to shader part epilog
; ;
; GFX8-LABEL: s_s_v_bfi_sha256_ch: ; GFX8-LABEL: s_s_v_bfi_sha256_ch:
; GFX8: ; %bb.0: ; %entry ; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: v_mov_b32_e32 v1, s1 ; GFX8-NEXT: v_mov_b32_e32 v1, s0
; GFX8-NEXT: v_bfi_b32 v0, s0, v1, v0 ; GFX8-NEXT: v_bfi_b32 v0, v1, s1, v0
; GFX8-NEXT: ; return to shader part epilog ; GFX8-NEXT: ; return to shader part epilog
; ;
; GFX10-LABEL: s_s_v_bfi_sha256_ch: ; GFX10-LABEL: s_s_v_bfi_sha256_ch:
; GFX10: ; %bb.0: ; %entry ; GFX10: ; %bb.0: ; %entry
; GFX10-NEXT: v_bfi_b32 v0, s0, s1, v0 ; GFX10-NEXT: v_bfi_b32 v0, s0, s1, v0
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
; ;
; GFX8-GISEL-LABEL: s_s_v_bfi_sha256_ch: ; GFX8-GISEL-LABEL: s_s_v_bfi_sha256_ch:
▲ Show 20 Lines • Show All 271 Lines • ▼ Show 20 Lines
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_bfi_b32 v0, v2, v0, v4 ; GFX10-NEXT: v_bfi_b32 v0, v2, v0, v4
; GFX10-NEXT: v_bfi_b32 v1, v3, v1, v5 ; GFX10-NEXT: v_bfi_b32 v1, v3, v1, v5
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX8-GISEL-LABEL: v_bitselect_v2i32_pat1: ; GFX8-GISEL-LABEL: v_bitselect_v2i32_pat1:
; GFX8-GISEL: ; %bb.0: ; GFX8-GISEL: ; %bb.0:
; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-GISEL-NEXT: v_xor_b32_e32 v0, v0, v4 ; GFX8-GISEL-NEXT: v_bfi_b32 v0, v2, v0, v4
; GFX8-GISEL-NEXT: v_xor_b32_e32 v1, v1, v5 ; GFX8-GISEL-NEXT: v_bfi_b32 v1, v3, v1, v5
; GFX8-GISEL-NEXT: v_and_b32_e32 v0, v0, v2
; GFX8-GISEL-NEXT: v_and_b32_e32 v1, v1, v3
; GFX8-GISEL-NEXT: v_xor_b32_e32 v0, v0, v4
; GFX8-GISEL-NEXT: v_xor_b32_e32 v1, v1, v5
; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31] ; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-GISEL-LABEL: v_bitselect_v2i32_pat1: ; GFX10-GISEL-LABEL: v_bitselect_v2i32_pat1:
; GFX10-GISEL: ; %bb.0: ; GFX10-GISEL: ; %bb.0:
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-GISEL-NEXT: v_xor_b32_e32 v0, v0, v4 ; GFX10-GISEL-NEXT: v_bfi_b32 v0, v2, v0, v4
; GFX10-GISEL-NEXT: v_xor_b32_e32 v1, v1, v5 ; GFX10-GISEL-NEXT: v_bfi_b32 v1, v3, v1, v5
; GFX10-GISEL-NEXT: v_and_b32_e32 v0, v0, v2
; GFX10-GISEL-NEXT: v_and_b32_e32 v1, v1, v3
; GFX10-GISEL-NEXT: v_xor_b32_e32 v0, v0, v4
; GFX10-GISEL-NEXT: v_xor_b32_e32 v1, v1, v5
; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] ; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
%xor.0 = xor <2 x i32> %a, %mask %xor.0 = xor <2 x i32> %a, %mask
%and = and <2 x i32> %xor.0, %b %and = and <2 x i32> %xor.0, %b
%bitselect = xor <2 x i32> %and, %mask %bitselect = xor <2 x i32> %and, %mask
ret <2 x i32> %bitselect ret <2 x i32> %bitselect
} }
define i64 @v_bitselect_i64_pat_0(i64 %a, i64 %b, i64 %mask) { define i64 @v_bitselect_i64_pat_0(i64 %a, i64 %b, i64 %mask) {
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; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_bfi_b32 v0, v0, v2, v4 ; GFX10-NEXT: v_bfi_b32 v0, v0, v2, v4
; GFX10-NEXT: v_bfi_b32 v1, v1, v3, v5 ; GFX10-NEXT: v_bfi_b32 v1, v1, v3, v5
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX8-GISEL-LABEL: v_bitselect_i64_pat_0: ; GFX8-GISEL-LABEL: v_bitselect_i64_pat_0:
; GFX8-GISEL: ; %bb.0: ; GFX8-GISEL: ; %bb.0:
; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-GISEL-NEXT: v_and_b32_e32 v2, v0, v2 ; GFX8-GISEL-NEXT: v_bfi_b32 v0, v0, v2, v4
; GFX8-GISEL-NEXT: v_and_b32_e32 v3, v1, v3 ; GFX8-GISEL-NEXT: v_bfi_b32 v1, v1, v3, v5
; GFX8-GISEL-NEXT: v_xor_b32_e32 v0, -1, v0
; GFX8-GISEL-NEXT: v_xor_b32_e32 v1, -1, v1
; GFX8-GISEL-NEXT: v_and_b32_e32 v0, v0, v4
; GFX8-GISEL-NEXT: v_and_b32_e32 v1, v1, v5
; GFX8-GISEL-NEXT: v_or_b32_e32 v0, v2, v0
; GFX8-GISEL-NEXT: v_or_b32_e32 v1, v3, v1
; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31] ; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-GISEL-LABEL: v_bitselect_i64_pat_0: ; GFX10-GISEL-LABEL: v_bitselect_i64_pat_0:
; GFX10-GISEL: ; %bb.0: ; GFX10-GISEL: ; %bb.0:
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-GISEL-NEXT: v_xor_b32_e32 v6, -1, v0 ; GFX10-GISEL-NEXT: v_bfi_b32 v0, v0, v2, v4
; GFX10-GISEL-NEXT: v_xor_b32_e32 v7, -1, v1 ; GFX10-GISEL-NEXT: v_bfi_b32 v1, v1, v3, v5
; GFX10-GISEL-NEXT: v_and_b32_e32 v0, v0, v2
; GFX10-GISEL-NEXT: v_and_b32_e32 v1, v1, v3
; GFX10-GISEL-NEXT: v_and_b32_e32 v2, v6, v4
; GFX10-GISEL-NEXT: v_and_b32_e32 v3, v7, v5
; GFX10-GISEL-NEXT: v_or_b32_e32 v0, v0, v2
; GFX10-GISEL-NEXT: v_or_b32_e32 v1, v1, v3
; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] ; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
%and0 = and i64 %a, %b %and0 = and i64 %a, %b
%not.a = xor i64 %a, -1 %not.a = xor i64 %a, -1
%and1 = and i64 %not.a, %mask %and1 = and i64 %not.a, %mask
%bitselect = or i64 %and0, %and1 %bitselect = or i64 %and0, %and1
ret i64 %bitselect ret i64 %bitselect
} }
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; GFX10-LABEL: v_s_s_bitselect_i64_pat_0: ; GFX10-LABEL: v_s_s_bitselect_i64_pat_0:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: v_bfi_b32 v0, v0, s0, s2 ; GFX10-NEXT: v_bfi_b32 v0, v0, s0, s2
; GFX10-NEXT: v_bfi_b32 v1, v1, s1, s3 ; GFX10-NEXT: v_bfi_b32 v1, v1, s1, s3
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
; ;
; GFX8-GISEL-LABEL: v_s_s_bitselect_i64_pat_0: ; GFX8-GISEL-LABEL: v_s_s_bitselect_i64_pat_0:
; GFX8-GISEL: ; %bb.0: ; GFX8-GISEL: ; %bb.0:
; GFX8-GISEL-NEXT: v_and_b32_e32 v2, s0, v0 ; GFX8-GISEL-NEXT: v_mov_b32_e32 v2, s0
; GFX8-GISEL-NEXT: v_and_b32_e32 v3, s1, v1 ; GFX8-GISEL-NEXT: v_bfi_b32 v0, v0, v2, s2
; GFX8-GISEL-NEXT: v_xor_b32_e32 v0, -1, v0 ; GFX8-GISEL-NEXT: v_mov_b32_e32 v2, s1
; GFX8-GISEL-NEXT: v_xor_b32_e32 v1, -1, v1 ; GFX8-GISEL-NEXT: v_bfi_b32 v1, v1, v2, s3
; GFX8-GISEL-NEXT: v_and_b32_e32 v0, s2, v0
; GFX8-GISEL-NEXT: v_and_b32_e32 v1, s3, v1
; GFX8-GISEL-NEXT: v_or_b32_e32 v0, v2, v0
; GFX8-GISEL-NEXT: v_or_b32_e32 v1, v3, v1
; GFX8-GISEL-NEXT: ; return to shader part epilog ; GFX8-GISEL-NEXT: ; return to shader part epilog
; ;
; GFX10-GISEL-LABEL: v_s_s_bitselect_i64_pat_0: ; GFX10-GISEL-LABEL: v_s_s_bitselect_i64_pat_0:
; GFX10-GISEL: ; %bb.0: ; GFX10-GISEL: ; %bb.0:
; GFX10-GISEL-NEXT: v_xor_b32_e32 v2, -1, v0 ; GFX10-GISEL-NEXT: v_bfi_b32 v0, v0, s0, s2
; GFX10-GISEL-NEXT: v_xor_b32_e32 v3, -1, v1 ; GFX10-GISEL-NEXT: v_bfi_b32 v1, v1, s1, s3
; GFX10-GISEL-NEXT: v_and_b32_e32 v0, s0, v0
; GFX10-GISEL-NEXT: v_and_b32_e32 v1, s1, v1
; GFX10-GISEL-NEXT: v_and_b32_e32 v2, s2, v2
; GFX10-GISEL-NEXT: v_and_b32_e32 v3, s3, v3
; GFX10-GISEL-NEXT: v_or_b32_e32 v0, v0, v2
; GFX10-GISEL-NEXT: v_or_b32_e32 v1, v1, v3
; GFX10-GISEL-NEXT: ; return to shader part epilog ; GFX10-GISEL-NEXT: ; return to shader part epilog
%and0 = and i64 %a, %b %and0 = and i64 %a, %b
%not.a = xor i64 %a, -1 %not.a = xor i64 %a, -1
%and1 = and i64 %not.a, %mask %and1 = and i64 %not.a, %mask
%bitselect = or i64 %and0, %and1 %bitselect = or i64 %and0, %and1
%cast = bitcast i64 %bitselect to <2 x float> %cast = bitcast i64 %bitselect to <2 x float>
ret <2 x float> %cast ret <2 x float> %cast
} }
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; GFX8-GISEL-NEXT: v_and_b32_e32 v1, s1, v1 ; GFX8-GISEL-NEXT: v_and_b32_e32 v1, s1, v1
; GFX8-GISEL-NEXT: s_andn2_b64 s[0:1], s[2:3], s[0:1] ; GFX8-GISEL-NEXT: s_andn2_b64 s[0:1], s[2:3], s[0:1]
; GFX8-GISEL-NEXT: v_or_b32_e32 v0, s0, v0 ; GFX8-GISEL-NEXT: v_or_b32_e32 v0, s0, v0
; GFX8-GISEL-NEXT: v_or_b32_e32 v1, s1, v1 ; GFX8-GISEL-NEXT: v_or_b32_e32 v1, s1, v1
; GFX8-GISEL-NEXT: ; return to shader part epilog ; GFX8-GISEL-NEXT: ; return to shader part epilog
; ;
; GFX10-GISEL-LABEL: s_v_s_bitselect_i64_pat_0: ; GFX10-GISEL-LABEL: s_v_s_bitselect_i64_pat_0:
; GFX10-GISEL: ; %bb.0: ; GFX10-GISEL: ; %bb.0:
; GFX10-GISEL-NEXT: v_and_b32_e32 v0, s0, v0 ; GFX10-GISEL-NEXT: s_andn2_b64 s[2:3], s[2:3], s[0:1]
; GFX10-GISEL-NEXT: v_and_b32_e32 v1, s1, v1 ; GFX10-GISEL-NEXT: v_and_or_b32 v0, s0, v0, s2
; GFX10-GISEL-NEXT: s_andn2_b64 s[0:1], s[2:3], s[0:1] ; GFX10-GISEL-NEXT: v_and_or_b32 v1, s1, v1, s3
; GFX10-GISEL-NEXT: v_or_b32_e32 v0, s0, v0
; GFX10-GISEL-NEXT: v_or_b32_e32 v1, s1, v1
; GFX10-GISEL-NEXT: ; return to shader part epilog ; GFX10-GISEL-NEXT: ; return to shader part epilog
%and0 = and i64 %a, %b %and0 = and i64 %a, %b
%not.a = xor i64 %a, -1 %not.a = xor i64 %a, -1
%and1 = and i64 %not.a, %mask %and1 = and i64 %not.a, %mask
%bitselect = or i64 %and0, %and1 %bitselect = or i64 %and0, %and1
%cast = bitcast i64 %bitselect to <2 x float> %cast = bitcast i64 %bitselect to <2 x float>
ret <2 x float> %cast ret <2 x float> %cast
} }
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; GFX8-GISEL-NEXT: v_and_b32_e32 v0, s0, v0 ; GFX8-GISEL-NEXT: v_and_b32_e32 v0, s0, v0
; GFX8-GISEL-NEXT: v_and_b32_e32 v1, s1, v1 ; GFX8-GISEL-NEXT: v_and_b32_e32 v1, s1, v1
; GFX8-GISEL-NEXT: v_or_b32_e32 v0, s2, v0 ; GFX8-GISEL-NEXT: v_or_b32_e32 v0, s2, v0
; GFX8-GISEL-NEXT: v_or_b32_e32 v1, s3, v1 ; GFX8-GISEL-NEXT: v_or_b32_e32 v1, s3, v1
; GFX8-GISEL-NEXT: ; return to shader part epilog ; GFX8-GISEL-NEXT: ; return to shader part epilog
; ;
; GFX10-GISEL-LABEL: s_s_v_bitselect_i64_pat_0: ; GFX10-GISEL-LABEL: s_s_v_bitselect_i64_pat_0:
; GFX10-GISEL: ; %bb.0: ; GFX10-GISEL: ; %bb.0:
; GFX10-GISEL-NEXT: s_not_b64 s[4:5], s[0:1] ; GFX10-GISEL-NEXT: s_and_b64 s[2:3], s[0:1], s[2:3]
; GFX10-GISEL-NEXT: s_and_b64 s[0:1], s[0:1], s[2:3] ; GFX10-GISEL-NEXT: s_not_b64 s[0:1], s[0:1]
; GFX10-GISEL-NEXT: v_and_b32_e32 v0, s4, v0 ; GFX10-GISEL-NEXT: v_and_or_b32 v0, s0, v0, s2
; GFX10-GISEL-NEXT: v_and_b32_e32 v1, s5, v1 ; GFX10-GISEL-NEXT: v_and_or_b32 v1, s1, v1, s3
; GFX10-GISEL-NEXT: v_or_b32_e32 v0, s0, v0
; GFX10-GISEL-NEXT: v_or_b32_e32 v1, s1, v1
; GFX10-GISEL-NEXT: ; return to shader part epilog ; GFX10-GISEL-NEXT: ; return to shader part epilog
%and0 = and i64 %a, %b %and0 = and i64 %a, %b
%not.a = xor i64 %a, -1 %not.a = xor i64 %a, -1
%and1 = and i64 %not.a, %mask %and1 = and i64 %not.a, %mask
%bitselect = or i64 %and0, %and1 %bitselect = or i64 %and0, %and1
%cast = bitcast i64 %bitselect to <2 x float> %cast = bitcast i64 %bitselect to <2 x float>
ret <2 x float> %cast ret <2 x float> %cast
} }
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; GFX10-LABEL: v_v_s_bitselect_i64_pat_0: ; GFX10-LABEL: v_v_s_bitselect_i64_pat_0:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: v_bfi_b32 v0, v0, v2, s0 ; GFX10-NEXT: v_bfi_b32 v0, v0, v2, s0
; GFX10-NEXT: v_bfi_b32 v1, v1, v3, s1 ; GFX10-NEXT: v_bfi_b32 v1, v1, v3, s1
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
; ;
; GFX8-GISEL-LABEL: v_v_s_bitselect_i64_pat_0: ; GFX8-GISEL-LABEL: v_v_s_bitselect_i64_pat_0:
; GFX8-GISEL: ; %bb.0: ; GFX8-GISEL: ; %bb.0:
; GFX8-GISEL-NEXT: v_and_b32_e32 v2, v0, v2 ; GFX8-GISEL-NEXT: v_bfi_b32 v0, v0, v2, s0
; GFX8-GISEL-NEXT: v_and_b32_e32 v3, v1, v3 ; GFX8-GISEL-NEXT: v_bfi_b32 v1, v1, v3, s1
; GFX8-GISEL-NEXT: v_xor_b32_e32 v0, -1, v0
; GFX8-GISEL-NEXT: v_xor_b32_e32 v1, -1, v1
; GFX8-GISEL-NEXT: v_and_b32_e32 v0, s0, v0
; GFX8-GISEL-NEXT: v_and_b32_e32 v1, s1, v1
; GFX8-GISEL-NEXT: v_or_b32_e32 v0, v2, v0
; GFX8-GISEL-NEXT: v_or_b32_e32 v1, v3, v1
; GFX8-GISEL-NEXT: ; return to shader part epilog ; GFX8-GISEL-NEXT: ; return to shader part epilog
; ;
; GFX10-GISEL-LABEL: v_v_s_bitselect_i64_pat_0: ; GFX10-GISEL-LABEL: v_v_s_bitselect_i64_pat_0:
; GFX10-GISEL: ; %bb.0: ; GFX10-GISEL: ; %bb.0:
; GFX10-GISEL-NEXT: v_xor_b32_e32 v4, -1, v0 ; GFX10-GISEL-NEXT: v_bfi_b32 v0, v0, v2, s0
; GFX10-GISEL-NEXT: v_xor_b32_e32 v5, -1, v1 ; GFX10-GISEL-NEXT: v_bfi_b32 v1, v1, v3, s1
; GFX10-GISEL-NEXT: v_and_b32_e32 v0, v0, v2
; GFX10-GISEL-NEXT: v_and_b32_e32 v1, v1, v3
; GFX10-GISEL-NEXT: v_and_b32_e32 v2, s0, v4
; GFX10-GISEL-NEXT: v_and_b32_e32 v3, s1, v5
; GFX10-GISEL-NEXT: v_or_b32_e32 v0, v0, v2
; GFX10-GISEL-NEXT: v_or_b32_e32 v1, v1, v3
; GFX10-GISEL-NEXT: ; return to shader part epilog ; GFX10-GISEL-NEXT: ; return to shader part epilog
%and0 = and i64 %a, %b %and0 = and i64 %a, %b
%not.a = xor i64 %a, -1 %not.a = xor i64 %a, -1
%and1 = and i64 %not.a, %mask %and1 = and i64 %not.a, %mask
%bitselect = or i64 %and0, %and1 %bitselect = or i64 %and0, %and1
%cast = bitcast i64 %bitselect to <2 x float> %cast = bitcast i64 %bitselect to <2 x float>
ret <2 x float> %cast ret <2 x float> %cast
} }
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; GFX10-LABEL: v_s_v_bitselect_i64_pat_0: ; GFX10-LABEL: v_s_v_bitselect_i64_pat_0:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: v_bfi_b32 v0, v0, s0, v2 ; GFX10-NEXT: v_bfi_b32 v0, v0, s0, v2
; GFX10-NEXT: v_bfi_b32 v1, v1, s1, v3 ; GFX10-NEXT: v_bfi_b32 v1, v1, s1, v3
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
; ;
; GFX8-GISEL-LABEL: v_s_v_bitselect_i64_pat_0: ; GFX8-GISEL-LABEL: v_s_v_bitselect_i64_pat_0:
; GFX8-GISEL: ; %bb.0: ; GFX8-GISEL: ; %bb.0:
; GFX8-GISEL-NEXT: v_and_b32_e32 v4, s0, v0 ; GFX8-GISEL-NEXT: v_bfi_b32 v0, v0, s0, v2
; GFX8-GISEL-NEXT: v_and_b32_e32 v5, s1, v1 ; GFX8-GISEL-NEXT: v_bfi_b32 v1, v1, s1, v3
; GFX8-GISEL-NEXT: v_xor_b32_e32 v0, -1, v0
; GFX8-GISEL-NEXT: v_xor_b32_e32 v1, -1, v1
; GFX8-GISEL-NEXT: v_and_b32_e32 v0, v0, v2
; GFX8-GISEL-NEXT: v_and_b32_e32 v1, v1, v3
; GFX8-GISEL-NEXT: v_or_b32_e32 v0, v4, v0
; GFX8-GISEL-NEXT: v_or_b32_e32 v1, v5, v1
; GFX8-GISEL-NEXT: ; return to shader part epilog ; GFX8-GISEL-NEXT: ; return to shader part epilog
; ;
; GFX10-GISEL-LABEL: v_s_v_bitselect_i64_pat_0: ; GFX10-GISEL-LABEL: v_s_v_bitselect_i64_pat_0:
; GFX10-GISEL: ; %bb.0: ; GFX10-GISEL: ; %bb.0:
; GFX10-GISEL-NEXT: v_xor_b32_e32 v4, -1, v0 ; GFX10-GISEL-NEXT: v_bfi_b32 v0, v0, s0, v2
; GFX10-GISEL-NEXT: v_xor_b32_e32 v5, -1, v1 ; GFX10-GISEL-NEXT: v_bfi_b32 v1, v1, s1, v3
; GFX10-GISEL-NEXT: v_and_b32_e32 v0, s0, v0
; GFX10-GISEL-NEXT: v_and_b32_e32 v1, s1, v1
; GFX10-GISEL-NEXT: v_and_b32_e32 v2, v4, v2
; GFX10-GISEL-NEXT: v_and_b32_e32 v3, v5, v3
; GFX10-GISEL-NEXT: v_or_b32_e32 v0, v0, v2
; GFX10-GISEL-NEXT: v_or_b32_e32 v1, v1, v3
; GFX10-GISEL-NEXT: ; return to shader part epilog ; GFX10-GISEL-NEXT: ; return to shader part epilog
%and0 = and i64 %a, %b %and0 = and i64 %a, %b
%not.a = xor i64 %a, -1 %not.a = xor i64 %a, -1
%and1 = and i64 %not.a, %mask %and1 = and i64 %not.a, %mask
%bitselect = or i64 %and0, %and1 %bitselect = or i64 %and0, %and1
%cast = bitcast i64 %bitselect to <2 x float> %cast = bitcast i64 %bitselect to <2 x float>
ret <2 x float> %cast ret <2 x float> %cast
} }
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; GFX8-GISEL-NEXT: v_and_b32_e32 v3, s1, v3 ; GFX8-GISEL-NEXT: v_and_b32_e32 v3, s1, v3
; GFX8-GISEL-NEXT: v_or_b32_e32 v0, v0, v2 ; GFX8-GISEL-NEXT: v_or_b32_e32 v0, v0, v2
; GFX8-GISEL-NEXT: v_or_b32_e32 v1, v1, v3 ; GFX8-GISEL-NEXT: v_or_b32_e32 v1, v1, v3
; GFX8-GISEL-NEXT: ; return to shader part epilog ; GFX8-GISEL-NEXT: ; return to shader part epilog
; ;
; GFX10-GISEL-LABEL: s_v_v_bitselect_i64_pat_0: ; GFX10-GISEL-LABEL: s_v_v_bitselect_i64_pat_0:
; GFX10-GISEL: ; %bb.0: ; GFX10-GISEL: ; %bb.0:
; GFX10-GISEL-NEXT: s_not_b64 s[2:3], s[0:1] ; GFX10-GISEL-NEXT: s_not_b64 s[2:3], s[0:1]
; GFX10-GISEL-NEXT: v_and_b32_e32 v0, s0, v0
; GFX10-GISEL-NEXT: v_and_b32_e32 v1, s1, v1
; GFX10-GISEL-NEXT: v_and_b32_e32 v2, s2, v2 ; GFX10-GISEL-NEXT: v_and_b32_e32 v2, s2, v2
; GFX10-GISEL-NEXT: v_and_b32_e32 v3, s3, v3 ; GFX10-GISEL-NEXT: v_and_b32_e32 v3, s3, v3
; GFX10-GISEL-NEXT: v_or_b32_e32 v0, v0, v2 ; GFX10-GISEL-NEXT: v_and_or_b32 v0, s0, v0, v2
; GFX10-GISEL-NEXT: v_or_b32_e32 v1, v1, v3 ; GFX10-GISEL-NEXT: v_and_or_b32 v1, s1, v1, v3
; GFX10-GISEL-NEXT: ; return to shader part epilog ; GFX10-GISEL-NEXT: ; return to shader part epilog
%and0 = and i64 %a, %b %and0 = and i64 %a, %b
%not.a = xor i64 %a, -1 %not.a = xor i64 %a, -1
%and1 = and i64 %not.a, %mask %and1 = and i64 %not.a, %mask
%bitselect = or i64 %and0, %and1 %bitselect = or i64 %and0, %and1
%cast = bitcast i64 %bitselect to <2 x float> %cast = bitcast i64 %bitselect to <2 x float>
ret <2 x float> %cast ret <2 x float> %cast
} }
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; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_bfi_b32 v0, v2, v0, v4 ; GFX10-NEXT: v_bfi_b32 v0, v2, v0, v4
; GFX10-NEXT: v_bfi_b32 v1, v3, v1, v5 ; GFX10-NEXT: v_bfi_b32 v1, v3, v1, v5
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX8-GISEL-LABEL: v_bitselect_i64_pat_1: ; GFX8-GISEL-LABEL: v_bitselect_i64_pat_1:
; GFX8-GISEL: ; %bb.0: ; GFX8-GISEL: ; %bb.0:
; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-GISEL-NEXT: v_xor_b32_e32 v0, v0, v4 ; GFX8-GISEL-NEXT: v_bfi_b32 v0, v2, v0, v4
; GFX8-GISEL-NEXT: v_xor_b32_e32 v1, v1, v5 ; GFX8-GISEL-NEXT: v_bfi_b32 v1, v3, v1, v5
; GFX8-GISEL-NEXT: v_and_b32_e32 v0, v0, v2
; GFX8-GISEL-NEXT: v_and_b32_e32 v1, v1, v3
; GFX8-GISEL-NEXT: v_xor_b32_e32 v0, v0, v4
; GFX8-GISEL-NEXT: v_xor_b32_e32 v1, v1, v5
; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31] ; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-GISEL-LABEL: v_bitselect_i64_pat_1: ; GFX10-GISEL-LABEL: v_bitselect_i64_pat_1:
; GFX10-GISEL: ; %bb.0: ; GFX10-GISEL: ; %bb.0:
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-GISEL-NEXT: v_xor_b32_e32 v0, v0, v4 ; GFX10-GISEL-NEXT: v_bfi_b32 v0, v2, v0, v4
; GFX10-GISEL-NEXT: v_xor_b32_e32 v1, v1, v5 ; GFX10-GISEL-NEXT: v_bfi_b32 v1, v3, v1, v5
; GFX10-GISEL-NEXT: v_and_b32_e32 v0, v0, v2
; GFX10-GISEL-NEXT: v_and_b32_e32 v1, v1, v3
; GFX10-GISEL-NEXT: v_xor_b32_e32 v0, v0, v4
; GFX10-GISEL-NEXT: v_xor_b32_e32 v1, v1, v5
; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] ; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
%xor.0 = xor i64 %a, %mask %xor.0 = xor i64 %a, %mask
%and = and i64 %xor.0, %b %and = and i64 %xor.0, %b
%bitselect = xor i64 %and, %mask %bitselect = xor i64 %and, %mask
ret i64 %bitselect ret i64 %bitselect
} }
define amdgpu_ps <2 x float> @v_s_s_bitselect_i64_pat_1(i64 %a, i64 inreg %b, i64 inreg %mask) { define amdgpu_ps <2 x float> @v_s_s_bitselect_i64_pat_1(i64 %a, i64 inreg %b, i64 inreg %mask) {
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; GFX10-LABEL: v_s_s_bitselect_i64_pat_1: ; GFX10-LABEL: v_s_s_bitselect_i64_pat_1:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: v_bfi_b32 v0, s0, v0, s2 ; GFX10-NEXT: v_bfi_b32 v0, s0, v0, s2
; GFX10-NEXT: v_bfi_b32 v1, s1, v1, s3 ; GFX10-NEXT: v_bfi_b32 v1, s1, v1, s3
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
; ;
; GFX8-GISEL-LABEL: v_s_s_bitselect_i64_pat_1: ; GFX8-GISEL-LABEL: v_s_s_bitselect_i64_pat_1:
; GFX8-GISEL: ; %bb.0: ; GFX8-GISEL: ; %bb.0:
; GFX8-GISEL-NEXT: v_xor_b32_e32 v0, s2, v0 ; GFX8-GISEL-NEXT: v_mov_b32_e32 v2, s0
; GFX8-GISEL-NEXT: v_xor_b32_e32 v1, s3, v1 ; GFX8-GISEL-NEXT: v_bfi_b32 v0, v2, v0, s2
; GFX8-GISEL-NEXT: v_and_b32_e32 v0, s0, v0 ; GFX8-GISEL-NEXT: v_mov_b32_e32 v2, s1
; GFX8-GISEL-NEXT: v_and_b32_e32 v1, s1, v1 ; GFX8-GISEL-NEXT: v_bfi_b32 v1, v2, v1, s3
; GFX8-GISEL-NEXT: v_xor_b32_e32 v0, s2, v0
; GFX8-GISEL-NEXT: v_xor_b32_e32 v1, s3, v1
; GFX8-GISEL-NEXT: ; return to shader part epilog ; GFX8-GISEL-NEXT: ; return to shader part epilog
; ;
; GFX10-GISEL-LABEL: v_s_s_bitselect_i64_pat_1: ; GFX10-GISEL-LABEL: v_s_s_bitselect_i64_pat_1:
; GFX10-GISEL: ; %bb.0: ; GFX10-GISEL: ; %bb.0:
; GFX10-GISEL-NEXT: v_xor_b32_e32 v0, s2, v0 ; GFX10-GISEL-NEXT: v_bfi_b32 v0, s0, v0, s2
; GFX10-GISEL-NEXT: v_xor_b32_e32 v1, s3, v1 ; GFX10-GISEL-NEXT: v_bfi_b32 v1, s1, v1, s3
; GFX10-GISEL-NEXT: v_and_b32_e32 v0, s0, v0
; GFX10-GISEL-NEXT: v_and_b32_e32 v1, s1, v1
; GFX10-GISEL-NEXT: v_xor_b32_e32 v0, s2, v0
; GFX10-GISEL-NEXT: v_xor_b32_e32 v1, s3, v1
; GFX10-GISEL-NEXT: ; return to shader part epilog ; GFX10-GISEL-NEXT: ; return to shader part epilog
%xor.0 = xor i64 %a, %mask %xor.0 = xor i64 %a, %mask
%and = and i64 %xor.0, %b %and = and i64 %xor.0, %b
%bitselect = xor i64 %and, %mask %bitselect = xor i64 %and, %mask
%cast = bitcast i64 %bitselect to <2 x float> %cast = bitcast i64 %bitselect to <2 x float>
ret <2 x float> %cast ret <2 x float> %cast
} }
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; GFX10-LABEL: s_s_v_bitselect_i64_pat_1: ; GFX10-LABEL: s_s_v_bitselect_i64_pat_1:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: v_bfi_b32 v0, s2, s0, v0 ; GFX10-NEXT: v_bfi_b32 v0, s2, s0, v0
; GFX10-NEXT: v_bfi_b32 v1, s3, s1, v1 ; GFX10-NEXT: v_bfi_b32 v1, s3, s1, v1
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
; ;
; GFX8-GISEL-LABEL: s_s_v_bitselect_i64_pat_1: ; GFX8-GISEL-LABEL: s_s_v_bitselect_i64_pat_1:
; GFX8-GISEL: ; %bb.0: ; GFX8-GISEL: ; %bb.0:
; GFX8-GISEL-NEXT: v_xor_b32_e32 v2, s0, v0 ; GFX8-GISEL-NEXT: v_mov_b32_e32 v2, s2
; GFX8-GISEL-NEXT: v_xor_b32_e32 v3, s1, v1 ; GFX8-GISEL-NEXT: v_bfi_b32 v0, v2, s0, v0
; GFX8-GISEL-NEXT: v_and_b32_e32 v2, s2, v2 ; GFX8-GISEL-NEXT: v_mov_b32_e32 v2, s3
; GFX8-GISEL-NEXT: v_and_b32_e32 v3, s3, v3 ; GFX8-GISEL-NEXT: v_bfi_b32 v1, v2, s1, v1
; GFX8-GISEL-NEXT: v_xor_b32_e32 v0, v2, v0
; GFX8-GISEL-NEXT: v_xor_b32_e32 v1, v3, v1
; GFX8-GISEL-NEXT: ; return to shader part epilog ; GFX8-GISEL-NEXT: ; return to shader part epilog
; ;
; GFX10-GISEL-LABEL: s_s_v_bitselect_i64_pat_1: ; GFX10-GISEL-LABEL: s_s_v_bitselect_i64_pat_1:
; GFX10-GISEL: ; %bb.0: ; GFX10-GISEL: ; %bb.0:
; GFX10-GISEL-NEXT: v_xor_b32_e32 v2, s0, v0 ; GFX10-GISEL-NEXT: v_bfi_b32 v0, s2, s0, v0
; GFX10-GISEL-NEXT: v_xor_b32_e32 v3, s1, v1 ; GFX10-GISEL-NEXT: v_bfi_b32 v1, s3, s1, v1
; GFX10-GISEL-NEXT: v_and_b32_e32 v2, s2, v2
; GFX10-GISEL-NEXT: v_and_b32_e32 v3, s3, v3
; GFX10-GISEL-NEXT: v_xor_b32_e32 v0, v2, v0
; GFX10-GISEL-NEXT: v_xor_b32_e32 v1, v3, v1
; GFX10-GISEL-NEXT: ; return to shader part epilog ; GFX10-GISEL-NEXT: ; return to shader part epilog
%xor.0 = xor i64 %a, %mask %xor.0 = xor i64 %a, %mask
%and = and i64 %xor.0, %b %and = and i64 %xor.0, %b
%bitselect = xor i64 %and, %mask %bitselect = xor i64 %and, %mask
%cast = bitcast i64 %bitselect to <2 x float> %cast = bitcast i64 %bitselect to <2 x float>
ret <2 x float> %cast ret <2 x float> %cast
} }
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; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_bfi_b32 v0, v2, v0, v4 ; GFX10-NEXT: v_bfi_b32 v0, v2, v0, v4
; GFX10-NEXT: v_bfi_b32 v1, v3, v1, v5 ; GFX10-NEXT: v_bfi_b32 v1, v3, v1, v5
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX8-GISEL-LABEL: v_bitselect_i64_pat_2: ; GFX8-GISEL-LABEL: v_bitselect_i64_pat_2:
; GFX8-GISEL: ; %bb.0: ; GFX8-GISEL: ; %bb.0:
; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-GISEL-NEXT: v_xor_b32_e32 v0, v0, v4 ; GFX8-GISEL-NEXT: v_bfi_b32 v0, v2, v0, v4
; GFX8-GISEL-NEXT: v_xor_b32_e32 v1, v1, v5 ; GFX8-GISEL-NEXT: v_bfi_b32 v1, v3, v1, v5
; GFX8-GISEL-NEXT: v_and_b32_e32 v0, v0, v2
; GFX8-GISEL-NEXT: v_and_b32_e32 v1, v1, v3
; GFX8-GISEL-NEXT: v_xor_b32_e32 v0, v0, v4
; GFX8-GISEL-NEXT: v_xor_b32_e32 v1, v1, v5
; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31] ; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-GISEL-LABEL: v_bitselect_i64_pat_2: ; GFX10-GISEL-LABEL: v_bitselect_i64_pat_2:
; GFX10-GISEL: ; %bb.0: ; GFX10-GISEL: ; %bb.0:
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-GISEL-NEXT: v_xor_b32_e32 v0, v0, v4 ; GFX10-GISEL-NEXT: v_bfi_b32 v0, v2, v0, v4
; GFX10-GISEL-NEXT: v_xor_b32_e32 v1, v1, v5 ; GFX10-GISEL-NEXT: v_bfi_b32 v1, v3, v1, v5
; GFX10-GISEL-NEXT: v_and_b32_e32 v0, v0, v2
; GFX10-GISEL-NEXT: v_and_b32_e32 v1, v1, v3
; GFX10-GISEL-NEXT: v_xor_b32_e32 v0, v0, v4
; GFX10-GISEL-NEXT: v_xor_b32_e32 v1, v1, v5
; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] ; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
%xor.0 = xor i64 %a, %mask %xor.0 = xor i64 %a, %mask
%and = and i64 %xor.0, %b %and = and i64 %xor.0, %b
%bitselect = xor i64 %and, %mask %bitselect = xor i64 %and, %mask
ret i64 %bitselect ret i64 %bitselect
} }
define i64 @v_bfi_sha256_ma_i64(i64 %x, i64 %y, i64 %z) { define i64 @v_bfi_sha256_ma_i64(i64 %x, i64 %y, i64 %z) {
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; GFX10-NEXT: v_xor_b32_e32 v1, v1, v3 ; GFX10-NEXT: v_xor_b32_e32 v1, v1, v3
; GFX10-NEXT: v_bfi_b32 v0, v0, v4, v2 ; GFX10-NEXT: v_bfi_b32 v0, v0, v4, v2
; GFX10-NEXT: v_bfi_b32 v1, v1, v5, v3 ; GFX10-NEXT: v_bfi_b32 v1, v1, v5, v3
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX8-GISEL-LABEL: v_bfi_sha256_ma_i64: ; GFX8-GISEL-LABEL: v_bfi_sha256_ma_i64:
; GFX8-GISEL: ; %bb.0: ; %entry ; GFX8-GISEL: ; %bb.0: ; %entry
; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-GISEL-NEXT: v_and_b32_e32 v6, v0, v4 ; GFX8-GISEL-NEXT: v_xor_b32_e32 v0, v0, v2
; GFX8-GISEL-NEXT: v_and_b32_e32 v7, v1, v5 ; GFX8-GISEL-NEXT: v_xor_b32_e32 v1, v1, v3
; GFX8-GISEL-NEXT: v_or_b32_e32 v0, v0, v4 ; GFX8-GISEL-NEXT: v_bfi_b32 v0, v0, v4, v2
; GFX8-GISEL-NEXT: v_or_b32_e32 v1, v1, v5 ; GFX8-GISEL-NEXT: v_bfi_b32 v1, v1, v5, v3
; GFX8-GISEL-NEXT: v_and_b32_e32 v0, v2, v0
; GFX8-GISEL-NEXT: v_and_b32_e32 v1, v3, v1
; GFX8-GISEL-NEXT: v_or_b32_e32 v0, v6, v0
; GFX8-GISEL-NEXT: v_or_b32_e32 v1, v7, v1
; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31] ; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-GISEL-LABEL: v_bfi_sha256_ma_i64: ; GFX10-GISEL-LABEL: v_bfi_sha256_ma_i64:
; GFX10-GISEL: ; %bb.0: ; %entry ; GFX10-GISEL: ; %bb.0: ; %entry
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-GISEL-NEXT: v_or_b32_e32 v6, v0, v4 ; GFX10-GISEL-NEXT: v_xor_b32_e32 v0, v0, v2
; GFX10-GISEL-NEXT: v_or_b32_e32 v7, v1, v5 ; GFX10-GISEL-NEXT: v_xor_b32_e32 v1, v1, v3
; GFX10-GISEL-NEXT: v_and_b32_e32 v0, v0, v4 ; GFX10-GISEL-NEXT: v_bfi_b32 v0, v0, v4, v2
; GFX10-GISEL-NEXT: v_and_b32_e32 v1, v1, v5 ; GFX10-GISEL-NEXT: v_bfi_b32 v1, v1, v5, v3
; GFX10-GISEL-NEXT: v_and_b32_e32 v2, v2, v6
; GFX10-GISEL-NEXT: v_and_b32_e32 v3, v3, v7
; GFX10-GISEL-NEXT: v_or_b32_e32 v0, v0, v2
; GFX10-GISEL-NEXT: v_or_b32_e32 v1, v1, v3
; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] ; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
entry: entry:
%and0 = and i64 %x, %z %and0 = and i64 %x, %z
%or0 = or i64 %x, %z %or0 = or i64 %x, %z
%and1 = and i64 %y, %or0 %and1 = and i64 %y, %or0
%or1 = or i64 %and0, %and1 %or1 = or i64 %and0, %and1
ret i64 %or1 ret i64 %or1
} }
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; GFX10-NEXT: v_xor_b32_e32 v0, s0, v0 ; GFX10-NEXT: v_xor_b32_e32 v0, s0, v0
; GFX10-NEXT: v_xor_b32_e32 v1, s1, v1 ; GFX10-NEXT: v_xor_b32_e32 v1, s1, v1
; GFX10-NEXT: v_bfi_b32 v0, v0, s2, s0 ; GFX10-NEXT: v_bfi_b32 v0, v0, s2, s0
; GFX10-NEXT: v_bfi_b32 v1, v1, s3, s1 ; GFX10-NEXT: v_bfi_b32 v1, v1, s3, s1
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
; ;
; GFX8-GISEL-LABEL: v_s_s_bfi_sha256_ma_i64: ; GFX8-GISEL-LABEL: v_s_s_bfi_sha256_ma_i64:
; GFX8-GISEL: ; %bb.0: ; %entry ; GFX8-GISEL: ; %bb.0: ; %entry
; GFX8-GISEL-NEXT: v_and_b32_e32 v2, s2, v0 ; GFX8-GISEL-NEXT: v_mov_b32_e32 v2, s2
; GFX8-GISEL-NEXT: v_and_b32_e32 v3, s3, v1 ; GFX8-GISEL-NEXT: v_xor_b32_e32 v0, s0, v0
; GFX8-GISEL-NEXT: v_or_b32_e32 v0, s2, v0 ; GFX8-GISEL-NEXT: v_bfi_b32 v0, v0, v2, s0
; GFX8-GISEL-NEXT: v_or_b32_e32 v1, s3, v1 ; GFX8-GISEL-NEXT: v_mov_b32_e32 v2, s3
; GFX8-GISEL-NEXT: v_and_b32_e32 v0, s0, v0 ; GFX8-GISEL-NEXT: v_xor_b32_e32 v1, s1, v1
; GFX8-GISEL-NEXT: v_and_b32_e32 v1, s1, v1 ; GFX8-GISEL-NEXT: v_bfi_b32 v1, v1, v2, s1
; GFX8-GISEL-NEXT: v_or_b32_e32 v0, v2, v0
; GFX8-GISEL-NEXT: v_or_b32_e32 v1, v3, v1
; GFX8-GISEL-NEXT: ; return to shader part epilog ; GFX8-GISEL-NEXT: ; return to shader part epilog
; ;
; GFX10-GISEL-LABEL: v_s_s_bfi_sha256_ma_i64: ; GFX10-GISEL-LABEL: v_s_s_bfi_sha256_ma_i64:
; GFX10-GISEL: ; %bb.0: ; %entry ; GFX10-GISEL: ; %bb.0: ; %entry
; GFX10-GISEL-NEXT: v_or_b32_e32 v2, s2, v0 ; GFX10-GISEL-NEXT: v_xor_b32_e32 v0, s0, v0
; GFX10-GISEL-NEXT: v_or_b32_e32 v3, s3, v1 ; GFX10-GISEL-NEXT: v_xor_b32_e32 v1, s1, v1
; GFX10-GISEL-NEXT: v_and_b32_e32 v0, s2, v0 ; GFX10-GISEL-NEXT: v_bfi_b32 v0, v0, s2, s0
; GFX10-GISEL-NEXT: v_and_b32_e32 v1, s3, v1 ; GFX10-GISEL-NEXT: v_bfi_b32 v1, v1, s3, s1
; GFX10-GISEL-NEXT: v_and_b32_e32 v2, s0, v2
; GFX10-GISEL-NEXT: v_and_b32_e32 v3, s1, v3
; GFX10-GISEL-NEXT: v_or_b32_e32 v0, v0, v2
; GFX10-GISEL-NEXT: v_or_b32_e32 v1, v1, v3
; GFX10-GISEL-NEXT: ; return to shader part epilog ; GFX10-GISEL-NEXT: ; return to shader part epilog
entry: entry:
%and0 = and i64 %x, %z %and0 = and i64 %x, %z
%or0 = or i64 %x, %z %or0 = or i64 %x, %z
%and1 = and i64 %y, %or0 %and1 = and i64 %y, %or0
%or1 = or i64 %and0, %and1 %or1 = or i64 %and0, %and1
%cast = bitcast i64 %or1 to <2 x float> %cast = bitcast i64 %or1 to <2 x float>
ret <2 x float> %cast ret <2 x float> %cast
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; GFX8-GISEL-NEXT: v_and_b32_e32 v0, s0, v0 ; GFX8-GISEL-NEXT: v_and_b32_e32 v0, s0, v0
; GFX8-GISEL-NEXT: v_and_b32_e32 v1, s1, v1 ; GFX8-GISEL-NEXT: v_and_b32_e32 v1, s1, v1
; GFX8-GISEL-NEXT: v_or_b32_e32 v0, s4, v0 ; GFX8-GISEL-NEXT: v_or_b32_e32 v0, s4, v0
; GFX8-GISEL-NEXT: v_or_b32_e32 v1, s5, v1 ; GFX8-GISEL-NEXT: v_or_b32_e32 v1, s5, v1
; GFX8-GISEL-NEXT: ; return to shader part epilog ; GFX8-GISEL-NEXT: ; return to shader part epilog
; ;
; GFX10-GISEL-LABEL: s_v_s_bfi_sha256_ma_i64: ; GFX10-GISEL-LABEL: s_v_s_bfi_sha256_ma_i64:
; GFX10-GISEL: ; %bb.0: ; %entry ; GFX10-GISEL: ; %bb.0: ; %entry
; GFX10-GISEL-NEXT: s_or_b64 s[4:5], s[0:1], s[2:3] ; GFX10-GISEL-NEXT: s_and_b64 s[4:5], s[0:1], s[2:3]
; GFX10-GISEL-NEXT: s_and_b64 s[0:1], s[0:1], s[2:3] ; GFX10-GISEL-NEXT: s_or_b64 s[0:1], s[0:1], s[2:3]
; GFX10-GISEL-NEXT: v_and_b32_e32 v0, s4, v0 ; GFX10-GISEL-NEXT: v_and_or_b32 v0, v0, s0, s4
; GFX10-GISEL-NEXT: v_and_b32_e32 v1, s5, v1 ; GFX10-GISEL-NEXT: v_and_or_b32 v1, v1, s1, s5
; GFX10-GISEL-NEXT: v_or_b32_e32 v0, s0, v0
; GFX10-GISEL-NEXT: v_or_b32_e32 v1, s1, v1
; GFX10-GISEL-NEXT: ; return to shader part epilog ; GFX10-GISEL-NEXT: ; return to shader part epilog
entry: entry:
%and0 = and i64 %x, %z %and0 = and i64 %x, %z
%or0 = or i64 %x, %z %or0 = or i64 %x, %z
%and1 = and i64 %y, %or0 %and1 = and i64 %y, %or0
%or1 = or i64 %and0, %and1 %or1 = or i64 %and0, %and1
%cast = bitcast i64 %or1 to <2 x float> %cast = bitcast i64 %or1 to <2 x float>
ret <2 x float> %cast ret <2 x float> %cast
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; GFX10-NEXT: v_xor_b32_e64 v2, s0, s2 ; GFX10-NEXT: v_xor_b32_e64 v2, s0, s2
; GFX10-NEXT: v_xor_b32_e64 v3, s1, s3 ; GFX10-NEXT: v_xor_b32_e64 v3, s1, s3
; GFX10-NEXT: v_bfi_b32 v0, v2, v0, s2 ; GFX10-NEXT: v_bfi_b32 v0, v2, v0, s2
; GFX10-NEXT: v_bfi_b32 v1, v3, v1, s3 ; GFX10-NEXT: v_bfi_b32 v1, v3, v1, s3
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
; ;
; GFX8-GISEL-LABEL: s_s_v_bfi_sha256_ma_i64: ; GFX8-GISEL-LABEL: s_s_v_bfi_sha256_ma_i64:
; GFX8-GISEL: ; %bb.0: ; %entry ; GFX8-GISEL: ; %bb.0: ; %entry
; GFX8-GISEL-NEXT: v_and_b32_e32 v2, s0, v0 ; GFX8-GISEL-NEXT: v_mov_b32_e32 v2, s0
; GFX8-GISEL-NEXT: v_and_b32_e32 v3, s1, v1 ; GFX8-GISEL-NEXT: v_xor_b32_e32 v2, s2, v2
; GFX8-GISEL-NEXT: v_or_b32_e32 v0, s0, v0 ; GFX8-GISEL-NEXT: v_bfi_b32 v0, v2, v0, s2
; GFX8-GISEL-NEXT: v_or_b32_e32 v1, s1, v1 ; GFX8-GISEL-NEXT: v_mov_b32_e32 v2, s1
; GFX8-GISEL-NEXT: v_and_b32_e32 v0, s2, v0 ; GFX8-GISEL-NEXT: v_xor_b32_e32 v2, s3, v2
; GFX8-GISEL-NEXT: v_and_b32_e32 v1, s3, v1 ; GFX8-GISEL-NEXT: v_bfi_b32 v1, v2, v1, s3
; GFX8-GISEL-NEXT: v_or_b32_e32 v0, v2, v0
; GFX8-GISEL-NEXT: v_or_b32_e32 v1, v3, v1
; GFX8-GISEL-NEXT: ; return to shader part epilog ; GFX8-GISEL-NEXT: ; return to shader part epilog
; ;
; GFX10-GISEL-LABEL: s_s_v_bfi_sha256_ma_i64: ; GFX10-GISEL-LABEL: s_s_v_bfi_sha256_ma_i64:
; GFX10-GISEL: ; %bb.0: ; %entry ; GFX10-GISEL: ; %bb.0: ; %entry
; GFX10-GISEL-NEXT: v_or_b32_e32 v2, s0, v0 ; GFX10-GISEL-NEXT: v_xor_b32_e64 v2, s0, s2
; GFX10-GISEL-NEXT: v_or_b32_e32 v3, s1, v1 ; GFX10-GISEL-NEXT: v_xor_b32_e64 v3, s1, s3
; GFX10-GISEL-NEXT: v_and_b32_e32 v0, s0, v0 ; GFX10-GISEL-NEXT: v_bfi_b32 v0, v2, v0, s2
; GFX10-GISEL-NEXT: v_and_b32_e32 v1, s1, v1 ; GFX10-GISEL-NEXT: v_bfi_b32 v1, v3, v1, s3
; GFX10-GISEL-NEXT: v_and_b32_e32 v2, s2, v2
; GFX10-GISEL-NEXT: v_and_b32_e32 v3, s3, v3
; GFX10-GISEL-NEXT: v_or_b32_e32 v0, v0, v2
; GFX10-GISEL-NEXT: v_or_b32_e32 v1, v1, v3
; GFX10-GISEL-NEXT: ; return to shader part epilog ; GFX10-GISEL-NEXT: ; return to shader part epilog
entry: entry:
%and0 = and i64 %x, %z %and0 = and i64 %x, %z
%or0 = or i64 %x, %z %or0 = or i64 %x, %z
%and1 = and i64 %y, %or0 %and1 = and i64 %y, %or0
%or1 = or i64 %and0, %and1 %or1 = or i64 %and0, %and1
%cast = bitcast i64 %or1 to <2 x float> %cast = bitcast i64 %or1 to <2 x float>
ret <2 x float> %cast ret <2 x float> %cast
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; GFX10-NEXT: v_xor_b32_e32 v0, s0, v0 ; GFX10-NEXT: v_xor_b32_e32 v0, s0, v0
; GFX10-NEXT: v_xor_b32_e32 v1, s1, v1 ; GFX10-NEXT: v_xor_b32_e32 v1, s1, v1
; GFX10-NEXT: v_bfi_b32 v0, v0, v2, s0 ; GFX10-NEXT: v_bfi_b32 v0, v0, v2, s0
; GFX10-NEXT: v_bfi_b32 v1, v1, v3, s1 ; GFX10-NEXT: v_bfi_b32 v1, v1, v3, s1
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
; ;
; GFX8-GISEL-LABEL: v_s_v_bfi_sha256_ma_i64: ; GFX8-GISEL-LABEL: v_s_v_bfi_sha256_ma_i64:
; GFX8-GISEL: ; %bb.0: ; %entry ; GFX8-GISEL: ; %bb.0: ; %entry
; GFX8-GISEL-NEXT: v_and_b32_e32 v4, v0, v2 ; GFX8-GISEL-NEXT: v_xor_b32_e32 v0, s0, v0
; GFX8-GISEL-NEXT: v_and_b32_e32 v5, v1, v3 ; GFX8-GISEL-NEXT: v_xor_b32_e32 v1, s1, v1
; GFX8-GISEL-NEXT: v_or_b32_e32 v0, v0, v2 ; GFX8-GISEL-NEXT: v_bfi_b32 v0, v0, v2, s0
; GFX8-GISEL-NEXT: v_or_b32_e32 v1, v1, v3 ; GFX8-GISEL-NEXT: v_bfi_b32 v1, v1, v3, s1
; GFX8-GISEL-NEXT: v_and_b32_e32 v0, s0, v0
; GFX8-GISEL-NEXT: v_and_b32_e32 v1, s1, v1
; GFX8-GISEL-NEXT: v_or_b32_e32 v0, v4, v0
; GFX8-GISEL-NEXT: v_or_b32_e32 v1, v5, v1
; GFX8-GISEL-NEXT: ; return to shader part epilog ; GFX8-GISEL-NEXT: ; return to shader part epilog
; ;
; GFX10-GISEL-LABEL: v_s_v_bfi_sha256_ma_i64: ; GFX10-GISEL-LABEL: v_s_v_bfi_sha256_ma_i64:
; GFX10-GISEL: ; %bb.0: ; %entry ; GFX10-GISEL: ; %bb.0: ; %entry
; GFX10-GISEL-NEXT: v_or_b32_e32 v4, v0, v2 ; GFX10-GISEL-NEXT: v_xor_b32_e32 v0, s0, v0
; GFX10-GISEL-NEXT: v_or_b32_e32 v5, v1, v3 ; GFX10-GISEL-NEXT: v_xor_b32_e32 v1, s1, v1
; GFX10-GISEL-NEXT: v_and_b32_e32 v0, v0, v2 ; GFX10-GISEL-NEXT: v_bfi_b32 v0, v0, v2, s0
; GFX10-GISEL-NEXT: v_and_b32_e32 v1, v1, v3 ; GFX10-GISEL-NEXT: v_bfi_b32 v1, v1, v3, s1
; GFX10-GISEL-NEXT: v_and_b32_e32 v2, s0, v4
; GFX10-GISEL-NEXT: v_and_b32_e32 v3, s1, v5
; GFX10-GISEL-NEXT: v_or_b32_e32 v0, v0, v2
; GFX10-GISEL-NEXT: v_or_b32_e32 v1, v1, v3
; GFX10-GISEL-NEXT: ; return to shader part epilog ; GFX10-GISEL-NEXT: ; return to shader part epilog
entry: entry:
%and0 = and i64 %x, %z %and0 = and i64 %x, %z
%or0 = or i64 %x, %z %or0 = or i64 %x, %z
%and1 = and i64 %y, %or0 %and1 = and i64 %y, %or0
%or1 = or i64 %and0, %and1 %or1 = or i64 %and0, %and1
%cast = bitcast i64 %or1 to <2 x float> %cast = bitcast i64 %or1 to <2 x float>
ret <2 x float> %cast ret <2 x float> %cast
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