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Differential D142192 Diff 491241 llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll

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llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll

Show First 20 Lines • Show All 1,059 Lines • ▼ Show 20 Lines
; CHECK-NEXT: v_add_i32_e32 v3, vcc, v3, v6 ; CHECK-NEXT: v_add_i32_e32 v3, vcc, v3, v6
; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v6, vcc, v7, v6 ; CHECK-NEXT: v_add_i32_e32 v6, vcc, v7, v6
; CHECK-NEXT: v_mul_lo_u32 v7, v3, s4 ; CHECK-NEXT: v_mul_lo_u32 v7, v3, s4
; CHECK-NEXT: v_mul_hi_u32 v3, s4, v3 ; CHECK-NEXT: v_mul_hi_u32 v3, s4, v3
; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v6 ; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v6
; CHECK-NEXT: v_mul_lo_u32 v5, v5, s4 ; CHECK-NEXT: v_mul_lo_u32 v5, v5, s4
; CHECK-NEXT: v_add_i32_e32 v3, vcc, v5, v3 ; CHECK-NEXT: v_add_i32_e32 v3, vcc, v5, v3
; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v7 ; CHECK-NEXT: v_sub_i32_e64 v0, s[4:5], v0, v7
; CHECK-NEXT: v_subb_u32_e64 v5, s[4:5], v1, v3, vcc ; CHECK-NEXT: v_subb_u32_e64 v5, vcc, v1, v3, s[4:5]
; CHECK-NEXT: v_sub_i32_e64 v1, s[4:5], v1, v3 ; CHECK-NEXT: v_sub_i32_e32 v1, vcc, v1, v3
; CHECK-NEXT: v_cmp_ge_u32_e64 s[4:5], v0, v2 ; CHECK-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2
; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, -1, s[4:5] ; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc
; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v5
; CHECK-NEXT: v_cndmask_b32_e64 v3, v4, v3, s[4:5]
; CHECK-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
; CHECK-NEXT: v_sub_i32_e32 v6, vcc, v0, v2 ; CHECK-NEXT: v_sub_i32_e32 v6, vcc, v0, v2
; CHECK-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc ; CHECK-NEXT: v_cmp_eq_u32_e64 s[6:7], 0, v5
; CHECK-NEXT: v_cmp_ge_u32_e32 vcc, v6, v2 ; CHECK-NEXT: v_cndmask_b32_e64 v3, v4, v3, s[6:7]
; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc ; CHECK-NEXT: v_subbrev_u32_e64 v1, s[4:5], 0, v1, s[4:5]
; CHECK-NEXT: v_sub_i32_e32 v2, vcc, v6, v2 ; CHECK-NEXT: v_cmp_ge_u32_e64 s[4:5], v6, v2
; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, -1, s[4:5]
; CHECK-NEXT: s_mov_b64 s[4:5], vcc
; CHECK-NEXT: v_subrev_i32_e32 v7, vcc, 0x12d8fb, v6
; CHECK-NEXT: v_subbrev_u32_e64 v1, s[4:5], 0, v1, s[4:5]
; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v1 ; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v1
; CHECK-NEXT: v_cndmask_b32_e64 v4, v4, v7, s[4:5] ; CHECK-NEXT: v_cndmask_b32_e64 v2, v4, v2, s[4:5]
; CHECK-NEXT: v_subbrev_u32_e32 v7, vcc, 0, v1, vcc ; CHECK-NEXT: v_subbrev_u32_e32 v4, vcc, 0, v1, vcc
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4 ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
; CHECK-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v2, v6, v7, vcc
; CHECK-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; CHECK-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
; CHECK-NEXT: s_setpc_b64 s[30:31] ; CHECK-NEXT: s_setpc_b64 s[30:31]
%result = urem i64 %num, 1235195 %result = urem i64 %num, 1235195
ret i64 %result ret i64 %result
} }
▲ Show 20 Lines • Show All 190 Lines • ▼ Show 20 Lines
; GISEL-NEXT: v_mul_lo_u32 v12, v6, s6 ; GISEL-NEXT: v_mul_lo_u32 v12, v6, s6
; GISEL-NEXT: v_mul_hi_u32 v6, s6, v6 ; GISEL-NEXT: v_mul_hi_u32 v6, s6, v6
; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v13 ; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v13
; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v11 ; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v11
; GISEL-NEXT: v_mul_lo_u32 v8, v8, s6 ; GISEL-NEXT: v_mul_lo_u32 v8, v8, s6
; GISEL-NEXT: v_mul_lo_u32 v9, v9, s6 ; GISEL-NEXT: v_mul_lo_u32 v9, v9, s6
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v8, v7 ; GISEL-NEXT: v_add_i32_e32 v7, vcc, v8, v7
; GISEL-NEXT: v_add_i32_e32 v6, vcc, v9, v6 ; GISEL-NEXT: v_add_i32_e32 v6, vcc, v9, v6
; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v14 ; GISEL-NEXT: v_sub_i32_e64 v0, s[4:5], v0, v14
; GISEL-NEXT: v_subb_u32_e64 v8, s[4:5], v1, v7, vcc ; GISEL-NEXT: v_subb_u32_e64 v8, vcc, v1, v7, s[4:5]
; GISEL-NEXT: v_sub_i32_e64 v1, s[4:5], v1, v7 ; GISEL-NEXT: v_sub_i32_e32 v1, vcc, v1, v7
; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v0, v4 ; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v0, v4
; GISEL-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc
; GISEL-NEXT: v_sub_i32_e64 v2, s[4:5], v2, v12 ; GISEL-NEXT: v_sub_i32_e64 v2, s[6:7], v2, v12
; GISEL-NEXT: v_subb_u32_e64 v9, s[6:7], v3, v6, s[4:5] ; GISEL-NEXT: v_subb_u32_e64 v9, vcc, v3, v6, s[6:7]
; GISEL-NEXT: v_sub_i32_e64 v3, s[6:7], v3, v6 ; GISEL-NEXT: v_sub_i32_e32 v3, vcc, v3, v6
; GISEL-NEXT: v_cmp_ge_u32_e64 s[6:7], v2, v4 ; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v2, v4
; GISEL-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[6:7] ; GISEL-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc
; GISEL-NEXT: v_cmp_eq_u32_e64 s[6:7], 0, v8 ; GISEL-NEXT: v_sub_i32_e32 v11, vcc, v2, v4
; GISEL-NEXT: v_cndmask_b32_e64 v7, v5, v7, s[6:7] ; GISEL-NEXT: v_cmp_eq_u32_e64 s[8:9], 0, v8
; GISEL-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v7, v5, v7, s[8:9]
; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v9 ; GISEL-NEXT: v_subbrev_u32_e64 v1, s[4:5], 0, v1, s[4:5]
; GISEL-NEXT: v_cndmask_b32_e32 v6, v5, v6, vcc ; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v9
; GISEL-NEXT: v_subbrev_u32_e64 v3, vcc, 0, v3, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v6, v5, v6, s[4:5]
; GISEL-NEXT: v_sub_i32_e32 v11, vcc, v0, v4 ; GISEL-NEXT: v_subbrev_u32_e64 v3, s[4:5], 0, v3, s[6:7]
; GISEL-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc ; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v11, v4
; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v11, v4 ; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, -1, s[4:5]
; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, -1, vcc ; GISEL-NEXT: s_mov_b64 s[4:5], vcc
; GISEL-NEXT: v_sub_i32_e32 v13, vcc, v2, v4 ; GISEL-NEXT: v_subrev_i32_e32 v13, vcc, 0x12d8fb, v11
; GISEL-NEXT: v_subbrev_u32_e32 v3, vcc, 0, v3, vcc ; GISEL-NEXT: v_sub_i32_e64 v14, s[6:7], v0, v4
; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v13, v4 ; GISEL-NEXT: v_subbrev_u32_e64 v1, s[6:7], 0, v1, s[6:7]
; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, -1, vcc ; GISEL-NEXT: v_cmp_ge_u32_e64 s[6:7], v14, v4
; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 ; GISEL-NEXT: v_cndmask_b32_e64 v15, 0, -1, s[6:7]
; GISEL-NEXT: v_cndmask_b32_e32 v5, v5, v12, vcc ; GISEL-NEXT: v_subbrev_u32_e64 v3, s[4:5], 0, v3, s[4:5]
; GISEL-NEXT: v_sub_i32_e32 v12, vcc, v11, v4 ; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v1
; GISEL-NEXT: v_subbrev_u32_e32 v15, vcc, 0, v1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v5, v5, v15, s[4:5]
; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3 ; GISEL-NEXT: v_sub_i32_e64 v4, s[4:5], v14, v4
; GISEL-NEXT: v_cndmask_b32_e32 v10, v10, v14, vcc ; GISEL-NEXT: v_subbrev_u32_e64 v15, s[4:5], 0, v1, s[4:5]
; GISEL-NEXT: v_sub_i32_e32 v4, vcc, v13, v4 ; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v3
; GISEL-NEXT: v_subbrev_u32_e32 v14, vcc, 0, v3, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v10, v10, v12, s[4:5]
; GISEL-NEXT: v_subbrev_u32_e32 v12, vcc, 0, v3, vcc
; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5 ; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5
; GISEL-NEXT: v_cndmask_b32_e32 v5, v11, v12, vcc ; GISEL-NEXT: v_cndmask_b32_e32 v4, v14, v4, vcc
; GISEL-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v10 ; GISEL-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v10
; GISEL-NEXT: v_cndmask_b32_e64 v4, v13, v4, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v5, v11, v13, s[4:5]
; GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v15, vcc ; GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v15, vcc
; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7 ; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7
; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc ; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
; GISEL-NEXT: v_cndmask_b32_e64 v3, v3, v14, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v3, v3, v12, s[4:5]
; GISEL-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v6 ; GISEL-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v6
; GISEL-NEXT: v_cndmask_b32_e64 v2, v2, v4, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v2, v2, v5, s[4:5]
; GISEL-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc ; GISEL-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc
; GISEL-NEXT: v_cndmask_b32_e64 v3, v9, v3, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v3, v9, v3, s[4:5]
; GISEL-NEXT: s_setpc_b64 s[30:31] ; GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; CGP-LABEL: v_urem_v2i64_oddk_denom: ; CGP-LABEL: v_urem_v2i64_oddk_denom:
; CGP: ; %bb.0: ; CGP: ; %bb.0:
; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CGP-NEXT: s_mov_b32 s6, 0x12d8fb ; CGP-NEXT: s_mov_b32 s6, 0x12d8fb
▲ Show 20 Lines • Show All 178 Lines • ▼ Show 20 Lines
; CGP-NEXT: v_mul_lo_u32 v13, v7, s6 ; CGP-NEXT: v_mul_lo_u32 v13, v7, s6
; CGP-NEXT: v_mul_hi_u32 v7, s6, v7 ; CGP-NEXT: v_mul_hi_u32 v7, s6, v7
; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v10 ; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v10
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v11 ; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v11
; CGP-NEXT: v_mul_lo_u32 v8, v8, s6 ; CGP-NEXT: v_mul_lo_u32 v8, v8, s6
; CGP-NEXT: v_mul_lo_u32 v9, v9, s6 ; CGP-NEXT: v_mul_lo_u32 v9, v9, s6
; CGP-NEXT: v_add_i32_e32 v6, vcc, v8, v6 ; CGP-NEXT: v_add_i32_e32 v6, vcc, v8, v6
; CGP-NEXT: v_add_i32_e32 v7, vcc, v9, v7 ; CGP-NEXT: v_add_i32_e32 v7, vcc, v9, v7
; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v12 ; CGP-NEXT: v_sub_i32_e64 v0, s[4:5], v0, v12
; CGP-NEXT: v_subb_u32_e64 v8, s[4:5], v1, v6, vcc ; CGP-NEXT: v_subb_u32_e64 v8, vcc, v1, v6, s[4:5]
; CGP-NEXT: v_sub_i32_e64 v1, s[4:5], v1, v6 ; CGP-NEXT: v_sub_i32_e32 v1, vcc, v1, v6
; CGP-NEXT: v_cmp_ge_u32_e64 s[4:5], v0, v4 ; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v4
; CGP-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc
; CGP-NEXT: v_sub_i32_e64 v2, s[4:5], v2, v13 ; CGP-NEXT: v_sub_i32_e64 v2, s[6:7], v2, v13
; CGP-NEXT: v_subb_u32_e64 v9, s[6:7], v3, v7, s[4:5] ; CGP-NEXT: v_subb_u32_e64 v9, vcc, v3, v7, s[6:7]
; CGP-NEXT: v_sub_i32_e64 v3, s[6:7], v3, v7 ; CGP-NEXT: v_sub_i32_e32 v3, vcc, v3, v7
; CGP-NEXT: v_cmp_ge_u32_e64 s[6:7], v2, v4 ; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v2, v4
; CGP-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[6:7] ; CGP-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc
; CGP-NEXT: v_cmp_eq_u32_e64 s[6:7], 0, v8 ; CGP-NEXT: v_sub_i32_e32 v10, vcc, v2, v4
; CGP-NEXT: v_cndmask_b32_e64 v6, v5, v6, s[6:7] ; CGP-NEXT: v_cmp_eq_u32_e64 s[8:9], 0, v8
; CGP-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v6, v5, v6, s[8:9]
; CGP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v9 ; CGP-NEXT: v_subbrev_u32_e64 v1, s[4:5], 0, v1, s[4:5]
; CGP-NEXT: v_cndmask_b32_e32 v7, v5, v7, vcc ; CGP-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v9
; CGP-NEXT: v_subbrev_u32_e64 v3, vcc, 0, v3, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v7, v5, v7, s[4:5]
; CGP-NEXT: v_sub_i32_e32 v10, vcc, v0, v4 ; CGP-NEXT: v_subbrev_u32_e64 v3, s[4:5], 0, v3, s[6:7]
; CGP-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc ; CGP-NEXT: v_cmp_ge_u32_e64 s[4:5], v10, v4
; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v10, v4 ; CGP-NEXT: v_cndmask_b32_e64 v11, 0, -1, s[4:5]
; CGP-NEXT: v_cndmask_b32_e64 v11, 0, -1, vcc ; CGP-NEXT: s_mov_b64 s[4:5], vcc
; CGP-NEXT: v_sub_i32_e32 v12, vcc, v2, v4 ; CGP-NEXT: v_subrev_i32_e32 v12, vcc, 0x12d8fb, v10
; CGP-NEXT: v_subbrev_u32_e32 v3, vcc, 0, v3, vcc ; CGP-NEXT: v_sub_i32_e64 v13, s[6:7], v0, v4
; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v12, v4 ; CGP-NEXT: v_subbrev_u32_e64 v1, s[6:7], 0, v1, s[6:7]
; CGP-NEXT: v_cndmask_b32_e64 v13, 0, -1, vcc ; CGP-NEXT: v_cmp_ge_u32_e64 s[6:7], v13, v4
; CGP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 ; CGP-NEXT: v_cndmask_b32_e64 v14, 0, -1, s[6:7]
; CGP-NEXT: v_cndmask_b32_e32 v11, v5, v11, vcc ; CGP-NEXT: v_subbrev_u32_e64 v3, s[4:5], 0, v3, s[4:5]
; CGP-NEXT: v_sub_i32_e32 v14, vcc, v10, v4 ; CGP-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v1
; CGP-NEXT: v_subbrev_u32_e32 v15, vcc, 0, v1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v14, v5, v14, s[4:5]
; CGP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3 ; CGP-NEXT: v_sub_i32_e64 v4, s[4:5], v13, v4
; CGP-NEXT: v_cndmask_b32_e32 v5, v5, v13, vcc ; CGP-NEXT: v_subbrev_u32_e64 v15, s[4:5], 0, v1, s[4:5]
; CGP-NEXT: v_sub_i32_e32 v4, vcc, v12, v4 ; CGP-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v3
; CGP-NEXT: v_subbrev_u32_e32 v13, vcc, 0, v3, vcc ; CGP-NEXT: v_cndmask_b32_e64 v5, v5, v11, s[4:5]
; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v11 ; CGP-NEXT: v_subbrev_u32_e32 v11, vcc, 0, v3, vcc
; CGP-NEXT: v_cndmask_b32_e32 v10, v10, v14, vcc ; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v14
; CGP-NEXT: v_cndmask_b32_e32 v4, v13, v4, vcc
; CGP-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v5 ; CGP-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v5
; CGP-NEXT: v_cndmask_b32_e64 v4, v12, v4, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v5, v10, v12, s[4:5]
; CGP-NEXT: v_cndmask_b32_e32 v1, v1, v15, vcc ; CGP-NEXT: v_cndmask_b32_e32 v1, v1, v15, vcc
; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6 ; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v10, vcc ; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
; CGP-NEXT: v_cndmask_b32_e64 v3, v3, v13, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v3, v3, v11, s[4:5]
; CGP-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v7 ; CGP-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v7
; CGP-NEXT: v_cndmask_b32_e64 v2, v2, v4, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v2, v2, v5, s[4:5]
; CGP-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc ; CGP-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc
; CGP-NEXT: v_cndmask_b32_e64 v3, v9, v3, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v3, v9, v3, s[4:5]
; CGP-NEXT: s_setpc_b64 s[30:31] ; CGP-NEXT: s_setpc_b64 s[30:31]
%result = urem <2 x i64> %num, <i64 1235195, i64 1235195> %result = urem <2 x i64> %num, <i64 1235195, i64 1235195>
ret <2 x i64> %result ret <2 x i64> %result
} }
define i64 @v_urem_i64_pow2_shl_denom(i64 %x, i64 %y) { define i64 @v_urem_i64_pow2_shl_denom(i64 %x, i64 %y) {
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