Page MenuHomePhabricator

Please use GitHub pull requests for new patches. Avoid migrating existing patches. Phabricator shutdown timeline

Differential D142192 Diff 491241 llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll

Changeset View

Standalone View

View Options

llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 4,231 Lines • ▼ Show 20 Lines; GFX11-NEXT: s_setpc_b64 s[30:31]
%result = call i48 @llvm.ssub.sat.i48(i48 %lhs, i48 %rhs) %result = call i48 @llvm.ssub.sat.i48(i48 %lhs, i48 %rhs)
ret i48 %result ret i48 %result
} }
define amdgpu_ps i48 @s_ssubsat_i48(i48 inreg %lhs, i48 inreg %rhs) { define amdgpu_ps i48 @s_ssubsat_i48(i48 inreg %lhs, i48 inreg %rhs) {
; GFX6-LABEL: s_ssubsat_i48: ; GFX6-LABEL: s_ssubsat_i48:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_sub_u32 s4, s0, s2 ; GFX6-NEXT: s_sub_u32 s4, s0, s2
; GFX6-NEXT: s_subb_u32 s5, s1, s3 ; GFX6-NEXT: s_subb_u32 s3, s1, s3
; GFX6-NEXT: s_bfe_i64 s[0:1], s[0:1], 0x300000 ; GFX6-NEXT: s_bfe_i64 s[0:1], s[0:1], 0x300000
; GFX6-NEXT: v_mov_b32_e32 v0, s0 ; GFX6-NEXT: v_mov_b32_e32 v0, s0
; GFX6-NEXT: s_bfe_i64 s[6:7], s[4:5], 0x300000 ; GFX6-NEXT: s_bfe_i64 s[6:7], s[4:5], 0x300000
; GFX6-NEXT: v_mov_b32_e32 v1, s1 ; GFX6-NEXT: v_mov_b32_e32 v1, s1
; GFX6-NEXT: s_bfe_i64 s[0:1], s[2:3], 0x300000 ; GFX6-NEXT: s_bfe_i64 s[0:1], s[2:3], 0x300000
; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, s[6:7], v[0:1] ; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, s[6:7], v[0:1]
; GFX6-NEXT: v_cmp_gt_i64_e64 s[0:1], s[0:1], 0 ; GFX6-NEXT: v_cmp_gt_i64_e64 s[0:1], s[0:1], 0
; GFX6-NEXT: s_ashr_i32 s3, s7, 31 ; GFX6-NEXT: s_ashr_i32 s2, s7, 31
; GFX6-NEXT: s_ashr_i32 s2, s7, 15 ; GFX6-NEXT: s_ashr_i32 s5, s7, 15
; GFX6-NEXT: s_add_u32 s3, s3, 0xffff8000 ; GFX6-NEXT: s_add_u32 s2, s2, 0xffff8000
; GFX6-NEXT: v_mov_b32_e32 v0, s2 ; GFX6-NEXT: v_mov_b32_e32 v0, s5
; GFX6-NEXT: v_mov_b32_e32 v1, s3 ; GFX6-NEXT: v_mov_b32_e32 v1, s2
; GFX6-NEXT: v_mov_b32_e32 v2, s4 ; GFX6-NEXT: v_mov_b32_e32 v2, s4
; GFX6-NEXT: v_mov_b32_e32 v3, s5 ; GFX6-NEXT: v_mov_b32_e32 v3, s3
; GFX6-NEXT: s_xor_b64 vcc, s[0:1], vcc ; GFX6-NEXT: s_xor_b64 vcc, s[0:1], vcc
; GFX6-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX6-NEXT: v_readfirstlane_b32 s0, v0 ; GFX6-NEXT: v_readfirstlane_b32 s0, v0
; GFX6-NEXT: v_readfirstlane_b32 s1, v1 ; GFX6-NEXT: v_readfirstlane_b32 s1, v1
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX8-LABEL: s_ssubsat_i48: ; GFX8-LABEL: s_ssubsat_i48:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_sub_u32 s4, s0, s2 ; GFX8-NEXT: s_sub_u32 s4, s0, s2
; GFX8-NEXT: s_subb_u32 s5, s1, s3 ; GFX8-NEXT: s_subb_u32 s3, s1, s3
; GFX8-NEXT: s_bfe_i64 s[0:1], s[0:1], 0x300000 ; GFX8-NEXT: s_bfe_i64 s[0:1], s[0:1], 0x300000
; GFX8-NEXT: v_mov_b32_e32 v0, s0 ; GFX8-NEXT: v_mov_b32_e32 v0, s0
; GFX8-NEXT: s_bfe_i64 s[6:7], s[4:5], 0x300000 ; GFX8-NEXT: s_bfe_i64 s[6:7], s[4:5], 0x300000
; GFX8-NEXT: v_mov_b32_e32 v1, s1 ; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: s_bfe_i64 s[0:1], s[2:3], 0x300000 ; GFX8-NEXT: s_bfe_i64 s[0:1], s[2:3], 0x300000
; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, s[6:7], v[0:1] ; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, s[6:7], v[0:1]
; GFX8-NEXT: v_cmp_gt_i64_e64 s[0:1], s[0:1], 0 ; GFX8-NEXT: v_cmp_gt_i64_e64 s[0:1], s[0:1], 0
; GFX8-NEXT: s_ashr_i32 s3, s7, 31 ; GFX8-NEXT: s_ashr_i32 s2, s7, 31
; GFX8-NEXT: s_ashr_i32 s2, s7, 15 ; GFX8-NEXT: s_ashr_i32 s5, s7, 15
; GFX8-NEXT: s_add_u32 s3, s3, 0xffff8000 ; GFX8-NEXT: s_add_u32 s2, s2, 0xffff8000
; GFX8-NEXT: v_mov_b32_e32 v0, s2 ; GFX8-NEXT: v_mov_b32_e32 v0, s5
; GFX8-NEXT: v_mov_b32_e32 v1, s3 ; GFX8-NEXT: v_mov_b32_e32 v1, s2
; GFX8-NEXT: v_mov_b32_e32 v2, s4 ; GFX8-NEXT: v_mov_b32_e32 v2, s4
; GFX8-NEXT: v_mov_b32_e32 v3, s5 ; GFX8-NEXT: v_mov_b32_e32 v3, s3
; GFX8-NEXT: s_xor_b64 vcc, s[0:1], vcc ; GFX8-NEXT: s_xor_b64 vcc, s[0:1], vcc
; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX8-NEXT: v_readfirstlane_b32 s0, v0 ; GFX8-NEXT: v_readfirstlane_b32 s0, v0
; GFX8-NEXT: v_readfirstlane_b32 s1, v1 ; GFX8-NEXT: v_readfirstlane_b32 s1, v1
; GFX8-NEXT: ; return to shader part epilog ; GFX8-NEXT: ; return to shader part epilog
; ;
; GFX9-LABEL: s_ssubsat_i48: ; GFX9-LABEL: s_ssubsat_i48:
Show All 21 Lines
; GFX9-NEXT: ; return to shader part epilog ; GFX9-NEXT: ; return to shader part epilog
; ;
; GFX10-LABEL: s_ssubsat_i48: ; GFX10-LABEL: s_ssubsat_i48:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_lshl_b64 s[0:1], s[0:1], 16 ; GFX10-NEXT: s_lshl_b64 s[0:1], s[0:1], 16
; GFX10-NEXT: s_lshl_b64 s[2:3], s[2:3], 16 ; GFX10-NEXT: s_lshl_b64 s[2:3], s[2:3], 16
; GFX10-NEXT: s_sub_u32 s4, s0, s2 ; GFX10-NEXT: s_sub_u32 s4, s0, s2
; GFX10-NEXT: s_subb_u32 s5, s1, s3 ; GFX10-NEXT: s_subb_u32 s5, s1, s3
; GFX10-NEXT: v_cmp_gt_i64_e64 s2, s[2:3], 0
; GFX10-NEXT: v_cmp_lt_i64_e64 s6, s[4:5], s[0:1]
; GFX10-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-NEXT: v_mov_b32_e32 v0, s4
; GFX10-NEXT: v_cmp_lt_i64_e64 s0, s[4:5], s[0:1]
; GFX10-NEXT: v_cmp_gt_i64_e64 s1, s[2:3], 0
; GFX10-NEXT: v_mov_b32_e32 v1, s5 ; GFX10-NEXT: v_mov_b32_e32 v1, s5
; GFX10-NEXT: s_ashr_i32 s0, s5, 31 ; GFX10-NEXT: s_ashr_i32 s2, s5, 31
; GFX10-NEXT: s_add_u32 s1, s0, 0x80000000 ; GFX10-NEXT: s_add_u32 s3, s2, 0x80000000
; GFX10-NEXT: s_xor_b32 s2, s2, s6 ; GFX10-NEXT: s_xor_b32 s0, s1, s0
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, s0, s2 ; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, s2, s0
; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s1, s2 ; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s3, s0
; GFX10-NEXT: v_ashrrev_i64 v[0:1], 16, v[0:1] ; GFX10-NEXT: v_ashrrev_i64 v[0:1], 16, v[0:1]
; GFX10-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: v_readfirstlane_b32 s1, v1 ; GFX10-NEXT: v_readfirstlane_b32 s1, v1
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
; ;
; GFX11-LABEL: s_ssubsat_i48: ; GFX11-LABEL: s_ssubsat_i48:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_lshl_b64 s[0:1], s[0:1], 16 ; GFX11-NEXT: s_lshl_b64 s[0:1], s[0:1], 16
; GFX11-NEXT: s_lshl_b64 s[2:3], s[2:3], 16 ; GFX11-NEXT: s_lshl_b64 s[2:3], s[2:3], 16
; GFX11-NEXT: s_sub_u32 s4, s0, s2 ; GFX11-NEXT: s_sub_u32 s4, s0, s2
; GFX11-NEXT: s_subb_u32 s5, s1, s3 ; GFX11-NEXT: s_subb_u32 s5, s1, s3
; GFX11-NEXT: v_cmp_gt_i64_e64 s2, s[2:3], 0
; GFX11-NEXT: v_cmp_lt_i64_e64 s6, s[4:5], s[0:1]
; GFX11-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5 ; GFX11-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
; GFX11-NEXT: s_ashr_i32 s0, s5, 31 ; GFX11-NEXT: v_cmp_lt_i64_e64 s0, s[4:5], s[0:1]
; GFX11-NEXT: s_add_u32 s1, s0, 0x80000000 ; GFX11-NEXT: v_cmp_gt_i64_e64 s1, s[2:3], 0
; GFX11-NEXT: s_xor_b32 s2, s2, s6 ; GFX11-NEXT: s_ashr_i32 s2, s5, 31
; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, s0, s2 ; GFX11-NEXT: s_add_u32 s3, s2, 0x80000000
; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s1, s2 ; GFX11-NEXT: s_xor_b32 s0, s1, s0
; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, s2, s0
; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s3, s0
; GFX11-NEXT: v_ashrrev_i64 v[0:1], 16, v[0:1] ; GFX11-NEXT: v_ashrrev_i64 v[0:1], 16, v[0:1]
; GFX11-NEXT: v_readfirstlane_b32 s0, v0 ; GFX11-NEXT: v_readfirstlane_b32 s0, v0
; GFX11-NEXT: v_readfirstlane_b32 s1, v1 ; GFX11-NEXT: v_readfirstlane_b32 s1, v1
; GFX11-NEXT: ; return to shader part epilog ; GFX11-NEXT: ; return to shader part epilog
%result = call i48 @llvm.ssub.sat.i48(i48 %lhs, i48 %rhs) %result = call i48 @llvm.ssub.sat.i48(i48 %lhs, i48 %rhs)
ret i48 %result ret i48 %result
} }
define amdgpu_ps <2 x float> @ssubsat_i48_sv(i48 inreg %lhs, i48 %rhs) { define amdgpu_ps <2 x float> @ssubsat_i48_sv(i48 inreg %lhs, i48 %rhs) {
; GFX6-LABEL: ssubsat_i48_sv: ; GFX6-LABEL: ssubsat_i48_sv:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: v_mov_b32_e32 v3, s1 ; GFX6-NEXT: v_mov_b32_e32 v3, s1
; GFX6-NEXT: v_sub_i32_e32 v2, vcc, s0, v0 ; GFX6-NEXT: v_sub_i32_e32 v2, vcc, s0, v0
; GFX6-NEXT: v_subb_u32_e32 v4, vcc, v3, v1, vcc ; GFX6-NEXT: v_subb_u32_e32 v4, vcc, v3, v1, vcc
; GFX6-NEXT: v_bfe_i32 v3, v2, 0, 16 ; GFX6-NEXT: v_bfe_i32 v3, v2, 0, 16
; GFX6-NEXT: s_bfe_i64 s[0:1], s[0:1], 0x300000 ; GFX6-NEXT: s_bfe_i64 s[0:1], s[0:1], 0x300000
; GFX6-NEXT: v_bfe_i32 v1, v0, 0, 16 ; GFX6-NEXT: v_bfe_i32 v1, v0, 0, 16
; GFX6-NEXT: v_cmp_gt_i64_e64 s[0:1], s[0:1], v[2:3] ; GFX6-NEXT: v_cmp_gt_i64_e64 s[0:1], s[0:1], v[2:3]
; GFX6-NEXT: v_cmp_lt_i64_e64 s[2:3], 0, v[0:1] ; GFX6-NEXT: v_cmp_lt_i64_e64 s[2:3], 0, v[0:1]
; GFX6-NEXT: v_ashrrev_i32_e32 v0, 31, v3 ; GFX6-NEXT: v_ashrrev_i32_e32 v0, 31, v3
; GFX6-NEXT: v_ashrrev_i32_e32 v1, 15, v3 ; GFX6-NEXT: v_ashrrev_i32_e32 v1, 15, v3
; GFX6-NEXT: v_mov_b32_e32 v3, 0xffff8000 ; GFX6-NEXT: v_add_i32_e32 v3, vcc, 0xffff8000, v0
; GFX6-NEXT: v_add_i32_e32 v3, vcc, v0, v3
; GFX6-NEXT: s_xor_b64 vcc, s[2:3], s[0:1] ; GFX6-NEXT: s_xor_b64 vcc, s[2:3], s[0:1]
; GFX6-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc
; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1 ; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX8-LABEL: ssubsat_i48_sv: ; GFX8-LABEL: ssubsat_i48_sv:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: v_mov_b32_e32 v3, s1 ; GFX8-NEXT: v_mov_b32_e32 v3, s1
; GFX8-NEXT: v_sub_u32_e32 v2, vcc, s0, v0 ; GFX8-NEXT: v_sub_u32_e32 v2, vcc, s0, v0
; GFX8-NEXT: v_subb_u32_e32 v4, vcc, v3, v1, vcc ; GFX8-NEXT: v_subb_u32_e32 v4, vcc, v3, v1, vcc
; GFX8-NEXT: v_bfe_i32 v3, v2, 0, 16 ; GFX8-NEXT: v_bfe_i32 v3, v2, 0, 16
; GFX8-NEXT: s_bfe_i64 s[0:1], s[0:1], 0x300000 ; GFX8-NEXT: s_bfe_i64 s[0:1], s[0:1], 0x300000
; GFX8-NEXT: v_bfe_i32 v1, v0, 0, 16 ; GFX8-NEXT: v_bfe_i32 v1, v0, 0, 16
; GFX8-NEXT: v_cmp_gt_i64_e64 s[0:1], s[0:1], v[2:3] ; GFX8-NEXT: v_cmp_gt_i64_e64 s[0:1], s[0:1], v[2:3]
; GFX8-NEXT: v_cmp_lt_i64_e64 s[2:3], 0, v[0:1] ; GFX8-NEXT: v_cmp_lt_i64_e64 s[2:3], 0, v[0:1]
; GFX8-NEXT: v_ashrrev_i32_e32 v0, 31, v3 ; GFX8-NEXT: v_ashrrev_i32_e32 v0, 31, v3
; GFX8-NEXT: v_ashrrev_i32_e32 v1, 15, v3 ; GFX8-NEXT: v_ashrrev_i32_e32 v1, 15, v3
; GFX8-NEXT: v_mov_b32_e32 v3, 0xffff8000 ; GFX8-NEXT: v_add_u32_e32 v3, vcc, 0xffff8000, v0
; GFX8-NEXT: v_add_u32_e32 v3, vcc, v0, v3
; GFX8-NEXT: s_xor_b64 vcc, s[2:3], s[0:1] ; GFX8-NEXT: s_xor_b64 vcc, s[2:3], s[0:1]
; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc
; GFX8-NEXT: v_and_b32_e32 v1, 0xffff, v1 ; GFX8-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX8-NEXT: ; return to shader part epilog ; GFX8-NEXT: ; return to shader part epilog
; ;
; GFX9-LABEL: ssubsat_i48_sv: ; GFX9-LABEL: ssubsat_i48_sv:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: v_lshlrev_b64 v[0:1], 16, v[0:1] ; GFX9-NEXT: v_lshlrev_b64 v[0:1], 16, v[0:1]
; GFX9-NEXT: s_lshl_b64 s[0:1], s[0:1], 16 ; GFX9-NEXT: s_lshl_b64 s[0:1], s[0:1], 16
; GFX9-NEXT: v_mov_b32_e32 v3, s1 ; GFX9-NEXT: v_mov_b32_e32 v3, s1
; GFX9-NEXT: v_sub_co_u32_e32 v2, vcc, s0, v0 ; GFX9-NEXT: v_sub_co_u32_e32 v2, vcc, s0, v0
; GFX9-NEXT: v_subb_co_u32_e32 v3, vcc, v3, v1, vcc ; GFX9-NEXT: v_subb_co_u32_e32 v3, vcc, v3, v1, vcc
; GFX9-NEXT: v_cmp_gt_i64_e64 s[0:1], s[0:1], v[2:3] ; GFX9-NEXT: v_cmp_gt_i64_e64 s[0:1], s[0:1], v[2:3]
; GFX9-NEXT: v_cmp_lt_i64_e64 s[2:3], 0, v[0:1] ; GFX9-NEXT: v_cmp_lt_i64_e64 s[2:3], 0, v[0:1]
; GFX9-NEXT: v_ashrrev_i32_e32 v0, 31, v3 ; GFX9-NEXT: v_ashrrev_i32_e32 v0, 31, v3
; GFX9-NEXT: v_bfrev_b32_e32 v1, 1 ; GFX9-NEXT: v_add_co_u32_e32 v1, vcc, 0x80000000, v0
; GFX9-NEXT: v_add_co_u32_e32 v1, vcc, v0, v1
; GFX9-NEXT: s_xor_b64 vcc, s[2:3], s[0:1] ; GFX9-NEXT: s_xor_b64 vcc, s[2:3], s[0:1]
; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX9-NEXT: v_ashrrev_i64 v[0:1], 16, v[0:1] ; GFX9-NEXT: v_ashrrev_i64 v[0:1], 16, v[0:1]
; GFX9-NEXT: v_and_b32_e32 v1, 0xffff, v1 ; GFX9-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX9-NEXT: ; return to shader part epilog ; GFX9-NEXT: ; return to shader part epilog
; ;
; GFX10-LABEL: ssubsat_i48_sv: ; GFX10-LABEL: ssubsat_i48_sv:
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
; GFX6-NEXT: v_subb_u32_e32 v4, vcc, v1, v3, vcc ; GFX6-NEXT: v_subb_u32_e32 v4, vcc, v1, v3, vcc
; GFX6-NEXT: v_bfe_i32 v3, v2, 0, 16 ; GFX6-NEXT: v_bfe_i32 v3, v2, 0, 16
; GFX6-NEXT: v_bfe_i32 v1, v0, 0, 16 ; GFX6-NEXT: v_bfe_i32 v1, v0, 0, 16
; GFX6-NEXT: s_bfe_i64 s[0:1], s[0:1], 0x300000 ; GFX6-NEXT: s_bfe_i64 s[0:1], s[0:1], 0x300000
; GFX6-NEXT: v_cmp_lt_i64_e64 s[2:3], v[2:3], v[0:1] ; GFX6-NEXT: v_cmp_lt_i64_e64 s[2:3], v[2:3], v[0:1]
; GFX6-NEXT: v_cmp_gt_i64_e64 s[0:1], s[0:1], 0 ; GFX6-NEXT: v_cmp_gt_i64_e64 s[0:1], s[0:1], 0
; GFX6-NEXT: v_ashrrev_i32_e32 v0, 31, v3 ; GFX6-NEXT: v_ashrrev_i32_e32 v0, 31, v3
; GFX6-NEXT: v_ashrrev_i32_e32 v1, 15, v3 ; GFX6-NEXT: v_ashrrev_i32_e32 v1, 15, v3
; GFX6-NEXT: v_mov_b32_e32 v3, 0xffff8000 ; GFX6-NEXT: v_add_i32_e32 v3, vcc, 0xffff8000, v0
; GFX6-NEXT: v_add_i32_e32 v3, vcc, v0, v3
; GFX6-NEXT: s_xor_b64 vcc, s[0:1], s[2:3] ; GFX6-NEXT: s_xor_b64 vcc, s[0:1], s[2:3]
; GFX6-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc
; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1 ; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX8-LABEL: ssubsat_i48_vs: ; GFX8-LABEL: ssubsat_i48_vs:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: v_mov_b32_e32 v3, s1 ; GFX8-NEXT: v_mov_b32_e32 v3, s1
; GFX8-NEXT: v_subrev_u32_e32 v2, vcc, s0, v0 ; GFX8-NEXT: v_subrev_u32_e32 v2, vcc, s0, v0
; GFX8-NEXT: v_subb_u32_e32 v4, vcc, v1, v3, vcc ; GFX8-NEXT: v_subb_u32_e32 v4, vcc, v1, v3, vcc
; GFX8-NEXT: v_bfe_i32 v3, v2, 0, 16 ; GFX8-NEXT: v_bfe_i32 v3, v2, 0, 16
; GFX8-NEXT: v_bfe_i32 v1, v0, 0, 16 ; GFX8-NEXT: v_bfe_i32 v1, v0, 0, 16
; GFX8-NEXT: s_bfe_i64 s[0:1], s[0:1], 0x300000 ; GFX8-NEXT: s_bfe_i64 s[0:1], s[0:1], 0x300000
; GFX8-NEXT: v_cmp_lt_i64_e64 s[2:3], v[2:3], v[0:1] ; GFX8-NEXT: v_cmp_lt_i64_e64 s[2:3], v[2:3], v[0:1]
; GFX8-NEXT: v_cmp_gt_i64_e64 s[0:1], s[0:1], 0 ; GFX8-NEXT: v_cmp_gt_i64_e64 s[0:1], s[0:1], 0
; GFX8-NEXT: v_ashrrev_i32_e32 v0, 31, v3 ; GFX8-NEXT: v_ashrrev_i32_e32 v0, 31, v3
; GFX8-NEXT: v_ashrrev_i32_e32 v1, 15, v3 ; GFX8-NEXT: v_ashrrev_i32_e32 v1, 15, v3
; GFX8-NEXT: v_mov_b32_e32 v3, 0xffff8000 ; GFX8-NEXT: v_add_u32_e32 v3, vcc, 0xffff8000, v0
; GFX8-NEXT: v_add_u32_e32 v3, vcc, v0, v3
; GFX8-NEXT: s_xor_b64 vcc, s[0:1], s[2:3] ; GFX8-NEXT: s_xor_b64 vcc, s[0:1], s[2:3]
; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc
; GFX8-NEXT: v_and_b32_e32 v1, 0xffff, v1 ; GFX8-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX8-NEXT: ; return to shader part epilog ; GFX8-NEXT: ; return to shader part epilog
; ;
; GFX9-LABEL: ssubsat_i48_vs: ; GFX9-LABEL: ssubsat_i48_vs:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: v_lshlrev_b64 v[0:1], 16, v[0:1] ; GFX9-NEXT: v_lshlrev_b64 v[0:1], 16, v[0:1]
; GFX9-NEXT: s_lshl_b64 s[2:3], s[0:1], 16 ; GFX9-NEXT: s_lshl_b64 s[2:3], s[0:1], 16
; GFX9-NEXT: v_mov_b32_e32 v3, s3 ; GFX9-NEXT: v_mov_b32_e32 v3, s3
; GFX9-NEXT: v_subrev_co_u32_e32 v2, vcc, s2, v0 ; GFX9-NEXT: v_subrev_co_u32_e32 v2, vcc, s2, v0
; GFX9-NEXT: v_subb_co_u32_e32 v3, vcc, v1, v3, vcc ; GFX9-NEXT: v_subb_co_u32_e32 v3, vcc, v1, v3, vcc
; GFX9-NEXT: v_cmp_lt_i64_e64 s[0:1], v[2:3], v[0:1] ; GFX9-NEXT: v_cmp_lt_i64_e64 s[0:1], v[2:3], v[0:1]
; GFX9-NEXT: v_cmp_gt_i64_e64 s[2:3], s[2:3], 0 ; GFX9-NEXT: v_cmp_gt_i64_e64 s[2:3], s[2:3], 0
; GFX9-NEXT: v_ashrrev_i32_e32 v0, 31, v3 ; GFX9-NEXT: v_ashrrev_i32_e32 v0, 31, v3
; GFX9-NEXT: v_bfrev_b32_e32 v1, 1 ; GFX9-NEXT: v_add_co_u32_e32 v1, vcc, 0x80000000, v0
; GFX9-NEXT: v_add_co_u32_e32 v1, vcc, v0, v1
; GFX9-NEXT: s_xor_b64 vcc, s[2:3], s[0:1] ; GFX9-NEXT: s_xor_b64 vcc, s[2:3], s[0:1]
; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX9-NEXT: v_ashrrev_i64 v[0:1], 16, v[0:1] ; GFX9-NEXT: v_ashrrev_i64 v[0:1], 16, v[0:1]
; GFX9-NEXT: v_and_b32_e32 v1, 0xffff, v1 ; GFX9-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX9-NEXT: ; return to shader part epilog ; GFX9-NEXT: ; return to shader part epilog
; ;
; GFX10-LABEL: ssubsat_i48_vs: ; GFX10-LABEL: ssubsat_i48_vs:
▲ Show 20 Lines • Show All 172 Lines • ▼ Show 20 Lines
; GFX9-NEXT: v_readfirstlane_b32 s0, v0 ; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: v_readfirstlane_b32 s1, v1 ; GFX9-NEXT: v_readfirstlane_b32 s1, v1
; GFX9-NEXT: ; return to shader part epilog ; GFX9-NEXT: ; return to shader part epilog
; ;
; GFX10-LABEL: s_ssubsat_i64: ; GFX10-LABEL: s_ssubsat_i64:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_sub_u32 s4, s0, s2 ; GFX10-NEXT: s_sub_u32 s4, s0, s2
; GFX10-NEXT: s_subb_u32 s5, s1, s3 ; GFX10-NEXT: s_subb_u32 s5, s1, s3
; GFX10-NEXT: v_cmp_gt_i64_e64 s2, s[2:3], 0
; GFX10-NEXT: v_cmp_lt_i64_e64 s6, s[4:5], s[0:1]
; GFX10-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-NEXT: v_mov_b32_e32 v0, s4
; GFX10-NEXT: v_cmp_lt_i64_e64 s0, s[4:5], s[0:1]
; GFX10-NEXT: v_cmp_gt_i64_e64 s1, s[2:3], 0
; GFX10-NEXT: v_mov_b32_e32 v1, s5 ; GFX10-NEXT: v_mov_b32_e32 v1, s5
; GFX10-NEXT: s_ashr_i32 s0, s5, 31 ; GFX10-NEXT: s_ashr_i32 s2, s5, 31
; GFX10-NEXT: s_add_u32 s1, s0, 0x80000000 ; GFX10-NEXT: s_add_u32 s3, s2, 0x80000000
; GFX10-NEXT: s_xor_b32 s2, s2, s6 ; GFX10-NEXT: s_xor_b32 s0, s1, s0
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, s0, s2 ; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, s2, s0
; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s1, s2 ; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s3, s0
; GFX10-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: v_readfirstlane_b32 s1, v1 ; GFX10-NEXT: v_readfirstlane_b32 s1, v1
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
; ;
; GFX11-LABEL: s_ssubsat_i64: ; GFX11-LABEL: s_ssubsat_i64:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_sub_u32 s4, s0, s2 ; GFX11-NEXT: s_sub_u32 s4, s0, s2
; GFX11-NEXT: s_subb_u32 s5, s1, s3 ; GFX11-NEXT: s_subb_u32 s5, s1, s3
; GFX11-NEXT: v_cmp_gt_i64_e64 s2, s[2:3], 0
; GFX11-NEXT: v_cmp_lt_i64_e64 s6, s[4:5], s[0:1]
; GFX11-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5 ; GFX11-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
; GFX11-NEXT: s_ashr_i32 s0, s5, 31 ; GFX11-NEXT: v_cmp_lt_i64_e64 s0, s[4:5], s[0:1]
; GFX11-NEXT: s_add_u32 s1, s0, 0x80000000 ; GFX11-NEXT: v_cmp_gt_i64_e64 s1, s[2:3], 0
; GFX11-NEXT: s_xor_b32 s2, s2, s6 ; GFX11-NEXT: s_ashr_i32 s2, s5, 31
; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, s0, s2 ; GFX11-NEXT: s_add_u32 s3, s2, 0x80000000
; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s1, s2 ; GFX11-NEXT: s_xor_b32 s0, s1, s0
; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, s2, s0
; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s3, s0
; GFX11-NEXT: v_readfirstlane_b32 s0, v0 ; GFX11-NEXT: v_readfirstlane_b32 s0, v0
; GFX11-NEXT: v_readfirstlane_b32 s1, v1 ; GFX11-NEXT: v_readfirstlane_b32 s1, v1
; GFX11-NEXT: ; return to shader part epilog ; GFX11-NEXT: ; return to shader part epilog
%result = call i64 @llvm.ssub.sat.i64(i64 %lhs, i64 %rhs) %result = call i64 @llvm.ssub.sat.i64(i64 %lhs, i64 %rhs)
ret i64 %result ret i64 %result
} }
define amdgpu_ps <2 x float> @ssubsat_i64_sv(i64 inreg %lhs, i64 %rhs) { define amdgpu_ps <2 x float> @ssubsat_i64_sv(i64 inreg %lhs, i64 %rhs) {
▲ Show 20 Lines • Show All 376 Lines • ▼ Show 20 Lines
; GFX9-NEXT: v_readfirstlane_b32 s2, v0 ; GFX9-NEXT: v_readfirstlane_b32 s2, v0
; GFX9-NEXT: v_readfirstlane_b32 s3, v1 ; GFX9-NEXT: v_readfirstlane_b32 s3, v1
; GFX9-NEXT: ; return to shader part epilog ; GFX9-NEXT: ; return to shader part epilog
; ;
; GFX10-LABEL: s_ssubsat_v2i64: ; GFX10-LABEL: s_ssubsat_v2i64:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_sub_u32 s8, s0, s4 ; GFX10-NEXT: s_sub_u32 s8, s0, s4
; GFX10-NEXT: s_subb_u32 s9, s1, s5 ; GFX10-NEXT: s_subb_u32 s9, s1, s5
; GFX10-NEXT: v_cmp_gt_i64_e64 s4, s[4:5], 0
; GFX10-NEXT: v_cmp_lt_i64_e64 s10, s[8:9], s[0:1]
; GFX10-NEXT: s_ashr_i32 s0, s9, 31
; GFX10-NEXT: v_mov_b32_e32 v0, s8 ; GFX10-NEXT: v_mov_b32_e32 v0, s8
; GFX10-NEXT: s_add_u32 s1, s0, 0x80000000 ; GFX10-NEXT: v_cmp_lt_i64_e64 s0, s[8:9], s[0:1]
; GFX10-NEXT: v_cmp_gt_i64_e64 s1, s[4:5], 0
; GFX10-NEXT: s_ashr_i32 s4, s9, 31
; GFX10-NEXT: v_mov_b32_e32 v1, s9 ; GFX10-NEXT: v_mov_b32_e32 v1, s9
; GFX10-NEXT: s_xor_b32 s8, s4, s10 ; GFX10-NEXT: s_add_u32 s5, s4, 0x80000000
; GFX10-NEXT: s_sub_u32 s4, s2, s6 ; GFX10-NEXT: s_xor_b32 s8, s1, s0
; GFX10-NEXT: s_subb_u32 s5, s3, s7 ; GFX10-NEXT: s_sub_u32 s0, s2, s6
; GFX10-NEXT: v_mov_b32_e32 v2, s4 ; GFX10-NEXT: s_subb_u32 s1, s3, s7
; GFX10-NEXT: v_cmp_lt_i64_e64 s2, s[4:5], s[2:3] ; GFX10-NEXT: v_mov_b32_e32 v2, s0
; GFX10-NEXT: v_cmp_lt_i64_e64 s2, s[0:1], s[2:3]
; GFX10-NEXT: v_cmp_gt_i64_e64 s3, s[6:7], 0 ; GFX10-NEXT: v_cmp_gt_i64_e64 s3, s[6:7], 0
; GFX10-NEXT: v_mov_b32_e32 v3, s5 ; GFX10-NEXT: v_mov_b32_e32 v3, s1
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, s0, s8 ; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, s4, s8
; GFX10-NEXT: s_ashr_i32 s0, s5, 31 ; GFX10-NEXT: s_ashr_i32 s4, s1, 31
; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s1, s8 ; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s5, s8
; GFX10-NEXT: s_add_u32 s1, s0, 0x80000000 ; GFX10-NEXT: s_add_u32 s0, s4, 0x80000000
; GFX10-NEXT: s_xor_b32 s2, s3, s2 ; GFX10-NEXT: s_xor_b32 s1, s3, s2
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s0, s2 ; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s4, s1
; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, s1, s2 ; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, s0, s1
; GFX10-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: v_readfirstlane_b32 s1, v1 ; GFX10-NEXT: v_readfirstlane_b32 s1, v1
; GFX10-NEXT: v_readfirstlane_b32 s2, v2 ; GFX10-NEXT: v_readfirstlane_b32 s2, v2
; GFX10-NEXT: v_readfirstlane_b32 s3, v3 ; GFX10-NEXT: v_readfirstlane_b32 s3, v3
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
; ;
; GFX11-LABEL: s_ssubsat_v2i64: ; GFX11-LABEL: s_ssubsat_v2i64:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_sub_u32 s8, s0, s4 ; GFX11-NEXT: s_sub_u32 s8, s0, s4
; GFX11-NEXT: s_subb_u32 s9, s1, s5 ; GFX11-NEXT: s_subb_u32 s9, s1, s5
; GFX11-NEXT: v_cmp_gt_i64_e64 s4, s[4:5], 0
; GFX11-NEXT: v_cmp_lt_i64_e64 s10, s[8:9], s[0:1]
; GFX11-NEXT: s_ashr_i32 s0, s9, 31
; GFX11-NEXT: v_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v1, s9 ; GFX11-NEXT: v_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v1, s9
; GFX11-NEXT: s_add_u32 s1, s0, 0x80000000 ; GFX11-NEXT: v_cmp_lt_i64_e64 s0, s[8:9], s[0:1]
; GFX11-NEXT: s_xor_b32 s8, s4, s10 ; GFX11-NEXT: v_cmp_gt_i64_e64 s1, s[4:5], 0
; GFX11-NEXT: s_sub_u32 s4, s2, s6 ; GFX11-NEXT: s_ashr_i32 s4, s9, 31
; GFX11-NEXT: s_subb_u32 s5, s3, s7 ; GFX11-NEXT: s_add_u32 s5, s4, 0x80000000
; GFX11-NEXT: v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5 ; GFX11-NEXT: s_xor_b32 s8, s1, s0
; GFX11-NEXT: v_cmp_lt_i64_e64 s2, s[4:5], s[2:3] ; GFX11-NEXT: s_sub_u32 s0, s2, s6
; GFX11-NEXT: s_subb_u32 s1, s3, s7
; GFX11-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
; GFX11-NEXT: v_cmp_lt_i64_e64 s2, s[0:1], s[2:3]
; GFX11-NEXT: v_cmp_gt_i64_e64 s3, s[6:7], 0 ; GFX11-NEXT: v_cmp_gt_i64_e64 s3, s[6:7], 0
; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, s0, s8 ; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, s4, s8
; GFX11-NEXT: s_ashr_i32 s0, s5, 31 ; GFX11-NEXT: s_ashr_i32 s4, s1, 31
; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s1, s8 ; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s5, s8
; GFX11-NEXT: s_add_u32 s1, s0, 0x80000000 ; GFX11-NEXT: s_add_u32 s0, s4, 0x80000000
; GFX11-NEXT: s_xor_b32 s2, s3, s2 ; GFX11-NEXT: s_xor_b32 s1, s3, s2
; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, s0, s2 ; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, s4, s1
; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, s1, s2 ; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, s0, s1
; GFX11-NEXT: v_readfirstlane_b32 s0, v0 ; GFX11-NEXT: v_readfirstlane_b32 s0, v0
; GFX11-NEXT: v_readfirstlane_b32 s1, v1 ; GFX11-NEXT: v_readfirstlane_b32 s1, v1
; GFX11-NEXT: v_readfirstlane_b32 s2, v2 ; GFX11-NEXT: v_readfirstlane_b32 s2, v2
; GFX11-NEXT: v_readfirstlane_b32 s3, v3 ; GFX11-NEXT: v_readfirstlane_b32 s3, v3
; GFX11-NEXT: ; return to shader part epilog ; GFX11-NEXT: ; return to shader part epilog
%result = call <2 x i64> @llvm.ssub.sat.v2i64(<2 x i64> %lhs, <2 x i64> %rhs) %result = call <2 x i64> @llvm.ssub.sat.v2i64(<2 x i64> %lhs, <2 x i64> %rhs)
ret <2 x i64> %result ret <2 x i64> %result
} }
Show All 21 Lines
; GFX6-NEXT: v_cmp_eq_u64_e64 vcc, s[6:7], 0 ; GFX6-NEXT: v_cmp_eq_u64_e64 vcc, s[6:7], 0
; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1] ; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1]
; GFX6-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
; GFX6-NEXT: v_xor_b32_e32 v0, v1, v0 ; GFX6-NEXT: v_xor_b32_e32 v0, v1, v0
; GFX6-NEXT: s_ashr_i32 s0, s11, 31 ; GFX6-NEXT: s_ashr_i32 s0, s11, 31
; GFX6-NEXT: v_and_b32_e32 v0, 1, v0 ; GFX6-NEXT: v_and_b32_e32 v0, 1, v0
; GFX6-NEXT: s_add_u32 s1, s0, 0x80000000 ; GFX6-NEXT: s_add_u32 s1, s0, 0x80000000
; GFX6-NEXT: v_mov_b32_e32 v1, s0 ; GFX6-NEXT: v_mov_b32_e32 v1, s0
; GFX6-NEXT: v_mov_b32_e32 v2, s0 ; GFX6-NEXT: v_mov_b32_e32 v2, s8
; GFX6-NEXT: v_mov_b32_e32 v3, s8 ; GFX6-NEXT: v_mov_b32_e32 v3, s9
; GFX6-NEXT: v_mov_b32_e32 v4, s9
; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 ; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; GFX6-NEXT: v_cndmask_b32_e32 v0, v3, v1, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v1, v4, v2, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v2, v3, v1, vcc
; GFX6-NEXT: v_mov_b32_e32 v3, s1 ; GFX6-NEXT: v_mov_b32_e32 v3, s1
; GFX6-NEXT: v_mov_b32_e32 v4, s10 ; GFX6-NEXT: v_mov_b32_e32 v4, s10
; GFX6-NEXT: v_mov_b32_e32 v5, s11 ; GFX6-NEXT: v_mov_b32_e32 v5, s11
; GFX6-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
; GFX6-NEXT: v_readfirstlane_b32 s0, v0 ; GFX6-NEXT: v_readfirstlane_b32 s0, v0
; GFX6-NEXT: v_readfirstlane_b32 s1, v1 ; GFX6-NEXT: v_readfirstlane_b32 s1, v2
; GFX6-NEXT: v_readfirstlane_b32 s2, v2 ; GFX6-NEXT: v_readfirstlane_b32 s2, v1
; GFX6-NEXT: v_readfirstlane_b32 s3, v3 ; GFX6-NEXT: v_readfirstlane_b32 s3, v3
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX8-LABEL: s_ssubsat_i128: ; GFX8-LABEL: s_ssubsat_i128:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_sub_u32 s8, s0, s4 ; GFX8-NEXT: s_sub_u32 s8, s0, s4
; GFX8-NEXT: s_subb_u32 s9, s1, s5 ; GFX8-NEXT: s_subb_u32 s9, s1, s5
; GFX8-NEXT: v_mov_b32_e32 v3, s1 ; GFX8-NEXT: v_mov_b32_e32 v3, s1
Show All 20 Lines
; GFX8-NEXT: s_and_b32 s0, 1, s2 ; GFX8-NEXT: s_and_b32 s0, 1, s2
; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 ; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
; GFX8-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
; GFX8-NEXT: v_xor_b32_e32 v0, v1, v0 ; GFX8-NEXT: v_xor_b32_e32 v0, v1, v0
; GFX8-NEXT: s_ashr_i32 s0, s11, 31 ; GFX8-NEXT: s_ashr_i32 s0, s11, 31
; GFX8-NEXT: v_and_b32_e32 v0, 1, v0 ; GFX8-NEXT: v_and_b32_e32 v0, 1, v0
; GFX8-NEXT: s_add_u32 s1, s0, 0x80000000 ; GFX8-NEXT: s_add_u32 s1, s0, 0x80000000
; GFX8-NEXT: v_mov_b32_e32 v1, s0 ; GFX8-NEXT: v_mov_b32_e32 v1, s0
; GFX8-NEXT: v_mov_b32_e32 v2, s0 ; GFX8-NEXT: v_mov_b32_e32 v2, s8
; GFX8-NEXT: v_mov_b32_e32 v3, s8 ; GFX8-NEXT: v_mov_b32_e32 v3, s9
; GFX8-NEXT: v_mov_b32_e32 v4, s9
; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 ; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v1, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v1, v4, v2, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v2, v3, v1, vcc
; GFX8-NEXT: v_mov_b32_e32 v2, s0
; GFX8-NEXT: v_mov_b32_e32 v3, s1 ; GFX8-NEXT: v_mov_b32_e32 v3, s1
; GFX8-NEXT: v_mov_b32_e32 v4, s10 ; GFX8-NEXT: v_mov_b32_e32 v4, s10
; GFX8-NEXT: v_mov_b32_e32 v5, s11 ; GFX8-NEXT: v_mov_b32_e32 v5, s11
; GFX8-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
; GFX8-NEXT: v_readfirstlane_b32 s0, v0 ; GFX8-NEXT: v_readfirstlane_b32 s0, v0
; GFX8-NEXT: v_readfirstlane_b32 s1, v1 ; GFX8-NEXT: v_readfirstlane_b32 s1, v2
; GFX8-NEXT: v_readfirstlane_b32 s2, v2 ; GFX8-NEXT: v_readfirstlane_b32 s2, v1
; GFX8-NEXT: v_readfirstlane_b32 s3, v3 ; GFX8-NEXT: v_readfirstlane_b32 s3, v3
; GFX8-NEXT: ; return to shader part epilog ; GFX8-NEXT: ; return to shader part epilog
; ;
; GFX9-LABEL: s_ssubsat_i128: ; GFX9-LABEL: s_ssubsat_i128:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_sub_u32 s8, s0, s4 ; GFX9-NEXT: s_sub_u32 s8, s0, s4
; GFX9-NEXT: s_subb_u32 s9, s1, s5 ; GFX9-NEXT: s_subb_u32 s9, s1, s5
; GFX9-NEXT: v_mov_b32_e32 v3, s1 ; GFX9-NEXT: v_mov_b32_e32 v3, s1
Show All 20 Lines
; GFX9-NEXT: s_and_b32 s0, 1, s2 ; GFX9-NEXT: s_and_b32 s0, 1, s2
; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 ; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
; GFX9-NEXT: v_xor_b32_e32 v0, v1, v0 ; GFX9-NEXT: v_xor_b32_e32 v0, v1, v0
; GFX9-NEXT: s_ashr_i32 s0, s11, 31 ; GFX9-NEXT: s_ashr_i32 s0, s11, 31
; GFX9-NEXT: v_and_b32_e32 v0, 1, v0 ; GFX9-NEXT: v_and_b32_e32 v0, 1, v0
; GFX9-NEXT: s_add_u32 s1, s0, 0x80000000 ; GFX9-NEXT: s_add_u32 s1, s0, 0x80000000
; GFX9-NEXT: v_mov_b32_e32 v1, s0 ; GFX9-NEXT: v_mov_b32_e32 v1, s0
; GFX9-NEXT: v_mov_b32_e32 v2, s0 ; GFX9-NEXT: v_mov_b32_e32 v2, s8
; GFX9-NEXT: v_mov_b32_e32 v3, s8 ; GFX9-NEXT: v_mov_b32_e32 v3, s9
; GFX9-NEXT: v_mov_b32_e32 v4, s9
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; GFX9-NEXT: v_cndmask_b32_e32 v0, v3, v1, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v1, v4, v2, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v1, vcc
; GFX9-NEXT: v_mov_b32_e32 v2, s0
; GFX9-NEXT: v_mov_b32_e32 v3, s1 ; GFX9-NEXT: v_mov_b32_e32 v3, s1
; GFX9-NEXT: v_mov_b32_e32 v4, s10 ; GFX9-NEXT: v_mov_b32_e32 v4, s10
; GFX9-NEXT: v_mov_b32_e32 v5, s11 ; GFX9-NEXT: v_mov_b32_e32 v5, s11
; GFX9-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
; GFX9-NEXT: v_readfirstlane_b32 s0, v0 ; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: v_readfirstlane_b32 s1, v1 ; GFX9-NEXT: v_readfirstlane_b32 s1, v2
; GFX9-NEXT: v_readfirstlane_b32 s2, v2 ; GFX9-NEXT: v_readfirstlane_b32 s2, v1
; GFX9-NEXT: v_readfirstlane_b32 s3, v3 ; GFX9-NEXT: v_readfirstlane_b32 s3, v3
; GFX9-NEXT: ; return to shader part epilog ; GFX9-NEXT: ; return to shader part epilog
; ;
; GFX10-LABEL: s_ssubsat_i128: ; GFX10-LABEL: s_ssubsat_i128:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_sub_u32 s8, s0, s4 ; GFX10-NEXT: s_sub_u32 s8, s0, s4
; GFX10-NEXT: s_subb_u32 s9, s1, s5 ; GFX10-NEXT: s_subb_u32 s9, s1, s5
; GFX10-NEXT: s_subb_u32 s10, s2, s6 ; GFX10-NEXT: s_subb_u32 s10, s2, s6
; GFX10-NEXT: v_cmp_lt_u64_e64 s0, s[8:9], s[0:1] ; GFX10-NEXT: v_cmp_lt_u64_e64 s0, s[8:9], s[0:1]
; GFX10-NEXT: s_subb_u32 s11, s3, s7 ; GFX10-NEXT: s_subb_u32 s11, s3, s7
; GFX10-NEXT: s_cmp_eq_u64 s[10:11], s[2:3] ; GFX10-NEXT: s_cmp_eq_u64 s[10:11], s[2:3]
; GFX10-NEXT: s_cselect_b32 s12, 1, 0 ; GFX10-NEXT: s_cselect_b32 s12, 1, 0
; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
; GFX10-NEXT: v_cmp_lt_i64_e64 s0, s[10:11], s[2:3] ; GFX10-NEXT: v_cmp_lt_i64_e64 s0, s[10:11], s[2:3]
; GFX10-NEXT: v_cmp_gt_u64_e64 s2, s[4:5], 0 ; GFX10-NEXT: v_cmp_gt_u64_e64 s2, s[4:5], 0
; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s0
; GFX10-NEXT: s_and_b32 s0, 1, s12 ; GFX10-NEXT: s_and_b32 s0, 1, s12
; GFX10-NEXT: s_cmp_eq_u64 s[6:7], 0 ; GFX10-NEXT: s_cmp_eq_u64 s[6:7], 0
; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, s2 ; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, s2
; GFX10-NEXT: v_cmp_gt_i64_e64 s2, s[6:7], 0 ; GFX10-NEXT: v_cmp_gt_i64_e64 s2, s[6:7], 0
; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0 ; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0
; GFX10-NEXT: s_cselect_b32 s1, 1, 0 ; GFX10-NEXT: s_cselect_b32 s1, 1, 0
; GFX10-NEXT: s_ashr_i32 s0, s11, 31 ; GFX10-NEXT: s_ashr_i32 s0, s11, 31
; GFX10-NEXT: s_and_b32 s1, 1, s1 ; GFX10-NEXT: s_and_b32 s1, 1, s1
; GFX10-NEXT: s_mov_b32 s3, s0
; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 1, s2 ; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 1, s2
; GFX10-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s1 ; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s1
; GFX10-NEXT: s_add_u32 s1, s0, 0x80000000 ; GFX10-NEXT: s_add_u32 s1, s0, 0x80000000
; GFX10-NEXT: s_mov_b32 s2, s0
; GFX10-NEXT: v_cndmask_b32_e32 v1, v3, v2, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v1, v3, v2, vcc_lo
; GFX10-NEXT: v_mov_b32_e32 v2, s9 ; GFX10-NEXT: v_mov_b32_e32 v2, s9
; GFX10-NEXT: v_mov_b32_e32 v3, s11 ; GFX10-NEXT: v_mov_b32_e32 v3, s11
; GFX10-NEXT: v_xor_b32_e32 v0, v1, v0 ; GFX10-NEXT: v_xor_b32_e32 v0, v1, v0
; GFX10-NEXT: v_mov_b32_e32 v1, s8 ; GFX10-NEXT: v_mov_b32_e32 v1, s8
; GFX10-NEXT: v_and_b32_e32 v0, 1, v0 ; GFX10-NEXT: v_and_b32_e32 v0, 1, v0
; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0 ; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
; GFX10-NEXT: v_mov_b32_e32 v0, s10 ; GFX10-NEXT: v_mov_b32_e32 v0, s10
; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s0, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s0, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s3, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s0, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, s2, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, s0, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, s1, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, s1, vcc_lo
; GFX10-NEXT: v_readfirstlane_b32 s0, v1 ; GFX10-NEXT: v_readfirstlane_b32 s0, v1
; GFX10-NEXT: v_readfirstlane_b32 s1, v2 ; GFX10-NEXT: v_readfirstlane_b32 s1, v2
; GFX10-NEXT: v_readfirstlane_b32 s2, v0 ; GFX10-NEXT: v_readfirstlane_b32 s2, v0
; GFX10-NEXT: v_readfirstlane_b32 s3, v3 ; GFX10-NEXT: v_readfirstlane_b32 s3, v3
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
; ;
; GFX11-LABEL: s_ssubsat_i128: ; GFX11-LABEL: s_ssubsat_i128:
Show All 12 Lines
; GFX11-NEXT: s_and_b32 s0, 1, s12 ; GFX11-NEXT: s_and_b32 s0, 1, s12
; GFX11-NEXT: s_cmp_eq_u64 s[6:7], 0 ; GFX11-NEXT: s_cmp_eq_u64 s[6:7], 0
; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 1, s2 ; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 1, s2
; GFX11-NEXT: v_cmp_gt_i64_e64 s2, s[6:7], 0 ; GFX11-NEXT: v_cmp_gt_i64_e64 s2, s[6:7], 0
; GFX11-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0 ; GFX11-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0
; GFX11-NEXT: s_cselect_b32 s1, 1, 0 ; GFX11-NEXT: s_cselect_b32 s1, 1, 0
; GFX11-NEXT: s_ashr_i32 s0, s11, 31 ; GFX11-NEXT: s_ashr_i32 s0, s11, 31
; GFX11-NEXT: s_and_b32 s1, 1, s1 ; GFX11-NEXT: s_and_b32 s1, 1, s1
; GFX11-NEXT: s_mov_b32 s3, s0
; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 1, s2 ; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 1, s2
; GFX11-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo ; GFX11-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
; GFX11-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s1 ; GFX11-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s1
; GFX11-NEXT: s_add_u32 s1, s0, 0x80000000 ; GFX11-NEXT: s_add_u32 s1, s0, 0x80000000
; GFX11-NEXT: s_mov_b32 s2, s0
; GFX11-NEXT: v_dual_cndmask_b32 v1, v3, v2 :: v_dual_mov_b32 v2, s9 ; GFX11-NEXT: v_dual_cndmask_b32 v1, v3, v2 :: v_dual_mov_b32 v2, s9
; GFX11-NEXT: v_mov_b32_e32 v3, s11 ; GFX11-NEXT: v_mov_b32_e32 v3, s11
; GFX11-NEXT: v_xor_b32_e32 v0, v1, v0 ; GFX11-NEXT: v_xor_b32_e32 v0, v1, v0
; GFX11-NEXT: v_dual_mov_b32 v1, s8 :: v_dual_and_b32 v0, 1, v0 ; GFX11-NEXT: v_dual_mov_b32 v1, s8 :: v_dual_and_b32 v0, 1, v0
; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0 ; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
; GFX11-NEXT: v_mov_b32_e32 v0, s10 ; GFX11-NEXT: v_mov_b32_e32 v0, s10
; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s0, vcc_lo ; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s0, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, s3, vcc_lo ; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, s0, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, s2, vcc_lo ; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, s0, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, s1, vcc_lo ; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, s1, vcc_lo
; GFX11-NEXT: v_readfirstlane_b32 s0, v1 ; GFX11-NEXT: v_readfirstlane_b32 s0, v1
; GFX11-NEXT: v_readfirstlane_b32 s1, v2 ; GFX11-NEXT: v_readfirstlane_b32 s1, v2
; GFX11-NEXT: v_readfirstlane_b32 s2, v0 ; GFX11-NEXT: v_readfirstlane_b32 s2, v0
; GFX11-NEXT: v_readfirstlane_b32 s3, v3 ; GFX11-NEXT: v_readfirstlane_b32 s3, v3
; GFX11-NEXT: ; return to shader part epilog ; GFX11-NEXT: ; return to shader part epilog
%result = call i128 @llvm.ssub.sat.i128(i128 %lhs, i128 %rhs) %result = call i128 @llvm.ssub.sat.i128(i128 %lhs, i128 %rhs)
ret i128 %result ret i128 %result
▲ Show 20 Lines • Show All 337 Lines • ▼ Show 20 Lines
; GFX6-LABEL: v_ssubsat_v2i128: ; GFX6-LABEL: v_ssubsat_v2i128:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_sub_i32_e32 v16, vcc, v0, v8 ; GFX6-NEXT: v_sub_i32_e32 v16, vcc, v0, v8
; GFX6-NEXT: v_subb_u32_e32 v17, vcc, v1, v9, vcc ; GFX6-NEXT: v_subb_u32_e32 v17, vcc, v1, v9, vcc
; GFX6-NEXT: v_subb_u32_e32 v18, vcc, v2, v10, vcc ; GFX6-NEXT: v_subb_u32_e32 v18, vcc, v2, v10, vcc
; GFX6-NEXT: v_subb_u32_e32 v19, vcc, v3, v11, vcc ; GFX6-NEXT: v_subb_u32_e32 v19, vcc, v3, v11, vcc
; GFX6-NEXT: v_cmp_lt_u64_e32 vcc, v[16:17], v[0:1] ; GFX6-NEXT: v_cmp_lt_u64_e32 vcc, v[16:17], v[0:1]
; GFX6-NEXT: v_bfrev_b32_e32 v20, 1
; GFX6-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc ; GFX6-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, v[18:19], v[2:3] ; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, v[18:19], v[2:3]
; GFX6-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc ; GFX6-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, v[18:19], v[2:3] ; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, v[18:19], v[2:3]
; GFX6-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX6-NEXT: v_cmp_lt_u64_e32 vcc, 0, v[8:9] ; GFX6-NEXT: v_cmp_lt_u64_e32 vcc, 0, v[8:9]
; GFX6-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc ; GFX6-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, 0, v[10:11] ; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, 0, v[10:11]
; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc ; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[10:11] ; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[10:11]
; GFX6-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
; GFX6-NEXT: v_xor_b32_e32 v0, v1, v0 ; GFX6-NEXT: v_xor_b32_e32 v0, v1, v0
; GFX6-NEXT: v_ashrrev_i32_e32 v2, 31, v19 ; GFX6-NEXT: v_ashrrev_i32_e32 v2, 31, v19
; GFX6-NEXT: v_add_i32_e32 v3, vcc, v2, v20 ; GFX6-NEXT: v_bfrev_b32_e32 v1, 1
; GFX6-NEXT: v_add_i32_e32 v3, vcc, v2, v1
; GFX6-NEXT: v_and_b32_e32 v0, 1, v0 ; GFX6-NEXT: v_and_b32_e32 v0, 1, v0
; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 ; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; GFX6-NEXT: v_cndmask_b32_e32 v0, v16, v2, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v0, v16, v2, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v1, v17, v2, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v1, v17, v2, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v2, v18, v2, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v2, v18, v2, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v3, v19, v3, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v3, v19, v3, vcc
; GFX6-NEXT: v_sub_i32_e32 v8, vcc, v4, v12 ; GFX6-NEXT: v_sub_i32_e32 v8, vcc, v4, v12
; GFX6-NEXT: v_subb_u32_e32 v9, vcc, v5, v13, vcc ; GFX6-NEXT: v_subb_u32_e32 v9, vcc, v5, v13, vcc
; GFX6-NEXT: v_subb_u32_e32 v10, vcc, v6, v14, vcc ; GFX6-NEXT: v_subb_u32_e32 v10, vcc, v6, v14, vcc
; GFX6-NEXT: v_subb_u32_e32 v11, vcc, v7, v15, vcc ; GFX6-NEXT: v_subb_u32_e32 v11, vcc, v7, v15, vcc
; GFX6-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[4:5] ; GFX6-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[4:5]
; GFX6-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc ; GFX6-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, v[10:11], v[6:7] ; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, v[10:11], v[6:7]
; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc ; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, v[10:11], v[6:7] ; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, v[10:11], v[6:7]
; GFX6-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc
; GFX6-NEXT: v_cmp_lt_u64_e32 vcc, 0, v[12:13] ; GFX6-NEXT: v_cmp_lt_u64_e32 vcc, 0, v[12:13]
; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc ; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, 0, v[14:15] ; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, 0, v[14:15]
; GFX6-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc ; GFX6-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[14:15] ; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[14:15]
; GFX6-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc
; GFX6-NEXT: v_xor_b32_e32 v4, v5, v4 ; GFX6-NEXT: v_xor_b32_e32 v4, v5, v4
; GFX6-NEXT: v_ashrrev_i32_e32 v6, 31, v11 ; GFX6-NEXT: v_ashrrev_i32_e32 v6, 31, v11
; GFX6-NEXT: v_add_i32_e32 v7, vcc, v6, v20 ; GFX6-NEXT: v_add_i32_e32 v7, vcc, 0x80000000, v6
; GFX6-NEXT: v_and_b32_e32 v4, 1, v4 ; GFX6-NEXT: v_and_b32_e32 v4, 1, v4
; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4 ; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4
; GFX6-NEXT: v_cndmask_b32_e32 v4, v8, v6, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v4, v8, v6, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v5, v9, v6, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v5, v9, v6, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v6, v10, v6, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v6, v10, v6, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v7, v11, v7, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v7, v11, v7, vcc
; GFX6-NEXT: s_setpc_b64 s[30:31] ; GFX6-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX8-LABEL: v_ssubsat_v2i128: ; GFX8-LABEL: v_ssubsat_v2i128:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_sub_u32_e32 v16, vcc, v0, v8 ; GFX8-NEXT: v_sub_u32_e32 v16, vcc, v0, v8
; GFX8-NEXT: v_subb_u32_e32 v17, vcc, v1, v9, vcc ; GFX8-NEXT: v_subb_u32_e32 v17, vcc, v1, v9, vcc
; GFX8-NEXT: v_subb_u32_e32 v18, vcc, v2, v10, vcc ; GFX8-NEXT: v_subb_u32_e32 v18, vcc, v2, v10, vcc
; GFX8-NEXT: v_subb_u32_e32 v19, vcc, v3, v11, vcc ; GFX8-NEXT: v_subb_u32_e32 v19, vcc, v3, v11, vcc
; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, v[16:17], v[0:1] ; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, v[16:17], v[0:1]
; GFX8-NEXT: v_bfrev_b32_e32 v20, 1
; GFX8-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, v[18:19], v[2:3] ; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, v[18:19], v[2:3]
; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX8-NEXT: v_cmp_eq_u64_e32 vcc, v[18:19], v[2:3] ; GFX8-NEXT: v_cmp_eq_u64_e32 vcc, v[18:19], v[2:3]
; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, 0, v[8:9] ; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, 0, v[8:9]
; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, 0, v[10:11] ; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, 0, v[10:11]
; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX8-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[10:11] ; GFX8-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[10:11]
; GFX8-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
; GFX8-NEXT: v_xor_b32_e32 v0, v1, v0 ; GFX8-NEXT: v_xor_b32_e32 v0, v1, v0
; GFX8-NEXT: v_ashrrev_i32_e32 v2, 31, v19 ; GFX8-NEXT: v_ashrrev_i32_e32 v2, 31, v19
; GFX8-NEXT: v_add_u32_e32 v3, vcc, v2, v20 ; GFX8-NEXT: v_bfrev_b32_e32 v1, 1
; GFX8-NEXT: v_add_u32_e32 v3, vcc, v2, v1
; GFX8-NEXT: v_and_b32_e32 v0, 1, v0 ; GFX8-NEXT: v_and_b32_e32 v0, 1, v0
; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 ; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; GFX8-NEXT: v_cndmask_b32_e32 v0, v16, v2, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v0, v16, v2, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v1, v17, v2, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v1, v17, v2, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v2, v18, v2, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v2, v18, v2, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v3, v19, v3, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v3, v19, v3, vcc
; GFX8-NEXT: v_sub_u32_e32 v8, vcc, v4, v12 ; GFX8-NEXT: v_sub_u32_e32 v8, vcc, v4, v12
; GFX8-NEXT: v_subb_u32_e32 v9, vcc, v5, v13, vcc ; GFX8-NEXT: v_subb_u32_e32 v9, vcc, v5, v13, vcc
; GFX8-NEXT: v_subb_u32_e32 v10, vcc, v6, v14, vcc ; GFX8-NEXT: v_subb_u32_e32 v10, vcc, v6, v14, vcc
; GFX8-NEXT: v_subb_u32_e32 v11, vcc, v7, v15, vcc ; GFX8-NEXT: v_subb_u32_e32 v11, vcc, v7, v15, vcc
; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[4:5] ; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[4:5]
; GFX8-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, v[10:11], v[6:7] ; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, v[10:11], v[6:7]
; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; GFX8-NEXT: v_cmp_eq_u64_e32 vcc, v[10:11], v[6:7] ; GFX8-NEXT: v_cmp_eq_u64_e32 vcc, v[10:11], v[6:7]
; GFX8-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc
; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, 0, v[12:13] ; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, 0, v[12:13]
; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, 0, v[14:15] ; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, 0, v[14:15]
; GFX8-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; GFX8-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[14:15] ; GFX8-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[14:15]
; GFX8-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc
; GFX8-NEXT: v_xor_b32_e32 v4, v5, v4 ; GFX8-NEXT: v_xor_b32_e32 v4, v5, v4
; GFX8-NEXT: v_ashrrev_i32_e32 v6, 31, v11 ; GFX8-NEXT: v_ashrrev_i32_e32 v6, 31, v11
; GFX8-NEXT: v_add_u32_e32 v7, vcc, v6, v20 ; GFX8-NEXT: v_add_u32_e32 v7, vcc, 0x80000000, v6
; GFX8-NEXT: v_and_b32_e32 v4, 1, v4 ; GFX8-NEXT: v_and_b32_e32 v4, 1, v4
; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4 ; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4
; GFX8-NEXT: v_cndmask_b32_e32 v4, v8, v6, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v4, v8, v6, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v5, v9, v6, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v5, v9, v6, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v6, v10, v6, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v6, v10, v6, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v7, v11, v7, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v7, v11, v7, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31] ; GFX8-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX9-LABEL: v_ssubsat_v2i128: ; GFX9-LABEL: v_ssubsat_v2i128:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_sub_co_u32_e32 v16, vcc, v0, v8 ; GFX9-NEXT: v_sub_co_u32_e32 v16, vcc, v0, v8
; GFX9-NEXT: v_subb_co_u32_e32 v17, vcc, v1, v9, vcc ; GFX9-NEXT: v_subb_co_u32_e32 v17, vcc, v1, v9, vcc
; GFX9-NEXT: v_subb_co_u32_e32 v18, vcc, v2, v10, vcc ; GFX9-NEXT: v_subb_co_u32_e32 v18, vcc, v2, v10, vcc
; GFX9-NEXT: v_subb_co_u32_e32 v19, vcc, v3, v11, vcc ; GFX9-NEXT: v_subb_co_u32_e32 v19, vcc, v3, v11, vcc
; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, v[16:17], v[0:1] ; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, v[16:17], v[0:1]
; GFX9-NEXT: v_bfrev_b32_e32 v20, 1
; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, v[18:19], v[2:3] ; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, v[18:19], v[2:3]
; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, v[18:19], v[2:3] ; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, v[18:19], v[2:3]
; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, 0, v[8:9] ; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, 0, v[8:9]
; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, 0, v[10:11] ; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, 0, v[10:11]
; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[10:11] ; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[10:11]
; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
; GFX9-NEXT: v_xor_b32_e32 v0, v1, v0 ; GFX9-NEXT: v_xor_b32_e32 v0, v1, v0
; GFX9-NEXT: v_ashrrev_i32_e32 v2, 31, v19 ; GFX9-NEXT: v_ashrrev_i32_e32 v2, 31, v19
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v2, v20 ; GFX9-NEXT: v_bfrev_b32_e32 v1, 1
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v2, v1
; GFX9-NEXT: v_and_b32_e32 v0, 1, v0 ; GFX9-NEXT: v_and_b32_e32 v0, 1, v0
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; GFX9-NEXT: v_cndmask_b32_e32 v0, v16, v2, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v0, v16, v2, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v1, v17, v2, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v1, v17, v2, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v2, v18, v2, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v2, v18, v2, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v3, v19, v3, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v3, v19, v3, vcc
; GFX9-NEXT: v_sub_co_u32_e32 v8, vcc, v4, v12 ; GFX9-NEXT: v_sub_co_u32_e32 v8, vcc, v4, v12
; GFX9-NEXT: v_subb_co_u32_e32 v9, vcc, v5, v13, vcc ; GFX9-NEXT: v_subb_co_u32_e32 v9, vcc, v5, v13, vcc
; GFX9-NEXT: v_subb_co_u32_e32 v10, vcc, v6, v14, vcc ; GFX9-NEXT: v_subb_co_u32_e32 v10, vcc, v6, v14, vcc
; GFX9-NEXT: v_subb_co_u32_e32 v11, vcc, v7, v15, vcc ; GFX9-NEXT: v_subb_co_u32_e32 v11, vcc, v7, v15, vcc
; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[4:5] ; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[4:5]
; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, v[10:11], v[6:7] ; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, v[10:11], v[6:7]
; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, v[10:11], v[6:7] ; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, v[10:11], v[6:7]
; GFX9-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc
; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, 0, v[12:13] ; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, 0, v[12:13]
; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, 0, v[14:15] ; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, 0, v[14:15]
; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[14:15] ; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[14:15]
; GFX9-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc
; GFX9-NEXT: v_xor_b32_e32 v4, v5, v4 ; GFX9-NEXT: v_xor_b32_e32 v4, v5, v4
; GFX9-NEXT: v_ashrrev_i32_e32 v6, 31, v11 ; GFX9-NEXT: v_ashrrev_i32_e32 v6, 31, v11
; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, v6, v20 ; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, 0x80000000, v6
; GFX9-NEXT: v_and_b32_e32 v4, 1, v4 ; GFX9-NEXT: v_and_b32_e32 v4, 1, v4
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4
; GFX9-NEXT: v_cndmask_b32_e32 v4, v8, v6, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v4, v8, v6, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v5, v9, v6, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v5, v9, v6, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v6, v10, v6, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v6, v10, v6, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v7, v11, v7, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v7, v11, v7, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
▲ Show 20 Lines • Show All 134 Lines • ▼ Show 20 Lines
; GFX6-NEXT: v_cmp_eq_u64_e64 vcc, s[10:11], 0 ; GFX6-NEXT: v_cmp_eq_u64_e64 vcc, s[10:11], 0
; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1] ; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1]
; GFX6-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
; GFX6-NEXT: v_xor_b32_e32 v0, v1, v0 ; GFX6-NEXT: v_xor_b32_e32 v0, v1, v0
; GFX6-NEXT: s_ashr_i32 s0, s19, 31 ; GFX6-NEXT: s_ashr_i32 s0, s19, 31
; GFX6-NEXT: v_and_b32_e32 v0, 1, v0 ; GFX6-NEXT: v_and_b32_e32 v0, 1, v0
; GFX6-NEXT: s_add_u32 s1, s0, 0x80000000 ; GFX6-NEXT: s_add_u32 s1, s0, 0x80000000
; GFX6-NEXT: v_mov_b32_e32 v1, s0 ; GFX6-NEXT: v_mov_b32_e32 v1, s0
; GFX6-NEXT: v_mov_b32_e32 v2, s0 ; GFX6-NEXT: v_mov_b32_e32 v2, s16
; GFX6-NEXT: v_mov_b32_e32 v3, s16 ; GFX6-NEXT: v_mov_b32_e32 v3, s17
; GFX6-NEXT: v_mov_b32_e32 v4, s17
; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 ; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; GFX6-NEXT: v_cndmask_b32_e32 v4, v2, v1, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v5, v3, v1, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v5, v3, v1, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v4, v4, v2, vcc ; GFX6-NEXT: v_mov_b32_e32 v0, s1
; GFX6-NEXT: v_mov_b32_e32 v0, s0
; GFX6-NEXT: v_mov_b32_e32 v1, s1
; GFX6-NEXT: v_mov_b32_e32 v2, s18 ; GFX6-NEXT: v_mov_b32_e32 v2, s18
; GFX6-NEXT: v_mov_b32_e32 v3, s19 ; GFX6-NEXT: v_mov_b32_e32 v3, s19
; GFX6-NEXT: v_cndmask_b32_e32 v6, v2, v0, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v6, v2, v1, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v7, v3, v1, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v7, v3, v0, vcc
; GFX6-NEXT: s_sub_u32 s0, s4, s12 ; GFX6-NEXT: s_sub_u32 s0, s4, s12
; GFX6-NEXT: v_mov_b32_e32 v2, s4 ; GFX6-NEXT: v_mov_b32_e32 v2, s4
; GFX6-NEXT: s_subb_u32 s1, s5, s13 ; GFX6-NEXT: s_subb_u32 s1, s5, s13
; GFX6-NEXT: v_mov_b32_e32 v3, s5 ; GFX6-NEXT: v_mov_b32_e32 v3, s5
; GFX6-NEXT: s_subb_u32 s2, s6, s14 ; GFX6-NEXT: s_subb_u32 s2, s6, s14
; GFX6-NEXT: v_mov_b32_e32 v0, s6 ; GFX6-NEXT: v_mov_b32_e32 v0, s6
; GFX6-NEXT: v_cmp_lt_u64_e32 vcc, s[0:1], v[2:3] ; GFX6-NEXT: v_cmp_lt_u64_e32 vcc, s[0:1], v[2:3]
; GFX6-NEXT: s_subb_u32 s3, s7, s15 ; GFX6-NEXT: s_subb_u32 s3, s7, s15
Show All 9 Lines
; GFX6-NEXT: v_cmp_eq_u64_e64 vcc, s[14:15], 0 ; GFX6-NEXT: v_cmp_eq_u64_e64 vcc, s[14:15], 0
; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[4:5] ; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[4:5]
; GFX6-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
; GFX6-NEXT: v_xor_b32_e32 v0, v1, v0 ; GFX6-NEXT: v_xor_b32_e32 v0, v1, v0
; GFX6-NEXT: s_ashr_i32 s4, s3, 31 ; GFX6-NEXT: s_ashr_i32 s4, s3, 31
; GFX6-NEXT: v_and_b32_e32 v0, 1, v0 ; GFX6-NEXT: v_and_b32_e32 v0, 1, v0
; GFX6-NEXT: s_add_u32 s5, s4, 0x80000000 ; GFX6-NEXT: s_add_u32 s5, s4, 0x80000000
; GFX6-NEXT: v_mov_b32_e32 v1, s4 ; GFX6-NEXT: v_mov_b32_e32 v1, s4
; GFX6-NEXT: v_mov_b32_e32 v2, s4 ; GFX6-NEXT: v_mov_b32_e32 v2, s0
; GFX6-NEXT: v_mov_b32_e32 v3, s0 ; GFX6-NEXT: v_mov_b32_e32 v3, s1
; GFX6-NEXT: v_mov_b32_e32 v8, s1
; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 ; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; GFX6-NEXT: v_cndmask_b32_e32 v0, v3, v1, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v1, v8, v2, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v2, v3, v1, vcc
; GFX6-NEXT: v_mov_b32_e32 v3, s5 ; GFX6-NEXT: v_mov_b32_e32 v3, s5
; GFX6-NEXT: v_mov_b32_e32 v8, s2 ; GFX6-NEXT: v_mov_b32_e32 v8, s2
; GFX6-NEXT: v_mov_b32_e32 v9, s3 ; GFX6-NEXT: v_mov_b32_e32 v9, s3
; GFX6-NEXT: v_cndmask_b32_e32 v2, v8, v2, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v3, v9, v3, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v3, v9, v3, vcc
; GFX6-NEXT: v_readfirstlane_b32 s0, v5 ; GFX6-NEXT: v_readfirstlane_b32 s0, v4
; GFX6-NEXT: v_readfirstlane_b32 s1, v4 ; GFX6-NEXT: v_readfirstlane_b32 s1, v5
; GFX6-NEXT: v_readfirstlane_b32 s2, v6 ; GFX6-NEXT: v_readfirstlane_b32 s2, v6
; GFX6-NEXT: v_readfirstlane_b32 s3, v7 ; GFX6-NEXT: v_readfirstlane_b32 s3, v7
; GFX6-NEXT: v_readfirstlane_b32 s4, v0 ; GFX6-NEXT: v_readfirstlane_b32 s4, v0
; GFX6-NEXT: v_readfirstlane_b32 s5, v1 ; GFX6-NEXT: v_readfirstlane_b32 s5, v2
; GFX6-NEXT: v_readfirstlane_b32 s6, v2 ; GFX6-NEXT: v_readfirstlane_b32 s6, v1
; GFX6-NEXT: v_readfirstlane_b32 s7, v3 ; GFX6-NEXT: v_readfirstlane_b32 s7, v3
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX8-LABEL: s_ssubsat_v2i128: ; GFX8-LABEL: s_ssubsat_v2i128:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_sub_u32 s16, s0, s8 ; GFX8-NEXT: s_sub_u32 s16, s0, s8
; GFX8-NEXT: s_subb_u32 s17, s1, s9 ; GFX8-NEXT: s_subb_u32 s17, s1, s9
; GFX8-NEXT: v_mov_b32_e32 v3, s1 ; GFX8-NEXT: v_mov_b32_e32 v3, s1
Show All 20 Lines
; GFX8-NEXT: s_and_b32 s0, 1, s2 ; GFX8-NEXT: s_and_b32 s0, 1, s2
; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 ; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
; GFX8-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
; GFX8-NEXT: v_xor_b32_e32 v0, v1, v0 ; GFX8-NEXT: v_xor_b32_e32 v0, v1, v0
; GFX8-NEXT: s_ashr_i32 s0, s19, 31 ; GFX8-NEXT: s_ashr_i32 s0, s19, 31
; GFX8-NEXT: v_and_b32_e32 v0, 1, v0 ; GFX8-NEXT: v_and_b32_e32 v0, 1, v0
; GFX8-NEXT: s_add_u32 s1, s0, 0x80000000 ; GFX8-NEXT: s_add_u32 s1, s0, 0x80000000
; GFX8-NEXT: v_mov_b32_e32 v1, s0 ; GFX8-NEXT: v_mov_b32_e32 v1, s0
; GFX8-NEXT: v_mov_b32_e32 v2, s0 ; GFX8-NEXT: v_mov_b32_e32 v2, s16
; GFX8-NEXT: v_mov_b32_e32 v3, s16 ; GFX8-NEXT: v_mov_b32_e32 v3, s17
; GFX8-NEXT: v_mov_b32_e32 v4, s17
; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 ; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; GFX8-NEXT: v_cndmask_b32_e32 v4, v2, v1, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v5, v3, v1, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v5, v3, v1, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v2, vcc ; GFX8-NEXT: v_mov_b32_e32 v0, s1
; GFX8-NEXT: v_mov_b32_e32 v0, s0
; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: v_mov_b32_e32 v2, s18 ; GFX8-NEXT: v_mov_b32_e32 v2, s18
; GFX8-NEXT: v_mov_b32_e32 v3, s19 ; GFX8-NEXT: v_mov_b32_e32 v3, s19
; GFX8-NEXT: s_sub_u32 s0, s4, s12 ; GFX8-NEXT: s_sub_u32 s0, s4, s12
; GFX8-NEXT: v_cndmask_b32_e32 v6, v2, v0, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v6, v2, v1, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v7, v3, v1, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v7, v3, v0, vcc
; GFX8-NEXT: s_subb_u32 s1, s5, s13 ; GFX8-NEXT: s_subb_u32 s1, s5, s13
; GFX8-NEXT: v_mov_b32_e32 v2, s4 ; GFX8-NEXT: v_mov_b32_e32 v2, s4
; GFX8-NEXT: s_subb_u32 s2, s6, s14 ; GFX8-NEXT: s_subb_u32 s2, s6, s14
; GFX8-NEXT: v_mov_b32_e32 v3, s5 ; GFX8-NEXT: v_mov_b32_e32 v3, s5
; GFX8-NEXT: s_subb_u32 s3, s7, s15 ; GFX8-NEXT: s_subb_u32 s3, s7, s15
; GFX8-NEXT: v_mov_b32_e32 v0, s6 ; GFX8-NEXT: v_mov_b32_e32 v0, s6
; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, s[0:1], v[2:3] ; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, s[0:1], v[2:3]
; GFX8-NEXT: v_mov_b32_e32 v1, s7 ; GFX8-NEXT: v_mov_b32_e32 v1, s7
Show All 14 Lines
; GFX8-NEXT: s_and_b32 s4, 1, s6 ; GFX8-NEXT: s_and_b32 s4, 1, s6
; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 ; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4
; GFX8-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
; GFX8-NEXT: v_xor_b32_e32 v0, v1, v0 ; GFX8-NEXT: v_xor_b32_e32 v0, v1, v0
; GFX8-NEXT: s_ashr_i32 s4, s3, 31 ; GFX8-NEXT: s_ashr_i32 s4, s3, 31
; GFX8-NEXT: v_and_b32_e32 v0, 1, v0 ; GFX8-NEXT: v_and_b32_e32 v0, 1, v0
; GFX8-NEXT: s_add_u32 s5, s4, 0x80000000 ; GFX8-NEXT: s_add_u32 s5, s4, 0x80000000
; GFX8-NEXT: v_mov_b32_e32 v1, s4 ; GFX8-NEXT: v_mov_b32_e32 v1, s4
; GFX8-NEXT: v_mov_b32_e32 v2, s4 ; GFX8-NEXT: v_mov_b32_e32 v2, s0
; GFX8-NEXT: v_mov_b32_e32 v3, s0 ; GFX8-NEXT: v_mov_b32_e32 v3, s1
; GFX8-NEXT: v_mov_b32_e32 v8, s1
; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 ; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v1, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v1, v8, v2, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v2, v3, v1, vcc
; GFX8-NEXT: v_mov_b32_e32 v2, s4
; GFX8-NEXT: v_mov_b32_e32 v3, s5 ; GFX8-NEXT: v_mov_b32_e32 v3, s5
; GFX8-NEXT: v_mov_b32_e32 v8, s2 ; GFX8-NEXT: v_mov_b32_e32 v8, s2
; GFX8-NEXT: v_mov_b32_e32 v9, s3 ; GFX8-NEXT: v_mov_b32_e32 v9, s3
; GFX8-NEXT: v_cndmask_b32_e32 v2, v8, v2, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v3, v9, v3, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v3, v9, v3, vcc
; GFX8-NEXT: v_readfirstlane_b32 s0, v5 ; GFX8-NEXT: v_readfirstlane_b32 s0, v4
; GFX8-NEXT: v_readfirstlane_b32 s1, v4 ; GFX8-NEXT: v_readfirstlane_b32 s1, v5
; GFX8-NEXT: v_readfirstlane_b32 s2, v6 ; GFX8-NEXT: v_readfirstlane_b32 s2, v6
; GFX8-NEXT: v_readfirstlane_b32 s3, v7 ; GFX8-NEXT: v_readfirstlane_b32 s3, v7
; GFX8-NEXT: v_readfirstlane_b32 s4, v0 ; GFX8-NEXT: v_readfirstlane_b32 s4, v0
; GFX8-NEXT: v_readfirstlane_b32 s5, v1 ; GFX8-NEXT: v_readfirstlane_b32 s5, v2
; GFX8-NEXT: v_readfirstlane_b32 s6, v2 ; GFX8-NEXT: v_readfirstlane_b32 s6, v1
; GFX8-NEXT: v_readfirstlane_b32 s7, v3 ; GFX8-NEXT: v_readfirstlane_b32 s7, v3
; GFX8-NEXT: ; return to shader part epilog ; GFX8-NEXT: ; return to shader part epilog
; ;
; GFX9-LABEL: s_ssubsat_v2i128: ; GFX9-LABEL: s_ssubsat_v2i128:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_sub_u32 s16, s0, s8 ; GFX9-NEXT: s_sub_u32 s16, s0, s8
; GFX9-NEXT: s_subb_u32 s17, s1, s9 ; GFX9-NEXT: s_subb_u32 s17, s1, s9
; GFX9-NEXT: v_mov_b32_e32 v3, s1 ; GFX9-NEXT: v_mov_b32_e32 v3, s1
Show All 20 Lines
; GFX9-NEXT: s_and_b32 s0, 1, s2 ; GFX9-NEXT: s_and_b32 s0, 1, s2
; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 ; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
; GFX9-NEXT: v_xor_b32_e32 v0, v1, v0 ; GFX9-NEXT: v_xor_b32_e32 v0, v1, v0
; GFX9-NEXT: s_ashr_i32 s0, s19, 31 ; GFX9-NEXT: s_ashr_i32 s0, s19, 31
; GFX9-NEXT: v_and_b32_e32 v0, 1, v0 ; GFX9-NEXT: v_and_b32_e32 v0, 1, v0
; GFX9-NEXT: s_add_u32 s1, s0, 0x80000000 ; GFX9-NEXT: s_add_u32 s1, s0, 0x80000000
; GFX9-NEXT: v_mov_b32_e32 v1, s0 ; GFX9-NEXT: v_mov_b32_e32 v1, s0
; GFX9-NEXT: v_mov_b32_e32 v2, s0 ; GFX9-NEXT: v_mov_b32_e32 v2, s16
; GFX9-NEXT: v_mov_b32_e32 v3, s16 ; GFX9-NEXT: v_mov_b32_e32 v3, s17
; GFX9-NEXT: v_mov_b32_e32 v4, s17
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; GFX9-NEXT: v_cndmask_b32_e32 v4, v2, v1, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v5, v3, v1, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v5, v3, v1, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v2, vcc ; GFX9-NEXT: v_mov_b32_e32 v0, s1
; GFX9-NEXT: v_mov_b32_e32 v0, s0
; GFX9-NEXT: v_mov_b32_e32 v1, s1
; GFX9-NEXT: v_mov_b32_e32 v2, s18 ; GFX9-NEXT: v_mov_b32_e32 v2, s18
; GFX9-NEXT: v_mov_b32_e32 v3, s19 ; GFX9-NEXT: v_mov_b32_e32 v3, s19
; GFX9-NEXT: s_sub_u32 s0, s4, s12 ; GFX9-NEXT: s_sub_u32 s0, s4, s12
; GFX9-NEXT: v_cndmask_b32_e32 v6, v2, v0, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v6, v2, v1, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v7, v3, v1, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v7, v3, v0, vcc
; GFX9-NEXT: s_subb_u32 s1, s5, s13 ; GFX9-NEXT: s_subb_u32 s1, s5, s13
; GFX9-NEXT: v_mov_b32_e32 v2, s4 ; GFX9-NEXT: v_mov_b32_e32 v2, s4
; GFX9-NEXT: s_subb_u32 s2, s6, s14 ; GFX9-NEXT: s_subb_u32 s2, s6, s14
; GFX9-NEXT: v_mov_b32_e32 v3, s5 ; GFX9-NEXT: v_mov_b32_e32 v3, s5
; GFX9-NEXT: s_subb_u32 s3, s7, s15 ; GFX9-NEXT: s_subb_u32 s3, s7, s15
; GFX9-NEXT: v_mov_b32_e32 v0, s6 ; GFX9-NEXT: v_mov_b32_e32 v0, s6
; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, s[0:1], v[2:3] ; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, s[0:1], v[2:3]
; GFX9-NEXT: v_mov_b32_e32 v1, s7 ; GFX9-NEXT: v_mov_b32_e32 v1, s7
Show All 14 Lines
; GFX9-NEXT: s_and_b32 s4, 1, s6 ; GFX9-NEXT: s_and_b32 s4, 1, s6
; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 ; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4
; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
; GFX9-NEXT: v_xor_b32_e32 v0, v1, v0 ; GFX9-NEXT: v_xor_b32_e32 v0, v1, v0
; GFX9-NEXT: s_ashr_i32 s4, s3, 31 ; GFX9-NEXT: s_ashr_i32 s4, s3, 31
; GFX9-NEXT: v_and_b32_e32 v0, 1, v0 ; GFX9-NEXT: v_and_b32_e32 v0, 1, v0
; GFX9-NEXT: s_add_u32 s5, s4, 0x80000000 ; GFX9-NEXT: s_add_u32 s5, s4, 0x80000000
; GFX9-NEXT: v_mov_b32_e32 v1, s4 ; GFX9-NEXT: v_mov_b32_e32 v1, s4
; GFX9-NEXT: v_mov_b32_e32 v2, s4 ; GFX9-NEXT: v_mov_b32_e32 v2, s0
; GFX9-NEXT: v_mov_b32_e32 v3, s0 ; GFX9-NEXT: v_mov_b32_e32 v3, s1
; GFX9-NEXT: v_mov_b32_e32 v8, s1
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; GFX9-NEXT: v_cndmask_b32_e32 v0, v3, v1, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v1, v8, v2, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v1, vcc
; GFX9-NEXT: v_mov_b32_e32 v2, s4
; GFX9-NEXT: v_mov_b32_e32 v3, s5 ; GFX9-NEXT: v_mov_b32_e32 v3, s5
; GFX9-NEXT: v_mov_b32_e32 v8, s2 ; GFX9-NEXT: v_mov_b32_e32 v8, s2
; GFX9-NEXT: v_mov_b32_e32 v9, s3 ; GFX9-NEXT: v_mov_b32_e32 v9, s3
; GFX9-NEXT: v_cndmask_b32_e32 v2, v8, v2, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v3, v9, v3, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v3, v9, v3, vcc
; GFX9-NEXT: v_readfirstlane_b32 s0, v5 ; GFX9-NEXT: v_readfirstlane_b32 s0, v4
; GFX9-NEXT: v_readfirstlane_b32 s1, v4 ; GFX9-NEXT: v_readfirstlane_b32 s1, v5
; GFX9-NEXT: v_readfirstlane_b32 s2, v6 ; GFX9-NEXT: v_readfirstlane_b32 s2, v6
; GFX9-NEXT: v_readfirstlane_b32 s3, v7 ; GFX9-NEXT: v_readfirstlane_b32 s3, v7
; GFX9-NEXT: v_readfirstlane_b32 s4, v0 ; GFX9-NEXT: v_readfirstlane_b32 s4, v0
; GFX9-NEXT: v_readfirstlane_b32 s5, v1 ; GFX9-NEXT: v_readfirstlane_b32 s5, v2
; GFX9-NEXT: v_readfirstlane_b32 s6, v2 ; GFX9-NEXT: v_readfirstlane_b32 s6, v1
; GFX9-NEXT: v_readfirstlane_b32 s7, v3 ; GFX9-NEXT: v_readfirstlane_b32 s7, v3
; GFX9-NEXT: ; return to shader part epilog ; GFX9-NEXT: ; return to shader part epilog
; ;
; GFX10-LABEL: s_ssubsat_v2i128: ; GFX10-LABEL: s_ssubsat_v2i128:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_sub_u32 s16, s0, s8 ; GFX10-NEXT: s_sub_u32 s16, s0, s8
; GFX10-NEXT: s_subb_u32 s17, s1, s9 ; GFX10-NEXT: s_subb_u32 s17, s1, s9
; GFX10-NEXT: s_subb_u32 s18, s2, s10 ; GFX10-NEXT: s_subb_u32 s18, s2, s10
; GFX10-NEXT: v_cmp_lt_u64_e64 s0, s[16:17], s[0:1] ; GFX10-NEXT: v_cmp_lt_u64_e64 s0, s[16:17], s[0:1]
; GFX10-NEXT: s_subb_u32 s19, s3, s11 ; GFX10-NEXT: s_subb_u32 s19, s3, s11
; GFX10-NEXT: s_cmp_eq_u64 s[18:19], s[2:3] ; GFX10-NEXT: s_cmp_eq_u64 s[18:19], s[2:3]
; GFX10-NEXT: s_cselect_b32 s20, 1, 0 ; GFX10-NEXT: s_cselect_b32 s20, 1, 0
; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
; GFX10-NEXT: v_cmp_lt_i64_e64 s0, s[18:19], s[2:3] ; GFX10-NEXT: v_cmp_lt_i64_e64 s0, s[18:19], s[2:3]
; GFX10-NEXT: v_cmp_gt_u64_e64 s2, s[8:9], 0 ; GFX10-NEXT: v_cmp_gt_u64_e64 s2, s[8:9], 0
; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s0
; GFX10-NEXT: s_and_b32 s0, 1, s20 ; GFX10-NEXT: s_and_b32 s0, 1, s20
; GFX10-NEXT: s_cmp_eq_u64 s[10:11], 0 ; GFX10-NEXT: s_cmp_eq_u64 s[10:11], 0
; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0
; GFX10-NEXT: s_cselect_b32 s1, 1, 0
; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, s2 ; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, s2
; GFX10-NEXT: v_cmp_gt_i64_e64 s2, s[10:11], 0 ; GFX10-NEXT: v_cmp_gt_i64_e64 s2, s[10:11], 0
; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0
; GFX10-NEXT: s_cselect_b32 s1, 1, 0
; GFX10-NEXT: s_ashr_i32 s8, s19, 31
; GFX10-NEXT: s_and_b32 s1, 1, s1 ; GFX10-NEXT: s_and_b32 s1, 1, s1
; GFX10-NEXT: s_ashr_i32 s0, s19, 31 ; GFX10-NEXT: s_add_u32 s9, s8, 0x80000000
; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 1, s2
; GFX10-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s1 ; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s1
; GFX10-NEXT: s_add_u32 s1, s0, 0x80000000 ; GFX10-NEXT: s_sub_u32 s0, s4, s12
; GFX10-NEXT: s_sub_u32 s8, s4, s12 ; GFX10-NEXT: s_subb_u32 s1, s5, s13
; GFX10-NEXT: s_subb_u32 s9, s5, s13 ; GFX10-NEXT: s_subb_u32 s2, s6, s14
; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 1, s2 ; GFX10-NEXT: v_cmp_lt_u64_e64 s4, s[0:1], s[4:5]
; GFX10-NEXT: v_cmp_lt_u64_e64 s4, s[8:9], s[4:5]
; GFX10-NEXT: s_subb_u32 s10, s6, s14
; GFX10-NEXT: s_subb_u32 s11, s7, s15
; GFX10-NEXT: s_mov_b32 s3, s0
; GFX10-NEXT: v_cndmask_b32_e32 v1, v3, v2, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v1, v3, v2, vcc_lo
; GFX10-NEXT: s_cmp_eq_u64 s[10:11], s[6:7] ; GFX10-NEXT: s_subb_u32 s3, s7, s15
; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 1, s4 ; GFX10-NEXT: v_mov_b32_e32 v5, s0
; GFX10-NEXT: v_cmp_lt_i64_e64 s4, s[10:11], s[6:7] ; GFX10-NEXT: s_cmp_eq_u64 s[2:3], s[6:7]
; GFX10-NEXT: v_cmp_gt_u64_e64 s6, s[12:13], 0 ; GFX10-NEXT: v_mov_b32_e32 v6, s1
; GFX10-NEXT: v_xor_b32_e32 v0, v1, v0 ; GFX10-NEXT: v_xor_b32_e32 v0, v1, v0
; GFX10-NEXT: v_mov_b32_e32 v1, s16 ; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s4
; GFX10-NEXT: s_cselect_b32 s16, 1, 0 ; GFX10-NEXT: v_cmp_lt_i64_e64 s4, s[2:3], s[6:7]
; GFX10-NEXT: v_mov_b32_e32 v2, s17 ; GFX10-NEXT: v_cmp_gt_u64_e64 s6, s[12:13], 0
; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 1, s4 ; GFX10-NEXT: s_cselect_b32 s10, 1, 0
; GFX10-NEXT: s_and_b32 s4, 1, s16 ; GFX10-NEXT: v_and_b32_e32 v0, 1, v0
; GFX10-NEXT: v_mov_b32_e32 v7, s3
; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, s4
; GFX10-NEXT: s_and_b32 s4, 1, s10
; GFX10-NEXT: s_cmp_eq_u64 s[14:15], 0 ; GFX10-NEXT: s_cmp_eq_u64 s[14:15], 0
; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s6 ; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 1, s6
; GFX10-NEXT: v_cmp_gt_i64_e64 s6, s[14:15], 0 ; GFX10-NEXT: v_cmp_gt_i64_e64 s6, s[14:15], 0
; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s4 ; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s4
; GFX10-NEXT: s_cselect_b32 s5, 1, 0 ; GFX10-NEXT: s_cselect_b32 s5, 1, 0
; GFX10-NEXT: v_and_b32_e32 v0, 1, v0 ; GFX10-NEXT: s_ashr_i32 s4, s3, 31
; GFX10-NEXT: s_and_b32 s5, 1, s5 ; GFX10-NEXT: s_and_b32 s5, 1, s5
; GFX10-NEXT: s_mov_b32 s2, s0 ; GFX10-NEXT: s_add_u32 s0, s4, 0x80000000
; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 1, s6 ; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 1, s6
; GFX10-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc_lo
; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s5 ; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s5
; GFX10-NEXT: v_mov_b32_e32 v7, s11 ; GFX10-NEXT: v_cndmask_b32_e32 v2, v4, v3, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v4, v6, v5, vcc_lo ; GFX10-NEXT: v_mov_b32_e32 v3, s16
; GFX10-NEXT: v_mov_b32_e32 v4, s17
; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0 ; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
; GFX10-NEXT: v_mov_b32_e32 v0, s18 ; GFX10-NEXT: v_mov_b32_e32 v0, s18
; GFX10-NEXT: v_mov_b32_e32 v5, s19 ; GFX10-NEXT: v_xor_b32_e32 v1, v2, v1
; GFX10-NEXT: v_mov_b32_e32 v6, s9 ; GFX10-NEXT: v_mov_b32_e32 v2, s19
; GFX10-NEXT: v_xor_b32_e32 v3, v4, v3 ; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, s8, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s0, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, s8, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s3, vcc_lo ; GFX10-NEXT: v_and_b32_e32 v1, 1, v1
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, s2, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, s8, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v4, v5, s1, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s9, vcc_lo
; GFX10-NEXT: v_and_b32_e32 v3, 1, v3 ; GFX10-NEXT: v_readfirstlane_b32 s1, v4
; GFX10-NEXT: v_mov_b32_e32 v5, s8 ; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v1
; GFX10-NEXT: s_ashr_i32 s0, s11, 31 ; GFX10-NEXT: v_mov_b32_e32 v1, s2
; GFX10-NEXT: s_add_u32 s1, s0, 0x80000000
; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v3
; GFX10-NEXT: v_mov_b32_e32 v3, s10
; GFX10-NEXT: s_mov_b32 s3, s0
; GFX10-NEXT: s_mov_b32 s2, s0
; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, s0, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, s3, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, s2, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v7, v7, s1, vcc_lo
; GFX10-NEXT: v_readfirstlane_b32 s0, v1
; GFX10-NEXT: v_readfirstlane_b32 s1, v2
; GFX10-NEXT: v_readfirstlane_b32 s2, v0 ; GFX10-NEXT: v_readfirstlane_b32 s2, v0
; GFX10-NEXT: v_readfirstlane_b32 s3, v4 ; GFX10-NEXT: v_readfirstlane_b32 s3, v2
; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, s4, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, s4, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s4, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v7, v7, s0, vcc_lo
; GFX10-NEXT: v_readfirstlane_b32 s0, v3
; GFX10-NEXT: v_readfirstlane_b32 s4, v5 ; GFX10-NEXT: v_readfirstlane_b32 s4, v5
; GFX10-NEXT: v_readfirstlane_b32 s5, v6 ; GFX10-NEXT: v_readfirstlane_b32 s5, v6
; GFX10-NEXT: v_readfirstlane_b32 s6, v3 ; GFX10-NEXT: v_readfirstlane_b32 s6, v1
; GFX10-NEXT: v_readfirstlane_b32 s7, v7 ; GFX10-NEXT: v_readfirstlane_b32 s7, v7
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
; ;
; GFX11-LABEL: s_ssubsat_v2i128: ; GFX11-LABEL: s_ssubsat_v2i128:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_sub_u32 s16, s0, s8 ; GFX11-NEXT: s_sub_u32 s16, s0, s8
; GFX11-NEXT: s_subb_u32 s17, s1, s9 ; GFX11-NEXT: s_subb_u32 s17, s1, s9
; GFX11-NEXT: s_subb_u32 s18, s2, s10 ; GFX11-NEXT: s_subb_u32 s18, s2, s10
; GFX11-NEXT: v_cmp_lt_u64_e64 s0, s[16:17], s[0:1] ; GFX11-NEXT: v_cmp_lt_u64_e64 s0, s[16:17], s[0:1]
; GFX11-NEXT: s_subb_u32 s19, s3, s11 ; GFX11-NEXT: s_subb_u32 s19, s3, s11
; GFX11-NEXT: s_cmp_eq_u64 s[18:19], s[2:3] ; GFX11-NEXT: s_cmp_eq_u64 s[18:19], s[2:3]
; GFX11-NEXT: s_cselect_b32 s20, 1, 0 ; GFX11-NEXT: s_cselect_b32 s20, 1, 0
; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 ; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
; GFX11-NEXT: v_cmp_lt_i64_e64 s0, s[18:19], s[2:3] ; GFX11-NEXT: v_cmp_lt_i64_e64 s0, s[18:19], s[2:3]
; GFX11-NEXT: v_cmp_gt_u64_e64 s2, s[8:9], 0 ; GFX11-NEXT: v_cmp_gt_u64_e64 s2, s[8:9], 0
; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 1, s0 ; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 1, s0
; GFX11-NEXT: s_and_b32 s0, 1, s20 ; GFX11-NEXT: s_and_b32 s0, 1, s20
; GFX11-NEXT: s_cmp_eq_u64 s[10:11], 0 ; GFX11-NEXT: s_cmp_eq_u64 s[10:11], 0
; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 1, s2 ; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 1, s2
; GFX11-NEXT: v_cmp_gt_i64_e64 s2, s[10:11], 0 ; GFX11-NEXT: v_cmp_gt_i64_e64 s2, s[10:11], 0
; GFX11-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0 ; GFX11-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0
; GFX11-NEXT: s_cselect_b32 s1, 1, 0 ; GFX11-NEXT: s_cselect_b32 s1, 1, 0
; GFX11-NEXT: s_ashr_i32 s0, s19, 31 ; GFX11-NEXT: s_ashr_i32 s8, s19, 31
; GFX11-NEXT: s_and_b32 s1, 1, s1 ; GFX11-NEXT: s_and_b32 s1, 1, s1
; GFX11-NEXT: s_mov_b32 s3, s0 ; GFX11-NEXT: s_add_u32 s9, s8, 0x80000000
; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 1, s2 ; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 1, s2
; GFX11-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo ; GFX11-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
; GFX11-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s1 ; GFX11-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s1
; GFX11-NEXT: s_add_u32 s1, s0, 0x80000000 ; GFX11-NEXT: s_sub_u32 s0, s4, s12
; GFX11-NEXT: s_sub_u32 s8, s4, s12 ; GFX11-NEXT: s_subb_u32 s1, s5, s13
; GFX11-NEXT: s_subb_u32 s9, s5, s13 ; GFX11-NEXT: s_subb_u32 s2, s6, s14
; GFX11-NEXT: s_subb_u32 s10, s6, s14 ; GFX11-NEXT: v_cmp_lt_u64_e64 s4, s[0:1], s[4:5]
; GFX11-NEXT: v_cndmask_b32_e32 v1, v3, v2, vcc_lo ; GFX11-NEXT: v_cndmask_b32_e32 v1, v3, v2, vcc_lo
; GFX11-NEXT: v_cmp_lt_u64_e64 s4, s[8:9], s[4:5] ; GFX11-NEXT: s_subb_u32 s3, s7, s15
; GFX11-NEXT: s_subb_u32 s11, s7, s15 ; GFX11-NEXT: v_dual_mov_b32 v6, s1 :: v_dual_mov_b32 v7, s3
; GFX11-NEXT: s_mov_b32 s2, s0 ; GFX11-NEXT: s_cmp_eq_u64 s[2:3], s[6:7]
; GFX11-NEXT: s_cmp_eq_u64 s[10:11], s[6:7]
; GFX11-NEXT: v_xor_b32_e32 v0, v1, v0 ; GFX11-NEXT: v_xor_b32_e32 v0, v1, v0
; GFX11-NEXT: v_mov_b32_e32 v1, s16 ; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 1, s4
; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 1, s4 ; GFX11-NEXT: v_cmp_lt_i64_e64 s4, s[2:3], s[6:7]
; GFX11-NEXT: v_cmp_lt_i64_e64 s4, s[10:11], s[6:7]
; GFX11-NEXT: v_cmp_gt_u64_e64 s6, s[12:13], 0 ; GFX11-NEXT: v_cmp_gt_u64_e64 s6, s[12:13], 0
; GFX11-NEXT: v_and_b32_e32 v0, 1, v0 ; GFX11-NEXT: s_cselect_b32 s10, 1, 0
; GFX11-NEXT: s_cselect_b32 s16, 1, 0 ; GFX11-NEXT: v_mov_b32_e32 v5, s0
; GFX11-NEXT: v_mov_b32_e32 v7, s11 ; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 1, s4
; GFX11-NEXT: v_cndmask_b32_e64 v4, 0, 1, s4 ; GFX11-NEXT: s_and_b32 s4, 1, s10
; GFX11-NEXT: s_and_b32 s4, 1, s16
; GFX11-NEXT: s_cmp_eq_u64 s[14:15], 0 ; GFX11-NEXT: s_cmp_eq_u64 s[14:15], 0
; GFX11-NEXT: v_cndmask_b32_e64 v5, 0, 1, s6 ; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 1, s6
; GFX11-NEXT: v_cmp_gt_i64_e64 s6, s[14:15], 0 ; GFX11-NEXT: v_cmp_gt_i64_e64 s6, s[14:15], 0
; GFX11-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s4 ; GFX11-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s4
; GFX11-NEXT: s_cselect_b32 s5, 1, 0 ; GFX11-NEXT: s_cselect_b32 s5, 1, 0
; GFX11-NEXT: v_mov_b32_e32 v2, s17 ; GFX11-NEXT: v_and_b32_e32 v0, 1, v0
; GFX11-NEXT: s_and_b32 s5, 1, s5 ; GFX11-NEXT: s_and_b32 s5, 1, s5
; GFX11-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc_lo ; GFX11-NEXT: s_ashr_i32 s4, s3, 31
; GFX11-NEXT: v_cndmask_b32_e64 v6, 0, 1, s6 ; GFX11-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v4, 0, 1, s6
; GFX11-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s5 ; GFX11-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s5
; GFX11-NEXT: v_dual_cndmask_b32 v4, v6, v5 :: v_dual_mov_b32 v5, s19 ; GFX11-NEXT: s_add_u32 s0, s4, 0x80000000
; GFX11-NEXT: v_dual_cndmask_b32 v2, v4, v3 :: v_dual_mov_b32 v3, s16
; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0 ; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
; GFX11-NEXT: v_mov_b32_e32 v6, s9
; GFX11-NEXT: v_xor_b32_e32 v3, v4, v3
; GFX11-NEXT: v_mov_b32_e32 v0, s18 ; GFX11-NEXT: v_mov_b32_e32 v0, s18
; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s0, vcc_lo ; GFX11-NEXT: v_xor_b32_e32 v1, v2, v1
; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, s3, vcc_lo ; GFX11-NEXT: v_mov_b32_e32 v4, s17
; GFX11-NEXT: v_cndmask_b32_e64 v4, v5, s1, vcc_lo ; GFX11-NEXT: v_mov_b32_e32 v2, s19
; GFX11-NEXT: v_and_b32_e32 v3, 1, v3 ; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, s8, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, s2, vcc_lo ; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, s8, vcc_lo
; GFX11-NEXT: v_mov_b32_e32 v5, s8 ; GFX11-NEXT: v_and_b32_e32 v1, 1, v1
; GFX11-NEXT: s_ashr_i32 s0, s11, 31 ; GFX11-NEXT: v_cndmask_b32_e64 v4, v4, s8, vcc_lo
; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v3 ; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, s9, vcc_lo
; GFX11-NEXT: v_mov_b32_e32 v3, s10 ; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v1
; GFX11-NEXT: s_add_u32 s1, s0, 0x80000000 ; GFX11-NEXT: v_mov_b32_e32 v1, s2
; GFX11-NEXT: s_mov_b32 s3, s0 ; GFX11-NEXT: v_readfirstlane_b32 s1, v4
; GFX11-NEXT: s_mov_b32 s2, s0
; GFX11-NEXT: v_cndmask_b32_e64 v5, v5, s0, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v6, v6, s3, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, s2, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v7, v7, s1, vcc_lo
; GFX11-NEXT: v_readfirstlane_b32 s0, v1
; GFX11-NEXT: v_readfirstlane_b32 s1, v2
; GFX11-NEXT: v_readfirstlane_b32 s2, v0 ; GFX11-NEXT: v_readfirstlane_b32 s2, v0
; GFX11-NEXT: v_readfirstlane_b32 s3, v4 ; GFX11-NEXT: v_readfirstlane_b32 s3, v2
; GFX11-NEXT: v_cndmask_b32_e64 v5, v5, s4, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v6, v6, s4, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s4, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v7, v7, s0, vcc_lo
; GFX11-NEXT: v_readfirstlane_b32 s0, v3
; GFX11-NEXT: v_readfirstlane_b32 s4, v5 ; GFX11-NEXT: v_readfirstlane_b32 s4, v5
; GFX11-NEXT: v_readfirstlane_b32 s5, v6 ; GFX11-NEXT: v_readfirstlane_b32 s5, v6
; GFX11-NEXT: v_readfirstlane_b32 s6, v3 ; GFX11-NEXT: v_readfirstlane_b32 s6, v1
; GFX11-NEXT: v_readfirstlane_b32 s7, v7 ; GFX11-NEXT: v_readfirstlane_b32 s7, v7
; GFX11-NEXT: ; return to shader part epilog ; GFX11-NEXT: ; return to shader part epilog
%result = call <2 x i128> @llvm.ssub.sat.v2i128(<2 x i128> %lhs, <2 x i128> %rhs) %result = call <2 x i128> @llvm.ssub.sat.v2i128(<2 x i128> %lhs, <2 x i128> %rhs)
ret <2 x i128> %result ret <2 x i128> %result
} }
declare i7 @llvm.ssub.sat.i7(i7, i7) #0 declare i7 @llvm.ssub.sat.i7(i7, i7) #0
declare i8 @llvm.ssub.sat.i8(i8, i8) #0 declare i8 @llvm.ssub.sat.i8(i8, i8) #0
Show All 29 Lines