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Differential D142192 Diff 491241 llvm/test/CodeGen/AMDGPU/GlobalISel/sext_inreg.ll

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llvm/test/CodeGen/AMDGPU/GlobalISel/sext_inreg.ll

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; GFX8-NEXT: s_setpc_b64 s[30:31] ; GFX8-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX9-LABEL: v_sext_inreg_i65_22: ; GFX9-LABEL: v_sext_inreg_i65_22:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_lshlrev_b64 v[2:3], 22, v[2:3] ; GFX9-NEXT: v_lshlrev_b64 v[2:3], 22, v[2:3]
; GFX9-NEXT: v_lshrrev_b32_e32 v3, 10, v1 ; GFX9-NEXT: v_lshrrev_b32_e32 v3, 10, v1
; GFX9-NEXT: v_or_b32_e32 v2, v2, v3 ; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
; GFX9-NEXT: v_bfe_i32 v2, v2, 0, 1
; GFX9-NEXT: v_lshrrev_b64 v[0:1], 0, v[0:1] ; GFX9-NEXT: v_lshrrev_b64 v[0:1], 0, v[0:1]
; GFX9-NEXT: v_bfe_i32 v2, v2, 0, 1
; GFX9-NEXT: v_ashrrev_i32_e32 v3, 31, v2 ; GFX9-NEXT: v_ashrrev_i32_e32 v3, 31, v2
; GFX9-NEXT: v_bfe_u32 v1, v1, 0, 10 ; GFX9-NEXT: v_bfe_u32 v1, v1, 0, 10
; GFX9-NEXT: v_lshlrev_b32_e32 v4, 10, v2 ; GFX9-NEXT: v_lshl_or_b32 v1, v2, 10, v1
; GFX9-NEXT: v_ashrrev_i64 v[2:3], 22, v[2:3] ; GFX9-NEXT: v_ashrrev_i64 v[2:3], 22, v[2:3]
; GFX9-NEXT: v_or_b32_e32 v1, v1, v4
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10PLUS-LABEL: v_sext_inreg_i65_22: ; GFX10PLUS-LABEL: v_sext_inreg_i65_22:
; GFX10PLUS: ; %bb.0: ; GFX10PLUS: ; %bb.0:
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10PLUS-NEXT: v_lshlrev_b64 v[2:3], 22, v[2:3] ; GFX10PLUS-NEXT: v_lshlrev_b64 v[2:3], 22, v[2:3]
; GFX10PLUS-NEXT: v_lshrrev_b32_e32 v3, 10, v1 ; GFX10PLUS-NEXT: v_lshrrev_b32_e32 v3, 10, v1
; GFX10PLUS-NEXT: v_lshrrev_b64 v[0:1], 0, v[0:1] ; GFX10PLUS-NEXT: v_lshrrev_b64 v[0:1], 0, v[0:1]
; GFX10PLUS-NEXT: v_or_b32_e32 v2, v2, v3 ; GFX10PLUS-NEXT: v_or_b32_e32 v2, v2, v3
; GFX10PLUS-NEXT: v_bfe_u32 v1, v1, 0, 10 ; GFX10PLUS-NEXT: v_bfe_u32 v1, v1, 0, 10
; GFX10PLUS-NEXT: v_bfe_i32 v2, v2, 0, 1 ; GFX10PLUS-NEXT: v_bfe_i32 v2, v2, 0, 1
; GFX10PLUS-NEXT: v_ashrrev_i32_e32 v3, 31, v2 ; GFX10PLUS-NEXT: v_ashrrev_i32_e32 v3, 31, v2
; GFX10PLUS-NEXT: v_lshlrev_b32_e32 v4, 10, v2 ; GFX10PLUS-NEXT: v_lshl_or_b32 v1, v2, 10, v1
; GFX10PLUS-NEXT: v_ashrrev_i64 v[2:3], 22, v[2:3] ; GFX10PLUS-NEXT: v_ashrrev_i64 v[2:3], 22, v[2:3]
; GFX10PLUS-NEXT: v_or_b32_e32 v1, v1, v4
; GFX10PLUS-NEXT: s_setpc_b64 s[30:31] ; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
%shl = shl i65 %value, 22 %shl = shl i65 %value, 22
%ashr = ashr i65 %shl, 22 %ashr = ashr i65 %shl, 22
ret i65 %ashr ret i65 %ashr
} }
define i65 @v_sext_inreg_i65_33(i65 %value) { define i65 @v_sext_inreg_i65_33(i65 %value) {
; GFX6-LABEL: v_sext_inreg_i65_33: ; GFX6-LABEL: v_sext_inreg_i65_33:
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