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Differential D142192 Diff 491241 llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll

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llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll

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; GFX8-NEXT: v_or_b32_e32 v1, v2, v1 ; GFX8-NEXT: v_or_b32_e32 v1, v2, v1
; GFX8-NEXT: s_setpc_b64 s[30:31] ; GFX8-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX9-LABEL: v_fshr_i64_5: ; GFX9-LABEL: v_fshr_i64_5:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v4, v0 ; GFX9-NEXT: v_mov_b32_e32 v4, v0
; GFX9-NEXT: v_lshrrev_b64 v[0:1], 5, v[2:3] ; GFX9-NEXT: v_lshrrev_b64 v[0:1], 5, v[2:3]
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 27, v4 ; GFX9-NEXT: v_lshl_or_b32 v1, v4, 27, v1
; GFX9-NEXT: v_or_b32_e32 v1, v2, v1
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: v_fshr_i64_5: ; GFX10-LABEL: v_fshr_i64_5:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_mov_b32_e32 v4, v0 ; GFX10-NEXT: v_mov_b32_e32 v4, v0
; GFX10-NEXT: v_lshrrev_b64 v[0:1], 5, v[2:3] ; GFX10-NEXT: v_lshrrev_b64 v[0:1], 5, v[2:3]
; GFX10-NEXT: v_lshlrev_b32_e32 v2, 27, v4 ; GFX10-NEXT: v_lshl_or_b32 v1, v4, 27, v1
; GFX10-NEXT: v_or_b32_e32 v1, v2, v1
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: v_fshr_i64_5: ; GFX11-LABEL: v_fshr_i64_5:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: v_mov_b32_e32 v4, v0 ; GFX11-NEXT: v_mov_b32_e32 v4, v0
; GFX11-NEXT: v_lshrrev_b64 v[0:1], 5, v[2:3] ; GFX11-NEXT: v_lshrrev_b64 v[0:1], 5, v[2:3]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_lshlrev_b32_e32 v2, 27, v4 ; GFX11-NEXT: v_lshl_or_b32 v1, v4, 27, v1
; GFX11-NEXT: v_or_b32_e32 v1, v2, v1
; GFX11-NEXT: s_setpc_b64 s[30:31] ; GFX11-NEXT: s_setpc_b64 s[30:31]
%result = call i64 @llvm.fshr.i64(i64 %lhs, i64 %rhs, i64 5) %result = call i64 @llvm.fshr.i64(i64 %lhs, i64 %rhs, i64 5)
ret i64 %result ret i64 %result
} }
define i64 @v_fshr_i64_32(i64 %lhs, i64 %rhs) { define i64 @v_fshr_i64_32(i64 %lhs, i64 %rhs) {
; GFX6-LABEL: v_fshr_i64_32: ; GFX6-LABEL: v_fshr_i64_32:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
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; GFX8-NEXT: v_lshrrev_b64 v[0:1], 1, v[6:7] ; GFX8-NEXT: v_lshrrev_b64 v[0:1], 1, v[6:7]
; GFX8-NEXT: v_or_b32_e32 v3, v5, v3 ; GFX8-NEXT: v_or_b32_e32 v3, v5, v3
; GFX8-NEXT: v_or_b32_e32 v1, v4, v1 ; GFX8-NEXT: v_or_b32_e32 v1, v4, v1
; GFX8-NEXT: s_setpc_b64 s[30:31] ; GFX8-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX9-LABEL: v_fshr_i128_65: ; GFX9-LABEL: v_fshr_i128_65:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_lshlrev_b32_e32 v4, 31, v0 ; GFX9-NEXT: v_mov_b32_e32 v8, v2
; GFX9-NEXT: v_lshlrev_b32_e32 v5, 31, v2
; GFX9-NEXT: v_lshrrev_b64 v[2:3], 1, v[0:1] ; GFX9-NEXT: v_lshrrev_b64 v[2:3], 1, v[0:1]
; GFX9-NEXT: v_lshrrev_b64 v[0:1], 1, v[6:7] ; GFX9-NEXT: v_lshrrev_b64 v[4:5], 1, v[6:7]
; GFX9-NEXT: v_or_b32_e32 v3, v5, v3 ; GFX9-NEXT: v_lshl_or_b32 v3, v8, 31, v3
; GFX9-NEXT: v_or_b32_e32 v1, v4, v1 ; GFX9-NEXT: v_lshl_or_b32 v1, v0, 31, v5
; GFX9-NEXT: v_mov_b32_e32 v0, v4
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: v_fshr_i128_65: ; GFX10-LABEL: v_fshr_i128_65:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_mov_b32_e32 v8, v2 ; GFX10-NEXT: v_mov_b32_e32 v8, v2
; GFX10-NEXT: v_lshrrev_b64 v[4:5], 1, v[6:7] ; GFX10-NEXT: v_lshrrev_b64 v[4:5], 1, v[6:7]
; GFX10-NEXT: v_lshrrev_b64 v[2:3], 1, v[0:1] ; GFX10-NEXT: v_lshrrev_b64 v[2:3], 1, v[0:1]
; GFX10-NEXT: v_lshlrev_b32_e32 v9, 31, v0 ; GFX10-NEXT: v_lshl_or_b32 v1, v0, 31, v5
; GFX10-NEXT: v_lshlrev_b32_e32 v0, 31, v8 ; GFX10-NEXT: v_lshl_or_b32 v3, v8, 31, v3
; GFX10-NEXT: v_or_b32_e32 v1, v9, v5
; GFX10-NEXT: v_or_b32_e32 v3, v0, v3
; GFX10-NEXT: v_mov_b32_e32 v0, v4 ; GFX10-NEXT: v_mov_b32_e32 v0, v4
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: v_fshr_i128_65: ; GFX11-LABEL: v_fshr_i128_65:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: v_dual_mov_b32 v8, v2 :: v_dual_lshlrev_b32 v9, 31, v0 ; GFX11-NEXT: v_mov_b32_e32 v8, v2
; GFX11-NEXT: v_lshrrev_b64 v[4:5], 1, v[6:7] ; GFX11-NEXT: v_lshrrev_b64 v[4:5], 1, v[6:7]
; GFX11-NEXT: v_lshrrev_b64 v[2:3], 1, v[0:1] ; GFX11-NEXT: v_lshrrev_b64 v[2:3], 1, v[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_lshlrev_b32_e32 v0, 31, v8 ; GFX11-NEXT: v_lshl_or_b32 v1, v0, 31, v5
; GFX11-NEXT: v_or_b32_e32 v1, v9, v5 ; GFX11-NEXT: v_lshl_or_b32 v3, v8, 31, v3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-NEXT: v_or_b32_e32 v3, v0, v3
; GFX11-NEXT: v_mov_b32_e32 v0, v4 ; GFX11-NEXT: v_mov_b32_e32 v0, v4
; GFX11-NEXT: s_setpc_b64 s[30:31] ; GFX11-NEXT: s_setpc_b64 s[30:31]
%result = call i128 @llvm.fshr.i128(i128 %lhs, i128 %rhs, i128 65) %result = call i128 @llvm.fshr.i128(i128 %lhs, i128 %rhs, i128 65)
ret i128 %result ret i128 %result
} }
define amdgpu_ps <2 x i128> @s_fshr_v2i128(<2 x i128> inreg %lhs, <2 x i128> inreg %rhs, <2 x i128> inreg %amt) { define amdgpu_ps <2 x i128> @s_fshr_v2i128(<2 x i128> inreg %lhs, <2 x i128> inreg %rhs, <2 x i128> inreg %amt) {
; GFX6-LABEL: s_fshr_v2i128: ; GFX6-LABEL: s_fshr_v2i128:
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