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Differential D141918 Diff 489761 clang/test/OpenMP/teams_distribute_parallel_for_simd_num_threads_codegen.cpp
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clang/test/OpenMP/teams_distribute_parallel_for_simd_num_threads_codegen.cpp
| Show First 20 Lines • Show All 113 Lines • ▼ Show 20 Lines | |||||
| // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 | // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 | ||||
| // CHECK1-NEXT: store ptr null, ptr [[TMP7]], align 8 | // CHECK1-NEXT: store ptr null, ptr [[TMP7]], align 8 | ||||
| // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 | // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 | ||||
| // CHECK1-NEXT: store i64 100, ptr [[TMP8]], align 8 | // CHECK1-NEXT: store i64 100, ptr [[TMP8]], align 8 | ||||
| // CHECK1-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3:[0-9]+]], i64 -1, i32 0, i32 2, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l50.region_id, ptr [[KERNEL_ARGS]]) | // CHECK1-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3:[0-9]+]], i64 -1, i32 0, i32 2, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l50.region_id, ptr [[KERNEL_ARGS]]) | ||||
| // CHECK1-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 | // CHECK1-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 | ||||
| // CHECK1-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] | // CHECK1-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] | ||||
| // CHECK1: omp_offload.failed: | // CHECK1: omp_offload.failed: | ||||
| // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l50() #[[ATTR6:[0-9]+]] | // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l50() #[[ATTR5:[0-9]+]] | ||||
| // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] | // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] | ||||
| // CHECK1: lpad: | // CHECK1: lpad: | ||||
| // CHECK1-NEXT: [[TMP11:%.*]] = landingpad { ptr, i32 } | // CHECK1-NEXT: [[TMP11:%.*]] = landingpad { ptr, i32 } | ||||
| // CHECK1-NEXT: cleanup | // CHECK1-NEXT: cleanup | ||||
| // CHECK1-NEXT: [[TMP12:%.*]] = extractvalue { ptr, i32 } [[TMP11]], 0 | // CHECK1-NEXT: [[TMP12:%.*]] = extractvalue { ptr, i32 } [[TMP11]], 0 | ||||
| // CHECK1-NEXT: store ptr [[TMP12]], ptr [[EXN_SLOT]], align 8 | // CHECK1-NEXT: store ptr [[TMP12]], ptr [[EXN_SLOT]], align 8 | ||||
| // CHECK1-NEXT: [[TMP13:%.*]] = extractvalue { ptr, i32 } [[TMP11]], 1 | // CHECK1-NEXT: [[TMP13:%.*]] = extractvalue { ptr, i32 } [[TMP11]], 1 | ||||
| // CHECK1-NEXT: store i32 [[TMP13]], ptr [[EHSELECTOR_SLOT]], align 4 | // CHECK1-NEXT: store i32 [[TMP13]], ptr [[EHSELECTOR_SLOT]], align 4 | ||||
| // CHECK1-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR6]] | // CHECK1-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR5]] | ||||
| // CHECK1-NEXT: br label [[EH_RESUME:%.*]] | // CHECK1-NEXT: br label [[EH_RESUME:%.*]] | ||||
| // CHECK1: omp_offload.cont: | // CHECK1: omp_offload.cont: | ||||
| // CHECK1-NEXT: [[TMP14:%.*]] = load i8, ptr [[A]], align 1 | // CHECK1-NEXT: [[TMP14:%.*]] = load i8, ptr [[A]], align 1 | ||||
| // CHECK1-NEXT: store i8 [[TMP14]], ptr [[A_CASTED]], align 1 | // CHECK1-NEXT: store i8 [[TMP14]], ptr [[A_CASTED]], align 1 | ||||
| // CHECK1-NEXT: [[TMP15:%.*]] = load i64, ptr [[A_CASTED]], align 8 | // CHECK1-NEXT: [[TMP15:%.*]] = load i64, ptr [[A_CASTED]], align 8 | ||||
| // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 | // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 | ||||
| // CHECK1-NEXT: store i64 [[TMP15]], ptr [[TMP16]], align 8 | // CHECK1-NEXT: store i64 [[TMP15]], ptr [[TMP16]], align 8 | ||||
| // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 | // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 | ||||
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| // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 7 | // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 7 | ||||
| // CHECK1-NEXT: store ptr null, ptr [[TMP31]], align 8 | // CHECK1-NEXT: store ptr null, ptr [[TMP31]], align 8 | ||||
| // CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 8 | // CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 8 | ||||
| // CHECK1-NEXT: store i64 100, ptr [[TMP32]], align 8 | // CHECK1-NEXT: store i64 100, ptr [[TMP32]], align 8 | ||||
| // CHECK1-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 [[TMP23]], ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55.region_id, ptr [[KERNEL_ARGS2]]) | // CHECK1-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 [[TMP23]], ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55.region_id, ptr [[KERNEL_ARGS2]]) | ||||
| // CHECK1-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0 | // CHECK1-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0 | ||||
| // CHECK1-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]] | // CHECK1-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]] | ||||
| // CHECK1: omp_offload.failed3: | // CHECK1: omp_offload.failed3: | ||||
| // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55(i64 [[TMP15]]) #[[ATTR6]] | // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55(i64 [[TMP15]]) #[[ATTR5]] | ||||
| // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT4]] | // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT4]] | ||||
| // CHECK1: omp_offload.cont4: | // CHECK1: omp_offload.cont4: | ||||
| // CHECK1-NEXT: [[TMP35:%.*]] = load i8, ptr [[A]], align 1 | // CHECK1-NEXT: [[TMP35:%.*]] = load i8, ptr [[A]], align 1 | ||||
| // CHECK1-NEXT: [[CONV:%.*]] = sext i8 [[TMP35]] to i32 | // CHECK1-NEXT: [[CONV:%.*]] = sext i8 [[TMP35]] to i32 | ||||
| // CHECK1-NEXT: [[CALL6:%.*]] = invoke noundef signext i32 @_Z5tmainIcLi5EEiv() | // CHECK1-NEXT: [[CALL6:%.*]] = invoke noundef signext i32 @_Z5tmainIcLi5EEiv() | ||||
| // CHECK1-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[LPAD]] | // CHECK1-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[LPAD]] | ||||
| // CHECK1: invoke.cont5: | // CHECK1: invoke.cont5: | ||||
| // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], [[CALL6]] | // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], [[CALL6]] | ||||
| // CHECK1-NEXT: [[CALL8:%.*]] = invoke noundef signext i32 @_Z5tmainI1SLi1EEiv() | // CHECK1-NEXT: [[CALL8:%.*]] = invoke noundef signext i32 @_Z5tmainI1SLi1EEiv() | ||||
| // CHECK1-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD]] | // CHECK1-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD]] | ||||
| // CHECK1: invoke.cont7: | // CHECK1: invoke.cont7: | ||||
| // CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 [[ADD]], [[CALL8]] | // CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 [[ADD]], [[CALL8]] | ||||
| // CHECK1-NEXT: store i32 [[ADD9]], ptr [[RETVAL]], align 4 | // CHECK1-NEXT: store i32 [[ADD9]], ptr [[RETVAL]], align 4 | ||||
| // CHECK1-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR6]] | // CHECK1-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR5]] | ||||
| // CHECK1-NEXT: [[TMP36:%.*]] = load i32, ptr [[RETVAL]], align 4 | // CHECK1-NEXT: [[TMP36:%.*]] = load i32, ptr [[RETVAL]], align 4 | ||||
| // CHECK1-NEXT: ret i32 [[TMP36]] | // CHECK1-NEXT: ret i32 [[TMP36]] | ||||
| // CHECK1: eh.resume: | // CHECK1: eh.resume: | ||||
| // CHECK1-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8 | // CHECK1-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8 | ||||
| // CHECK1-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4 | // CHECK1-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4 | ||||
| // CHECK1-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0 | // CHECK1-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0 | ||||
| // CHECK1-NEXT: [[LPAD_VAL10:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1 | // CHECK1-NEXT: [[LPAD_VAL10:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1 | ||||
| // CHECK1-NEXT: resume { ptr, i32 } [[LPAD_VAL10]] | // CHECK1-NEXT: resume { ptr, i32 } [[LPAD_VAL10]] | ||||
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| // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP13]] | // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP13]] | ||||
| // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] | // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] | ||||
| // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | ||||
| // CHECK1: omp.inner.for.body: | // CHECK1: omp.inner.for.body: | ||||
| // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]] | // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]] | ||||
| // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 | // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 | ||||
| // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | ||||
| // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP13]] | // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP13]] | ||||
| // CHECK1-NEXT: invoke void @_Z3foov() | // CHECK1-NEXT: call unwindabort void @_Z3foov(), !llvm.access.group [[ACC_GRP13]] | ||||
| // CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP13]] | |||||
| // CHECK1: invoke.cont: | |||||
| // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | ||||
| // CHECK1: omp.body.continue: | // CHECK1: omp.body.continue: | ||||
| // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | ||||
| // CHECK1: omp.inner.for.inc: | // CHECK1: omp.inner.for.inc: | ||||
| // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]] | // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]] | ||||
| // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 | // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 | ||||
| // CHECK1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]] | // CHECK1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]] | ||||
| // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] | // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] | ||||
| // CHECK1: omp.inner.for.end: | // CHECK1: omp.inner.for.end: | ||||
| // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | ||||
| // CHECK1: omp.loop.exit: | // CHECK1: omp.loop.exit: | ||||
| // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) | // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) | ||||
| // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 | // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 | ||||
| // CHECK1-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 | // CHECK1-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 | ||||
| // CHECK1-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] | // CHECK1-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] | ||||
| // CHECK1: .omp.final.then: | // CHECK1: .omp.final.then: | ||||
| // CHECK1-NEXT: store i32 100, ptr [[I]], align 4 | // CHECK1-NEXT: store i32 100, ptr [[I]], align 4 | ||||
| // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] | // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] | ||||
| // CHECK1: .omp.final.done: | // CHECK1: .omp.final.done: | ||||
| // CHECK1-NEXT: ret void | // CHECK1-NEXT: ret void | ||||
| // CHECK1: terminate.lpad: | |||||
| // CHECK1-NEXT: [[TMP13:%.*]] = landingpad { ptr, i32 } | |||||
| // CHECK1-NEXT: catch ptr null | |||||
| // CHECK1-NEXT: [[TMP14:%.*]] = extractvalue { ptr, i32 } [[TMP13]], 0 | |||||
| // CHECK1-NEXT: call void @__clang_call_terminate(ptr [[TMP14]]) #[[ATTR9:[0-9]+]], !llvm.access.group [[ACC_GRP13]] | |||||
| // CHECK1-NEXT: unreachable | |||||
| // | |||||
| // | |||||
| // CHECK1-LABEL: define {{[^@]+}}@__clang_call_terminate | |||||
| // CHECK1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR5:[0-9]+]] comdat { | |||||
| // CHECK1-NEXT: [[TMP2:%.*]] = call ptr @__cxa_begin_catch(ptr [[TMP0]]) #[[ATTR6]] | |||||
| // CHECK1-NEXT: call void @_ZSt9terminatev() #[[ATTR9]] | |||||
| // CHECK1-NEXT: unreachable | |||||
| // | // | ||||
| // | // | ||||
| // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55 | // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55 | ||||
| // CHECK1-SAME: (i64 noundef [[A:%.*]]) #[[ATTR3]] { | // CHECK1-SAME: (i64 noundef [[A:%.*]]) #[[ATTR3]] { | ||||
| // CHECK1-NEXT: entry: | // CHECK1-NEXT: entry: | ||||
| // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 | // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 | ||||
| // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 | // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 | ||||
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| // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP21]] | // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP21]] | ||||
| // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] | // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] | ||||
| // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | ||||
| // CHECK1: omp.inner.for.body: | // CHECK1: omp.inner.for.body: | ||||
| // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]] | // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]] | ||||
| // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 | // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 | ||||
| // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | ||||
| // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP21]] | // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP21]] | ||||
| // CHECK1-NEXT: invoke void @_Z3foov() | // CHECK1-NEXT: call unwindabort void @_Z3foov(), !llvm.access.group [[ACC_GRP21]] | ||||
| // CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP21]] | |||||
| // CHECK1: invoke.cont: | |||||
| // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | ||||
| // CHECK1: omp.body.continue: | // CHECK1: omp.body.continue: | ||||
| // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | ||||
| // CHECK1: omp.inner.for.inc: | // CHECK1: omp.inner.for.inc: | ||||
| // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]] | // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]] | ||||
| // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 | // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 | ||||
| // CHECK1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]] | // CHECK1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]] | ||||
| // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] | // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] | ||||
| // CHECK1: omp.inner.for.end: | // CHECK1: omp.inner.for.end: | ||||
| // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | ||||
| // CHECK1: omp.loop.exit: | // CHECK1: omp.loop.exit: | ||||
| // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) | // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) | ||||
| // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 | // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 | ||||
| // CHECK1-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 | // CHECK1-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 | ||||
| // CHECK1-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] | // CHECK1-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] | ||||
| // CHECK1: .omp.final.then: | // CHECK1: .omp.final.then: | ||||
| // CHECK1-NEXT: store i32 100, ptr [[I]], align 4 | // CHECK1-NEXT: store i32 100, ptr [[I]], align 4 | ||||
| // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] | // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] | ||||
| // CHECK1: .omp.final.done: | // CHECK1: .omp.final.done: | ||||
| // CHECK1-NEXT: ret void | // CHECK1-NEXT: ret void | ||||
| // CHECK1: terminate.lpad: | |||||
| // CHECK1-NEXT: [[TMP13:%.*]] = landingpad { ptr, i32 } | |||||
| // CHECK1-NEXT: catch ptr null | |||||
| // CHECK1-NEXT: [[TMP14:%.*]] = extractvalue { ptr, i32 } [[TMP13]], 0 | |||||
| // CHECK1-NEXT: call void @__clang_call_terminate(ptr [[TMP14]]) #[[ATTR9]], !llvm.access.group [[ACC_GRP21]] | |||||
| // CHECK1-NEXT: unreachable | |||||
| // | // | ||||
| // | // | ||||
| // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIcLi5EEiv | // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIcLi5EEiv | ||||
| // CHECK1-SAME: () #[[ATTR2]] comdat { | // CHECK1-SAME: () #[[ATTR2]] comdat { | ||||
| // CHECK1-NEXT: entry: | // CHECK1-NEXT: entry: | ||||
| // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 | // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 | ||||
| // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 | // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 | ||||
| // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 | // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 | ||||
| Show All 14 Lines | |||||
| // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 | // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 | ||||
| // CHECK1-NEXT: store ptr null, ptr [[TMP7]], align 8 | // CHECK1-NEXT: store ptr null, ptr [[TMP7]], align 8 | ||||
| // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 | // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 | ||||
| // CHECK1-NEXT: store i64 100, ptr [[TMP8]], align 8 | // CHECK1-NEXT: store i64 100, ptr [[TMP8]], align 8 | ||||
| // CHECK1-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 5, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l36.region_id, ptr [[KERNEL_ARGS]]) | // CHECK1-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 5, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l36.region_id, ptr [[KERNEL_ARGS]]) | ||||
| // CHECK1-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 | // CHECK1-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 | ||||
| // CHECK1-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] | // CHECK1-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] | ||||
| // CHECK1: omp_offload.failed: | // CHECK1: omp_offload.failed: | ||||
| // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l36() #[[ATTR6]] | // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l36() #[[ATTR5]] | ||||
| // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] | // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] | ||||
| // CHECK1: omp_offload.cont: | // CHECK1: omp_offload.cont: | ||||
| // CHECK1-NEXT: [[KERNEL_ARGS2:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 | // CHECK1-NEXT: [[KERNEL_ARGS2:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 | ||||
| // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 0 | // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 0 | ||||
| // CHECK1-NEXT: store i32 1, ptr [[TMP11]], align 4 | // CHECK1-NEXT: store i32 1, ptr [[TMP11]], align 4 | ||||
| // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 1 | // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 1 | ||||
| // CHECK1-NEXT: store i32 0, ptr [[TMP12]], align 4 | // CHECK1-NEXT: store i32 0, ptr [[TMP12]], align 4 | ||||
| // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 2 | // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 2 | ||||
| Show All 9 Lines | |||||
| // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 7 | // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 7 | ||||
| // CHECK1-NEXT: store ptr null, ptr [[TMP18]], align 8 | // CHECK1-NEXT: store ptr null, ptr [[TMP18]], align 8 | ||||
| // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 8 | // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 8 | ||||
| // CHECK1-NEXT: store i64 100, ptr [[TMP19]], align 8 | // CHECK1-NEXT: store i64 100, ptr [[TMP19]], align 8 | ||||
| // CHECK1-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 23, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l40.region_id, ptr [[KERNEL_ARGS2]]) | // CHECK1-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 23, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l40.region_id, ptr [[KERNEL_ARGS2]]) | ||||
| // CHECK1-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 | // CHECK1-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 | ||||
| // CHECK1-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]] | // CHECK1-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]] | ||||
| // CHECK1: omp_offload.failed3: | // CHECK1: omp_offload.failed3: | ||||
| // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l40() #[[ATTR6]] | // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l40() #[[ATTR5]] | ||||
| // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT4]] | // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT4]] | ||||
| // CHECK1: omp_offload.cont4: | // CHECK1: omp_offload.cont4: | ||||
| // CHECK1-NEXT: ret i32 0 | // CHECK1-NEXT: ret i32 0 | ||||
| // | // | ||||
| // | // | ||||
| // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainI1SLi1EEiv | // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainI1SLi1EEiv | ||||
| // CHECK1-SAME: () #[[ATTR2]] comdat personality ptr @__gxx_personality_v0 { | // CHECK1-SAME: () #[[ATTR6:[0-9]+]] comdat personality ptr @__gxx_personality_v0 { | ||||
| // CHECK1-NEXT: entry: | // CHECK1-NEXT: entry: | ||||
| // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 | // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 | ||||
| // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 | // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 | ||||
| // CHECK1-NEXT: [[REF_TMP:%.*]] = alloca [[STRUCT_S:%.*]], align 8 | // CHECK1-NEXT: [[REF_TMP:%.*]] = alloca [[STRUCT_S:%.*]], align 8 | ||||
| // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 | // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 | ||||
| // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 | // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 | ||||
| // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 | // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 | ||||
| // CHECK1-NEXT: store i32 1, ptr [[TMP0]], align 4 | // CHECK1-NEXT: store i32 1, ptr [[TMP0]], align 4 | ||||
| Show All 12 Lines | |||||
| // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 | // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 | ||||
| // CHECK1-NEXT: store ptr null, ptr [[TMP7]], align 8 | // CHECK1-NEXT: store ptr null, ptr [[TMP7]], align 8 | ||||
| // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 | // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 | ||||
| // CHECK1-NEXT: store i64 100, ptr [[TMP8]], align 8 | // CHECK1-NEXT: store i64 100, ptr [[TMP8]], align 8 | ||||
| // CHECK1-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l36.region_id, ptr [[KERNEL_ARGS]]) | // CHECK1-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l36.region_id, ptr [[KERNEL_ARGS]]) | ||||
| // CHECK1-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 | // CHECK1-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 | ||||
| // CHECK1-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] | // CHECK1-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] | ||||
| // CHECK1: omp_offload.failed: | // CHECK1: omp_offload.failed: | ||||
| // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l36() #[[ATTR6]] | // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l36() #[[ATTR5]] | ||||
| // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] | // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] | ||||
| // CHECK1: omp_offload.cont: | // CHECK1: omp_offload.cont: | ||||
| // CHECK1-NEXT: invoke void @_ZN1SC1El(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]], i64 noundef 23) | // CHECK1-NEXT: call unwindabort void @_ZN1SC1El(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]], i64 noundef 23) | ||||
| // CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] | |||||
| // CHECK1: invoke.cont: | |||||
| // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i8 @_ZN1ScvcEv(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) | // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i8 @_ZN1ScvcEv(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) | ||||
| // CHECK1-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]] | // CHECK1-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR5]] | ||||
| // CHECK1-NEXT: store i8 [[CALL]], ptr [[DOTCAPTURE_EXPR_]], align 1 | // CHECK1-NEXT: store i8 [[CALL]], ptr [[DOTCAPTURE_EXPR_]], align 1 | ||||
| // CHECK1-NEXT: [[TMP11:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 | // CHECK1-NEXT: [[TMP11:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 | ||||
| // CHECK1-NEXT: [[TMP12:%.*]] = zext i8 [[TMP11]] to i32 | // CHECK1-NEXT: [[TMP12:%.*]] = zext i8 [[TMP11]] to i32 | ||||
| // CHECK1-NEXT: [[KERNEL_ARGS2:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 | // CHECK1-NEXT: [[KERNEL_ARGS2:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 | ||||
| // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 0 | // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 0 | ||||
| // CHECK1-NEXT: store i32 1, ptr [[TMP13]], align 4 | // CHECK1-NEXT: store i32 1, ptr [[TMP13]], align 4 | ||||
| // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 1 | // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 1 | ||||
| // CHECK1-NEXT: store i32 0, ptr [[TMP14]], align 4 | // CHECK1-NEXT: store i32 0, ptr [[TMP14]], align 4 | ||||
| Show All 10 Lines | |||||
| // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 7 | // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 7 | ||||
| // CHECK1-NEXT: store ptr null, ptr [[TMP20]], align 8 | // CHECK1-NEXT: store ptr null, ptr [[TMP20]], align 8 | ||||
| // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 8 | // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 8 | ||||
| // CHECK1-NEXT: store i64 100, ptr [[TMP21]], align 8 | // CHECK1-NEXT: store i64 100, ptr [[TMP21]], align 8 | ||||
| // CHECK1-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 [[TMP12]], ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l40.region_id, ptr [[KERNEL_ARGS2]]) | // CHECK1-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 [[TMP12]], ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l40.region_id, ptr [[KERNEL_ARGS2]]) | ||||
| // CHECK1-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 | // CHECK1-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 | ||||
| // CHECK1-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]] | // CHECK1-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]] | ||||
| // CHECK1: omp_offload.failed3: | // CHECK1: omp_offload.failed3: | ||||
| // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l40() #[[ATTR6]] | // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l40() #[[ATTR5]] | ||||
| // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT4]] | // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT4]] | ||||
| // CHECK1: omp_offload.cont4: | // CHECK1: omp_offload.cont4: | ||||
| // CHECK1-NEXT: ret i32 0 | // CHECK1-NEXT: ret i32 0 | ||||
| // CHECK1: terminate.lpad: | |||||
| // CHECK1-NEXT: [[TMP24:%.*]] = landingpad { ptr, i32 } | |||||
| // CHECK1-NEXT: catch ptr null | |||||
| // CHECK1-NEXT: [[TMP25:%.*]] = extractvalue { ptr, i32 } [[TMP24]], 0 | |||||
| // CHECK1-NEXT: call void @__clang_call_terminate(ptr [[TMP25]]) #[[ATTR9]] | |||||
| // CHECK1-NEXT: unreachable | |||||
| // | // | ||||
| // | // | ||||
| // CHECK1-LABEL: define {{[^@]+}}@_ZN1SD1Ev | // CHECK1-LABEL: define {{[^@]+}}@_ZN1SD1Ev | ||||
| // CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR7:[0-9]+]] comdat align 2 { | // CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR7:[0-9]+]] comdat align 2 { | ||||
| // CHECK1-NEXT: entry: | // CHECK1-NEXT: entry: | ||||
| // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 | // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 | ||||
| // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 | // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 | ||||
| // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 | // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 | ||||
| // CHECK1-NEXT: call void @_ZN1SD2Ev(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR6]] | // CHECK1-NEXT: call void @_ZN1SD2Ev(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR5]] | ||||
| // CHECK1-NEXT: ret void | // CHECK1-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK1-LABEL: define {{[^@]+}}@_ZN1SC2El | // CHECK1-LABEL: define {{[^@]+}}@_ZN1SC2El | ||||
| // CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR7]] comdat align 2 { | // CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR7]] comdat align 2 { | ||||
| // CHECK1-NEXT: entry: | // CHECK1-NEXT: entry: | ||||
| // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 | // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 | ||||
| // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | ||||
| ▲ Show 20 Lines • Show All 140 Lines • ▼ Show 20 Lines | |||||
| // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP27]] | // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP27]] | ||||
| // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] | // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] | ||||
| // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | ||||
| // CHECK1: omp.inner.for.body: | // CHECK1: omp.inner.for.body: | ||||
| // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]] | // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]] | ||||
| // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 | // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 | ||||
| // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | ||||
| // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP27]] | // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP27]] | ||||
| // CHECK1-NEXT: invoke void @_Z3foov() | // CHECK1-NEXT: call unwindabort void @_Z3foov(), !llvm.access.group [[ACC_GRP27]] | ||||
| // CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP27]] | |||||
| // CHECK1: invoke.cont: | |||||
| // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | ||||
| // CHECK1: omp.body.continue: | // CHECK1: omp.body.continue: | ||||
| // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | ||||
| // CHECK1: omp.inner.for.inc: | // CHECK1: omp.inner.for.inc: | ||||
| // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]] | // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]] | ||||
| // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 | // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 | ||||
| // CHECK1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]] | // CHECK1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]] | ||||
| // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]] | // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]] | ||||
| // CHECK1: omp.inner.for.end: | // CHECK1: omp.inner.for.end: | ||||
| // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | ||||
| // CHECK1: omp.loop.exit: | // CHECK1: omp.loop.exit: | ||||
| // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) | // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) | ||||
| // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 | // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 | ||||
| // CHECK1-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 | // CHECK1-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 | ||||
| // CHECK1-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] | // CHECK1-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] | ||||
| // CHECK1: .omp.final.then: | // CHECK1: .omp.final.then: | ||||
| // CHECK1-NEXT: store i32 100, ptr [[I]], align 4 | // CHECK1-NEXT: store i32 100, ptr [[I]], align 4 | ||||
| // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] | // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] | ||||
| // CHECK1: .omp.final.done: | // CHECK1: .omp.final.done: | ||||
| // CHECK1-NEXT: ret void | // CHECK1-NEXT: ret void | ||||
| // CHECK1: terminate.lpad: | |||||
| // CHECK1-NEXT: [[TMP13:%.*]] = landingpad { ptr, i32 } | |||||
| // CHECK1-NEXT: catch ptr null | |||||
| // CHECK1-NEXT: [[TMP14:%.*]] = extractvalue { ptr, i32 } [[TMP13]], 0 | |||||
| // CHECK1-NEXT: call void @__clang_call_terminate(ptr [[TMP14]]) #[[ATTR9]], !llvm.access.group [[ACC_GRP27]] | |||||
| // CHECK1-NEXT: unreachable | |||||
| // | // | ||||
| // | // | ||||
| // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l40 | // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l40 | ||||
| // CHECK1-SAME: () #[[ATTR3]] { | // CHECK1-SAME: () #[[ATTR3]] { | ||||
| // CHECK1-NEXT: entry: | // CHECK1-NEXT: entry: | ||||
| // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @.omp_outlined..6) | // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @.omp_outlined..6) | ||||
| // CHECK1-NEXT: ret void | // CHECK1-NEXT: ret void | ||||
| // | // | ||||
| ▲ Show 20 Lines • Show All 116 Lines • ▼ Show 20 Lines | |||||
| // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP33]] | // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP33]] | ||||
| // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] | // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] | ||||
| // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | ||||
| // CHECK1: omp.inner.for.body: | // CHECK1: omp.inner.for.body: | ||||
| // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]] | // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]] | ||||
| // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 | // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 | ||||
| // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | ||||
| // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP33]] | // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP33]] | ||||
| // CHECK1-NEXT: invoke void @_Z3foov() | // CHECK1-NEXT: call unwindabort void @_Z3foov(), !llvm.access.group [[ACC_GRP33]] | ||||
| // CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP33]] | |||||
| // CHECK1: invoke.cont: | |||||
| // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | ||||
| // CHECK1: omp.body.continue: | // CHECK1: omp.body.continue: | ||||
| // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | ||||
| // CHECK1: omp.inner.for.inc: | // CHECK1: omp.inner.for.inc: | ||||
| // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]] | // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]] | ||||
| // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 | // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 | ||||
| // CHECK1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]] | // CHECK1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]] | ||||
| // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]] | // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]] | ||||
| // CHECK1: omp.inner.for.end: | // CHECK1: omp.inner.for.end: | ||||
| // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | ||||
| // CHECK1: omp.loop.exit: | // CHECK1: omp.loop.exit: | ||||
| // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) | // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) | ||||
| // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 | // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 | ||||
| // CHECK1-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 | // CHECK1-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 | ||||
| // CHECK1-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] | // CHECK1-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] | ||||
| // CHECK1: .omp.final.then: | // CHECK1: .omp.final.then: | ||||
| // CHECK1-NEXT: store i32 100, ptr [[I]], align 4 | // CHECK1-NEXT: store i32 100, ptr [[I]], align 4 | ||||
| // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] | // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] | ||||
| // CHECK1: .omp.final.done: | // CHECK1: .omp.final.done: | ||||
| // CHECK1-NEXT: ret void | // CHECK1-NEXT: ret void | ||||
| // CHECK1: terminate.lpad: | |||||
| // CHECK1-NEXT: [[TMP13:%.*]] = landingpad { ptr, i32 } | |||||
| // CHECK1-NEXT: catch ptr null | |||||
| // CHECK1-NEXT: [[TMP14:%.*]] = extractvalue { ptr, i32 } [[TMP13]], 0 | |||||
| // CHECK1-NEXT: call void @__clang_call_terminate(ptr [[TMP14]]) #[[ATTR9]], !llvm.access.group [[ACC_GRP33]] | |||||
| // CHECK1-NEXT: unreachable | |||||
| // | // | ||||
| // | // | ||||
| // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l36 | // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l36 | ||||
| // CHECK1-SAME: () #[[ATTR3]] { | // CHECK1-SAME: () #[[ATTR3]] { | ||||
| // CHECK1-NEXT: entry: | // CHECK1-NEXT: entry: | ||||
| // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @.omp_outlined..8) | // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @.omp_outlined..8) | ||||
| // CHECK1-NEXT: ret void | // CHECK1-NEXT: ret void | ||||
| // | // | ||||
| ▲ Show 20 Lines • Show All 116 Lines • ▼ Show 20 Lines | |||||
| // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP39]] | // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP39]] | ||||
| // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] | // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] | ||||
| // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | ||||
| // CHECK1: omp.inner.for.body: | // CHECK1: omp.inner.for.body: | ||||
| // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP39]] | // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP39]] | ||||
| // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 | // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 | ||||
| // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | ||||
| // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP39]] | // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP39]] | ||||
| // CHECK1-NEXT: invoke void @_Z3foov() | // CHECK1-NEXT: call unwindabort void @_Z3foov(), !llvm.access.group [[ACC_GRP39]] | ||||
| // CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP39]] | |||||
| // CHECK1: invoke.cont: | |||||
| // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | ||||
| // CHECK1: omp.body.continue: | // CHECK1: omp.body.continue: | ||||
| // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | ||||
| // CHECK1: omp.inner.for.inc: | // CHECK1: omp.inner.for.inc: | ||||
| // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP39]] | // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP39]] | ||||
| // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 | // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 | ||||
| // CHECK1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP39]] | // CHECK1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP39]] | ||||
| // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP40:![0-9]+]] | // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP40:![0-9]+]] | ||||
| // CHECK1: omp.inner.for.end: | // CHECK1: omp.inner.for.end: | ||||
| // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | ||||
| // CHECK1: omp.loop.exit: | // CHECK1: omp.loop.exit: | ||||
| // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) | // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) | ||||
| // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 | // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 | ||||
| // CHECK1-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 | // CHECK1-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 | ||||
| // CHECK1-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] | // CHECK1-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] | ||||
| // CHECK1: .omp.final.then: | // CHECK1: .omp.final.then: | ||||
| // CHECK1-NEXT: store i32 100, ptr [[I]], align 4 | // CHECK1-NEXT: store i32 100, ptr [[I]], align 4 | ||||
| // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] | // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] | ||||
| // CHECK1: .omp.final.done: | // CHECK1: .omp.final.done: | ||||
| // CHECK1-NEXT: ret void | // CHECK1-NEXT: ret void | ||||
| // CHECK1: terminate.lpad: | |||||
| // CHECK1-NEXT: [[TMP13:%.*]] = landingpad { ptr, i32 } | |||||
| // CHECK1-NEXT: catch ptr null | |||||
| // CHECK1-NEXT: [[TMP14:%.*]] = extractvalue { ptr, i32 } [[TMP13]], 0 | |||||
| // CHECK1-NEXT: call void @__clang_call_terminate(ptr [[TMP14]]) #[[ATTR9]], !llvm.access.group [[ACC_GRP39]] | |||||
| // CHECK1-NEXT: unreachable | |||||
| // | // | ||||
| // | // | ||||
| // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l40 | // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l40 | ||||
| // CHECK1-SAME: () #[[ATTR3]] personality ptr @__gxx_personality_v0 { | // CHECK1-SAME: () #[[ATTR3]] personality ptr @__gxx_personality_v0 { | ||||
| // CHECK1-NEXT: entry: | // CHECK1-NEXT: entry: | ||||
| // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 | // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 | ||||
| // CHECK1-NEXT: [[REF_TMP:%.*]] = alloca [[STRUCT_S:%.*]], align 8 | // CHECK1-NEXT: [[REF_TMP:%.*]] = alloca [[STRUCT_S:%.*]], align 8 | ||||
| // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 | // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 | ||||
| // CHECK1-NEXT: invoke void @_ZN1SC1El(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]], i64 noundef 23) | // CHECK1-NEXT: call unwindabort void @_ZN1SC1El(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]], i64 noundef 23) | ||||
| // CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] | |||||
| // CHECK1: invoke.cont: | |||||
| // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i8 @_ZN1ScvcEv(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) | // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i8 @_ZN1ScvcEv(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) | ||||
| // CHECK1-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]] | // CHECK1-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR5]] | ||||
| // CHECK1-NEXT: store i8 [[CALL]], ptr [[DOTCAPTURE_EXPR_]], align 1 | // CHECK1-NEXT: store i8 [[CALL]], ptr [[DOTCAPTURE_EXPR_]], align 1 | ||||
| // CHECK1-NEXT: [[TMP0:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 | // CHECK1-NEXT: [[TMP0:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 | ||||
| // CHECK1-NEXT: store i8 [[TMP0]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 1 | // CHECK1-NEXT: store i8 [[TMP0]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 1 | ||||
| // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8 | // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8 | ||||
| // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 1, ptr @.omp_outlined..10, i64 [[TMP1]]) | // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 1, ptr @.omp_outlined..10, i64 [[TMP1]]) | ||||
| // CHECK1-NEXT: ret void | // CHECK1-NEXT: ret void | ||||
| // CHECK1: terminate.lpad: | |||||
| // CHECK1-NEXT: [[TMP2:%.*]] = landingpad { ptr, i32 } | |||||
| // CHECK1-NEXT: catch ptr null | |||||
| // CHECK1-NEXT: [[TMP3:%.*]] = extractvalue { ptr, i32 } [[TMP2]], 0 | |||||
| // CHECK1-NEXT: call void @__clang_call_terminate(ptr [[TMP3]]) #[[ATTR9]] | |||||
| // CHECK1-NEXT: unreachable | |||||
| // | // | ||||
| // | // | ||||
| // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..10 | // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..10 | ||||
| // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { | // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { | ||||
| // CHECK1-NEXT: entry: | // CHECK1-NEXT: entry: | ||||
| // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 | // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 | ||||
| // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 | // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 | ||||
| // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 | // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 | ||||
| ▲ Show 20 Lines • Show All 113 Lines • ▼ Show 20 Lines | |||||
| // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP45]] | // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP45]] | ||||
| // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] | // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] | ||||
| // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | ||||
| // CHECK1: omp.inner.for.body: | // CHECK1: omp.inner.for.body: | ||||
| // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45]] | // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45]] | ||||
| // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 | // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 | ||||
| // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | ||||
| // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP45]] | // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP45]] | ||||
| // CHECK1-NEXT: invoke void @_Z3foov() | // CHECK1-NEXT: call unwindabort void @_Z3foov(), !llvm.access.group [[ACC_GRP45]] | ||||
| // CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP45]] | |||||
| // CHECK1: invoke.cont: | |||||
| // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | ||||
| // CHECK1: omp.body.continue: | // CHECK1: omp.body.continue: | ||||
| // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | ||||
| // CHECK1: omp.inner.for.inc: | // CHECK1: omp.inner.for.inc: | ||||
| // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45]] | // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45]] | ||||
| // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 | // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 | ||||
| // CHECK1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45]] | // CHECK1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45]] | ||||
| // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP46:![0-9]+]] | // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP46:![0-9]+]] | ||||
| // CHECK1: omp.inner.for.end: | // CHECK1: omp.inner.for.end: | ||||
| // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | ||||
| // CHECK1: omp.loop.exit: | // CHECK1: omp.loop.exit: | ||||
| // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) | // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) | ||||
| // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 | // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 | ||||
| // CHECK1-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 | // CHECK1-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 | ||||
| // CHECK1-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] | // CHECK1-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] | ||||
| // CHECK1: .omp.final.then: | // CHECK1: .omp.final.then: | ||||
| // CHECK1-NEXT: store i32 100, ptr [[I]], align 4 | // CHECK1-NEXT: store i32 100, ptr [[I]], align 4 | ||||
| // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] | // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] | ||||
| // CHECK1: .omp.final.done: | // CHECK1: .omp.final.done: | ||||
| // CHECK1-NEXT: ret void | // CHECK1-NEXT: ret void | ||||
| // CHECK1: terminate.lpad: | |||||
| // CHECK1-NEXT: [[TMP13:%.*]] = landingpad { ptr, i32 } | |||||
| // CHECK1-NEXT: catch ptr null | |||||
| // CHECK1-NEXT: [[TMP14:%.*]] = extractvalue { ptr, i32 } [[TMP13]], 0 | |||||
| // CHECK1-NEXT: call void @__clang_call_terminate(ptr [[TMP14]]) #[[ATTR9]], !llvm.access.group [[ACC_GRP45]] | |||||
| // CHECK1-NEXT: unreachable | |||||
| // | // | ||||
| // | // | ||||
| // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg | // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg | ||||
| // CHECK1-SAME: () #[[ATTR8:[0-9]+]] section ".text.startup" { | // CHECK1-SAME: () #[[ATTR8:[0-9]+]] section ".text.startup" { | ||||
| // CHECK1-NEXT: entry: | // CHECK1-NEXT: entry: | ||||
| // CHECK1-NEXT: call void @__tgt_register_requires(i64 1) | // CHECK1-NEXT: call void @__tgt_register_requires(i64 1) | ||||
| // CHECK1-NEXT: ret void | // CHECK1-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK3-LABEL: define {{[^@]+}}@main | // CHECK3-LABEL: define {{[^@]+}}@main | ||||
| // CHECK3-SAME: () #[[ATTR0:[0-9]+]] personality ptr @__gxx_personality_v0 { | // CHECK3-SAME: () #[[ATTR0:[0-9]+]] personality ptr @__gxx_personality_v0 { | ||||
| // CHECK3-NEXT: entry: | // CHECK3-NEXT: entry: | ||||
| // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 | // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 | ||||
| // CHECK3-NEXT: [[S:%.*]] = alloca [[STRUCT_S:%.*]], align 8 | // CHECK3-NEXT: [[S:%.*]] = alloca [[STRUCT_S:%.*]], align 8 | ||||
| // CHECK3-NEXT: [[A:%.*]] = alloca i8, align 1 | // CHECK3-NEXT: [[A:%.*]] = alloca i8, align 1 | ||||
| // CHECK3-NEXT: [[EXN_SLOT:%.*]] = alloca ptr, align 8 | // CHECK3-NEXT: [[EXN_SLOT:%.*]] = alloca ptr, align 8 | ||||
| // CHECK3-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 | // CHECK3-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 | ||||
| // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 | // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 | ||||
| // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | ||||
| // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 | // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 | ||||
| // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | ||||
| // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 | // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 | ||||
| // CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 | // CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 | ||||
| // CHECK3-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 | // CHECK3-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 | ||||
| // CHECK3-NEXT: [[DOTOMP_LB4:%.*]] = alloca i32, align 4 | // CHECK3-NEXT: [[DOTOMP_LB3:%.*]] = alloca i32, align 4 | ||||
| // CHECK3-NEXT: [[DOTOMP_UB5:%.*]] = alloca i32, align 4 | // CHECK3-NEXT: [[DOTOMP_UB4:%.*]] = alloca i32, align 4 | ||||
| // CHECK3-NEXT: [[DOTOMP_IV6:%.*]] = alloca i32, align 4 | // CHECK3-NEXT: [[DOTOMP_IV5:%.*]] = alloca i32, align 4 | ||||
| // CHECK3-NEXT: [[I7:%.*]] = alloca i32, align 4 | // CHECK3-NEXT: [[I6:%.*]] = alloca i32, align 4 | ||||
| // CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4 | // CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4 | ||||
| // CHECK3-NEXT: call void @_ZN1SC1El(ptr noundef nonnull align 8 dereferenceable(24) [[S]], i64 noundef 0) | // CHECK3-NEXT: call void @_ZN1SC1El(ptr noundef nonnull align 8 dereferenceable(24) [[S]], i64 noundef 0) | ||||
| // CHECK3-NEXT: [[CALL:%.*]] = invoke noundef signext i8 @_ZN1ScvcEv(ptr noundef nonnull align 8 dereferenceable(24) [[S]]) | // CHECK3-NEXT: [[CALL:%.*]] = invoke noundef signext i8 @_ZN1ScvcEv(ptr noundef nonnull align 8 dereferenceable(24) [[S]]) | ||||
| // CHECK3-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] | // CHECK3-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]] | ||||
| // CHECK3: invoke.cont: | // CHECK3: invoke.cont: | ||||
| // CHECK3-NEXT: store i8 [[CALL]], ptr [[A]], align 1 | // CHECK3-NEXT: store i8 [[CALL]], ptr [[A]], align 1 | ||||
| // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 | // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 | ||||
| // CHECK3-NEXT: store i32 99, ptr [[DOTOMP_UB]], align 4 | // CHECK3-NEXT: store i32 99, ptr [[DOTOMP_UB]], align 4 | ||||
| // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 | // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 | ||||
| // CHECK3-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4 | // CHECK3-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4 | ||||
| // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] | // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] | ||||
| // CHECK3: omp.inner.for.cond: | // CHECK3: omp.inner.for.cond: | ||||
| // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2:![0-9]+]] | // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2:![0-9]+]] | ||||
| // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP2]] | // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP2]] | ||||
| // CHECK3-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] | // CHECK3-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] | ||||
| // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | ||||
| // CHECK3: omp.inner.for.body: | // CHECK3: omp.inner.for.body: | ||||
| // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] | // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] | ||||
| // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 | // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 | ||||
| // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | ||||
| // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] | // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] | ||||
| // CHECK3-NEXT: invoke void @_Z3foov() | // CHECK3-NEXT: call unwindabort void @_Z3foov(), !llvm.access.group [[ACC_GRP2]] | ||||
| // CHECK3-NEXT: to label [[INVOKE_CONT1:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP2]] | |||||
| // CHECK3: invoke.cont1: | |||||
| // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | ||||
| // CHECK3: omp.body.continue: | // CHECK3: omp.body.continue: | ||||
| // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | ||||
| // CHECK3: omp.inner.for.inc: | // CHECK3: omp.inner.for.inc: | ||||
| // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] | // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] | ||||
| // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP4]], 1 | // CHECK3-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 | ||||
| // CHECK3-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] | // CHECK3-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] | ||||
| // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] | // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] | ||||
| // CHECK3: lpad: | // CHECK3: lpad: | ||||
| // CHECK3-NEXT: [[TMP5:%.*]] = landingpad { ptr, i32 } | // CHECK3-NEXT: [[TMP5:%.*]] = landingpad { ptr, i32 } | ||||
| // CHECK3-NEXT: cleanup | // CHECK3-NEXT: cleanup | ||||
| // CHECK3-NEXT: [[TMP6:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 0 | // CHECK3-NEXT: [[TMP6:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 0 | ||||
| // CHECK3-NEXT: store ptr [[TMP6]], ptr [[EXN_SLOT]], align 8 | // CHECK3-NEXT: store ptr [[TMP6]], ptr [[EXN_SLOT]], align 8 | ||||
| // CHECK3-NEXT: [[TMP7:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 1 | // CHECK3-NEXT: [[TMP7:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 1 | ||||
| // CHECK3-NEXT: store i32 [[TMP7]], ptr [[EHSELECTOR_SLOT]], align 4 | // CHECK3-NEXT: store i32 [[TMP7]], ptr [[EHSELECTOR_SLOT]], align 4 | ||||
| // CHECK3-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR6:[0-9]+]] | // CHECK3-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR6:[0-9]+]] | ||||
| // CHECK3-NEXT: br label [[EH_RESUME:%.*]] | // CHECK3-NEXT: br label [[EH_RESUME:%.*]] | ||||
| // CHECK3: omp.inner.for.end: | // CHECK3: omp.inner.for.end: | ||||
| // CHECK3-NEXT: store i32 100, ptr [[I]], align 4 | // CHECK3-NEXT: store i32 100, ptr [[I]], align 4 | ||||
| // CHECK3-NEXT: [[TMP8:%.*]] = load i8, ptr [[A]], align 1 | // CHECK3-NEXT: [[TMP8:%.*]] = load i8, ptr [[A]], align 1 | ||||
| // CHECK3-NEXT: store i8 [[TMP8]], ptr [[DOTCAPTURE_EXPR_]], align 1 | // CHECK3-NEXT: store i8 [[TMP8]], ptr [[DOTCAPTURE_EXPR_]], align 1 | ||||
| // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB4]], align 4 | // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB3]], align 4 | ||||
| // CHECK3-NEXT: store i32 99, ptr [[DOTOMP_UB5]], align 4 | // CHECK3-NEXT: store i32 99, ptr [[DOTOMP_UB4]], align 4 | ||||
| // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_LB4]], align 4 | // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_LB3]], align 4 | ||||
| // CHECK3-NEXT: store i32 [[TMP9]], ptr [[DOTOMP_IV6]], align 4 | // CHECK3-NEXT: store i32 [[TMP9]], ptr [[DOTOMP_IV5]], align 4 | ||||
| // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND8:%.*]] | // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND7:%.*]] | ||||
| // CHECK3: omp.inner.for.cond8: | // CHECK3: omp.inner.for.cond7: | ||||
| // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP6:![0-9]+]] | // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV5]], align 4, !llvm.access.group [[ACC_GRP6:![0-9]+]] | ||||
| // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB5]], align 4, !llvm.access.group [[ACC_GRP6]] | // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB4]], align 4, !llvm.access.group [[ACC_GRP6]] | ||||
| // CHECK3-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] | // CHECK3-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] | ||||
| // CHECK3-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY10:%.*]], label [[OMP_INNER_FOR_END17:%.*]] | // CHECK3-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY9:%.*]], label [[OMP_INNER_FOR_END15:%.*]] | ||||
| // CHECK3: omp.inner.for.body10: | // CHECK3: omp.inner.for.body9: | ||||
| // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP6]] | // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV5]], align 4, !llvm.access.group [[ACC_GRP6]] | ||||
| // CHECK3-NEXT: [[MUL11:%.*]] = mul nsw i32 [[TMP12]], 1 | // CHECK3-NEXT: [[MUL10:%.*]] = mul nsw i32 [[TMP12]], 1 | ||||
| // CHECK3-NEXT: [[ADD12:%.*]] = add nsw i32 0, [[MUL11]] | // CHECK3-NEXT: [[ADD11:%.*]] = add nsw i32 0, [[MUL10]] | ||||
| // CHECK3-NEXT: store i32 [[ADD12]], ptr [[I7]], align 4, !llvm.access.group [[ACC_GRP6]] | // CHECK3-NEXT: store i32 [[ADD11]], ptr [[I6]], align 4, !llvm.access.group [[ACC_GRP6]] | ||||
| // CHECK3-NEXT: invoke void @_Z3foov() | // CHECK3-NEXT: call unwindabort void @_Z3foov(), !llvm.access.group [[ACC_GRP6]] | ||||
| // CHECK3-NEXT: to label [[INVOKE_CONT13:%.*]] unwind label [[TERMINATE_LPAD]], !llvm.access.group [[ACC_GRP6]] | // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE12:%.*]] | ||||
| // CHECK3: invoke.cont13: | // CHECK3: omp.body.continue12: | ||||
| // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE14:%.*]] | // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC13:%.*]] | ||||
| // CHECK3: omp.body.continue14: | // CHECK3: omp.inner.for.inc13: | ||||
| // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC15:%.*]] | // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV5]], align 4, !llvm.access.group [[ACC_GRP6]] | ||||
| // CHECK3: omp.inner.for.inc15: | // CHECK3-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP13]], 1 | ||||
| // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP6]] | // CHECK3-NEXT: store i32 [[ADD14]], ptr [[DOTOMP_IV5]], align 4, !llvm.access.group [[ACC_GRP6]] | ||||
| // CHECK3-NEXT: [[ADD16:%.*]] = add nsw i32 [[TMP13]], 1 | // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND7]], !llvm.loop [[LOOP7:![0-9]+]] | ||||
| // CHECK3-NEXT: store i32 [[ADD16]], ptr [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP6]] | // CHECK3: omp.inner.for.end15: | ||||
| // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND8]], !llvm.loop [[LOOP7:![0-9]+]] | // CHECK3-NEXT: store i32 100, ptr [[I6]], align 4 | ||||
| // CHECK3: omp.inner.for.end17: | |||||
| // CHECK3-NEXT: store i32 100, ptr [[I7]], align 4 | |||||
| // CHECK3-NEXT: [[TMP14:%.*]] = load i8, ptr [[A]], align 1 | // CHECK3-NEXT: [[TMP14:%.*]] = load i8, ptr [[A]], align 1 | ||||
| // CHECK3-NEXT: [[CONV:%.*]] = sext i8 [[TMP14]] to i32 | // CHECK3-NEXT: [[CONV:%.*]] = sext i8 [[TMP14]] to i32 | ||||
| // CHECK3-NEXT: [[CALL19:%.*]] = invoke noundef signext i32 @_Z5tmainIcLi5EEiv() | // CHECK3-NEXT: [[CALL17:%.*]] = invoke noundef signext i32 @_Z5tmainIcLi5EEiv() | ||||
| // CHECK3-NEXT: to label [[INVOKE_CONT18:%.*]] unwind label [[LPAD]] | // CHECK3-NEXT: to label [[INVOKE_CONT16:%.*]] unwind label [[LPAD]] | ||||
| // CHECK3: invoke.cont18: | // CHECK3: invoke.cont16: | ||||
| // CHECK3-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV]], [[CALL19]] | // CHECK3-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV]], [[CALL17]] | ||||
| // CHECK3-NEXT: [[CALL22:%.*]] = invoke noundef signext i32 @_Z5tmainI1SLi1EEiv() | // CHECK3-NEXT: [[CALL20:%.*]] = invoke noundef signext i32 @_Z5tmainI1SLi1EEiv() | ||||
| // CHECK3-NEXT: to label [[INVOKE_CONT21:%.*]] unwind label [[LPAD]] | // CHECK3-NEXT: to label [[INVOKE_CONT19:%.*]] unwind label [[LPAD]] | ||||
| // CHECK3: invoke.cont21: | // CHECK3: invoke.cont19: | ||||
| // CHECK3-NEXT: [[ADD23:%.*]] = add nsw i32 [[ADD20]], [[CALL22]] | // CHECK3-NEXT: [[ADD21:%.*]] = add nsw i32 [[ADD18]], [[CALL20]] | ||||
| // CHECK3-NEXT: store i32 [[ADD23]], ptr [[RETVAL]], align 4 | // CHECK3-NEXT: store i32 [[ADD21]], ptr [[RETVAL]], align 4 | ||||
| // CHECK3-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR6]] | // CHECK3-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR6]] | ||||
| // CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[RETVAL]], align 4 | // CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[RETVAL]], align 4 | ||||
| // CHECK3-NEXT: ret i32 [[TMP15]] | // CHECK3-NEXT: ret i32 [[TMP15]] | ||||
| // CHECK3: eh.resume: | // CHECK3: eh.resume: | ||||
| // CHECK3-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8 | // CHECK3-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8 | ||||
| // CHECK3-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4 | // CHECK3-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4 | ||||
| // CHECK3-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0 | // CHECK3-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0 | ||||
| // CHECK3-NEXT: [[LPAD_VAL24:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1 | // CHECK3-NEXT: [[LPAD_VAL22:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1 | ||||
| // CHECK3-NEXT: resume { ptr, i32 } [[LPAD_VAL24]] | // CHECK3-NEXT: resume { ptr, i32 } [[LPAD_VAL22]] | ||||
| // CHECK3: terminate.lpad: | |||||
| // CHECK3-NEXT: [[TMP16:%.*]] = landingpad { ptr, i32 } | |||||
| // CHECK3-NEXT: catch ptr null | |||||
| // CHECK3-NEXT: [[TMP17:%.*]] = extractvalue { ptr, i32 } [[TMP16]], 0 | |||||
| // CHECK3-NEXT: call void @__clang_call_terminate(ptr [[TMP17]]) #[[ATTR7:[0-9]+]], !llvm.access.group [[ACC_GRP2]] | |||||
| // CHECK3-NEXT: unreachable | |||||
| // | // | ||||
| // | // | ||||
| // CHECK3-LABEL: define {{[^@]+}}@_ZN1SC1El | // CHECK3-LABEL: define {{[^@]+}}@_ZN1SC1El | ||||
| // CHECK3-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { | // CHECK3-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { | ||||
| // CHECK3-NEXT: entry: | // CHECK3-NEXT: entry: | ||||
| // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 | // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 | ||||
| // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 | // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 | ||||
| Show All 11 Lines | |||||
| // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 | // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 | ||||
| // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 | // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 | ||||
| // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 | // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 | ||||
| // CHECK3-NEXT: [[TMP0:%.*]] = load i64, ptr [[A]], align 8 | // CHECK3-NEXT: [[TMP0:%.*]] = load i64, ptr [[A]], align 8 | ||||
| // CHECK3-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i8 | // CHECK3-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i8 | ||||
| // CHECK3-NEXT: ret i8 [[CONV]] | // CHECK3-NEXT: ret i8 [[CONV]] | ||||
| // | // | ||||
| // | // | ||||
| // CHECK3-LABEL: define {{[^@]+}}@__clang_call_terminate | |||||
| // CHECK3-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR4:[0-9]+]] comdat { | |||||
| // CHECK3-NEXT: [[TMP2:%.*]] = call ptr @__cxa_begin_catch(ptr [[TMP0]]) #[[ATTR6]] | |||||
| // CHECK3-NEXT: call void @_ZSt9terminatev() #[[ATTR7]] | |||||
| // CHECK3-NEXT: unreachable | |||||
| // | |||||
| // | |||||
| // CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIcLi5EEiv | // CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIcLi5EEiv | ||||
| // CHECK3-SAME: () #[[ATTR2]] comdat personality ptr @__gxx_personality_v0 { | // CHECK3-SAME: () #[[ATTR4:[0-9]+]] comdat personality ptr @__gxx_personality_v0 { | ||||
| // CHECK3-NEXT: entry: | // CHECK3-NEXT: entry: | ||||
| // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 | // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 | ||||
| // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | ||||
| // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 | // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 | ||||
| // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | ||||
| // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 | // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 | ||||
| // CHECK3-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 | // CHECK3-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 | ||||
| // CHECK3-NEXT: [[DOTOMP_LB3:%.*]] = alloca i32, align 4 | // CHECK3-NEXT: [[DOTOMP_LB3:%.*]] = alloca i32, align 4 | ||||
| Show All 10 Lines | |||||
| // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP9]] | // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP9]] | ||||
| // CHECK3-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] | // CHECK3-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] | ||||
| // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | ||||
| // CHECK3: omp.inner.for.body: | // CHECK3: omp.inner.for.body: | ||||
| // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]] | // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]] | ||||
| // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 | // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 | ||||
| // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | ||||
| // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] | // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] | ||||
| // CHECK3-NEXT: invoke void @_Z3foov() | // CHECK3-NEXT: call unwindabort void @_Z3foov(), !llvm.access.group [[ACC_GRP9]] | ||||
| // CHECK3-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP9]] | |||||
| // CHECK3: invoke.cont: | |||||
| // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | ||||
| // CHECK3: omp.body.continue: | // CHECK3: omp.body.continue: | ||||
| // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | ||||
| // CHECK3: omp.inner.for.inc: | // CHECK3: omp.inner.for.inc: | ||||
| // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]] | // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]] | ||||
| // CHECK3-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 | // CHECK3-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 | ||||
| // CHECK3-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]] | // CHECK3-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]] | ||||
| // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] | // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] | ||||
| // CHECK3: omp.inner.for.end: | // CHECK3: omp.inner.for.end: | ||||
| // CHECK3-NEXT: store i32 100, ptr [[I]], align 4 | // CHECK3-NEXT: store i32 100, ptr [[I]], align 4 | ||||
| // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB3]], align 4 | // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB3]], align 4 | ||||
| // CHECK3-NEXT: store i32 99, ptr [[DOTOMP_UB4]], align 4 | // CHECK3-NEXT: store i32 99, ptr [[DOTOMP_UB4]], align 4 | ||||
| // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB3]], align 4 | // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB3]], align 4 | ||||
| // CHECK3-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV5]], align 4 | // CHECK3-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV5]], align 4 | ||||
| // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND7:%.*]] | // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND7:%.*]] | ||||
| // CHECK3: omp.inner.for.cond7: | // CHECK3: omp.inner.for.cond7: | ||||
| // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV5]], align 4, !llvm.access.group [[ACC_GRP12:![0-9]+]] | // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV5]], align 4, !llvm.access.group [[ACC_GRP12:![0-9]+]] | ||||
| // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB4]], align 4, !llvm.access.group [[ACC_GRP12]] | // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB4]], align 4, !llvm.access.group [[ACC_GRP12]] | ||||
| // CHECK3-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] | // CHECK3-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] | ||||
| // CHECK3-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY9:%.*]], label [[OMP_INNER_FOR_END16:%.*]] | // CHECK3-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY9:%.*]], label [[OMP_INNER_FOR_END15:%.*]] | ||||
| // CHECK3: omp.inner.for.body9: | // CHECK3: omp.inner.for.body9: | ||||
| // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV5]], align 4, !llvm.access.group [[ACC_GRP12]] | // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV5]], align 4, !llvm.access.group [[ACC_GRP12]] | ||||
| // CHECK3-NEXT: [[MUL10:%.*]] = mul nsw i32 [[TMP8]], 1 | // CHECK3-NEXT: [[MUL10:%.*]] = mul nsw i32 [[TMP8]], 1 | ||||
| // CHECK3-NEXT: [[ADD11:%.*]] = add nsw i32 0, [[MUL10]] | // CHECK3-NEXT: [[ADD11:%.*]] = add nsw i32 0, [[MUL10]] | ||||
| // CHECK3-NEXT: store i32 [[ADD11]], ptr [[I6]], align 4, !llvm.access.group [[ACC_GRP12]] | // CHECK3-NEXT: store i32 [[ADD11]], ptr [[I6]], align 4, !llvm.access.group [[ACC_GRP12]] | ||||
| // CHECK3-NEXT: invoke void @_Z3foov() | // CHECK3-NEXT: call unwindabort void @_Z3foov(), !llvm.access.group [[ACC_GRP12]] | ||||
| // CHECK3-NEXT: to label [[INVOKE_CONT12:%.*]] unwind label [[TERMINATE_LPAD]], !llvm.access.group [[ACC_GRP12]] | // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE12:%.*]] | ||||
| // CHECK3: invoke.cont12: | // CHECK3: omp.body.continue12: | ||||
| // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE13:%.*]] | // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC13:%.*]] | ||||
| // CHECK3: omp.body.continue13: | // CHECK3: omp.inner.for.inc13: | ||||
| // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC14:%.*]] | |||||
| // CHECK3: omp.inner.for.inc14: | |||||
| // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV5]], align 4, !llvm.access.group [[ACC_GRP12]] | // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV5]], align 4, !llvm.access.group [[ACC_GRP12]] | ||||
| // CHECK3-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP9]], 1 | // CHECK3-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP9]], 1 | ||||
| // CHECK3-NEXT: store i32 [[ADD15]], ptr [[DOTOMP_IV5]], align 4, !llvm.access.group [[ACC_GRP12]] | // CHECK3-NEXT: store i32 [[ADD14]], ptr [[DOTOMP_IV5]], align 4, !llvm.access.group [[ACC_GRP12]] | ||||
| // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND7]], !llvm.loop [[LOOP13:![0-9]+]] | // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND7]], !llvm.loop [[LOOP13:![0-9]+]] | ||||
| // CHECK3: omp.inner.for.end16: | // CHECK3: omp.inner.for.end15: | ||||
| // CHECK3-NEXT: store i32 100, ptr [[I6]], align 4 | // CHECK3-NEXT: store i32 100, ptr [[I6]], align 4 | ||||
| // CHECK3-NEXT: ret i32 0 | // CHECK3-NEXT: ret i32 0 | ||||
| // CHECK3: terminate.lpad: | |||||
| // CHECK3-NEXT: [[TMP10:%.*]] = landingpad { ptr, i32 } | |||||
| // CHECK3-NEXT: catch ptr null | |||||
| // CHECK3-NEXT: [[TMP11:%.*]] = extractvalue { ptr, i32 } [[TMP10]], 0 | |||||
| // CHECK3-NEXT: call void @__clang_call_terminate(ptr [[TMP11]]) #[[ATTR7]], !llvm.access.group [[ACC_GRP9]] | |||||
| // CHECK3-NEXT: unreachable | |||||
| // | // | ||||
| // | // | ||||
| // CHECK3-LABEL: define {{[^@]+}}@_Z5tmainI1SLi1EEiv | // CHECK3-LABEL: define {{[^@]+}}@_Z5tmainI1SLi1EEiv | ||||
| // CHECK3-SAME: () #[[ATTR2]] comdat personality ptr @__gxx_personality_v0 { | // CHECK3-SAME: () #[[ATTR4]] comdat personality ptr @__gxx_personality_v0 { | ||||
| // CHECK3-NEXT: entry: | // CHECK3-NEXT: entry: | ||||
| // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 | // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 | ||||
| // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 | ||||
| // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 | // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 | ||||
| // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 | ||||
| // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 | // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 | ||||
| // CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 | // CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 | ||||
| // CHECK3-NEXT: [[REF_TMP:%.*]] = alloca [[STRUCT_S:%.*]], align 8 | // CHECK3-NEXT: [[REF_TMP:%.*]] = alloca [[STRUCT_S:%.*]], align 8 | ||||
| // CHECK3-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 | // CHECK3-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 | ||||
| // CHECK3-NEXT: [[DOTOMP_LB4:%.*]] = alloca i32, align 4 | // CHECK3-NEXT: [[DOTOMP_LB3:%.*]] = alloca i32, align 4 | ||||
| // CHECK3-NEXT: [[DOTOMP_UB5:%.*]] = alloca i32, align 4 | // CHECK3-NEXT: [[DOTOMP_UB4:%.*]] = alloca i32, align 4 | ||||
| // CHECK3-NEXT: [[DOTOMP_IV6:%.*]] = alloca i32, align 4 | // CHECK3-NEXT: [[DOTOMP_IV5:%.*]] = alloca i32, align 4 | ||||
| // CHECK3-NEXT: [[I7:%.*]] = alloca i32, align 4 | // CHECK3-NEXT: [[I6:%.*]] = alloca i32, align 4 | ||||
| // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 | // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 | ||||
| // CHECK3-NEXT: store i32 99, ptr [[DOTOMP_UB]], align 4 | // CHECK3-NEXT: store i32 99, ptr [[DOTOMP_UB]], align 4 | ||||
| // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 | // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 | ||||
| // CHECK3-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4 | // CHECK3-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4 | ||||
| // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] | // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] | ||||
| // CHECK3: omp.inner.for.cond: | // CHECK3: omp.inner.for.cond: | ||||
| // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15:![0-9]+]] | // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15:![0-9]+]] | ||||
| // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP15]] | // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP15]] | ||||
| // CHECK3-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] | // CHECK3-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] | ||||
| // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | ||||
| // CHECK3: omp.inner.for.body: | // CHECK3: omp.inner.for.body: | ||||
| // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15]] | // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15]] | ||||
| // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 | // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 | ||||
| // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | ||||
| // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP15]] | // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP15]] | ||||
| // CHECK3-NEXT: invoke void @_Z3foov() | // CHECK3-NEXT: call unwindabort void @_Z3foov(), !llvm.access.group [[ACC_GRP15]] | ||||
| // CHECK3-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP15]] | |||||
| // CHECK3: invoke.cont: | |||||
| // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | ||||
| // CHECK3: omp.body.continue: | // CHECK3: omp.body.continue: | ||||
| // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | ||||
| // CHECK3: omp.inner.for.inc: | // CHECK3: omp.inner.for.inc: | ||||
| // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15]] | // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15]] | ||||
| // CHECK3-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 | // CHECK3-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 | ||||
| // CHECK3-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15]] | // CHECK3-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15]] | ||||
| // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] | // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] | ||||
| // CHECK3: omp.inner.for.end: | // CHECK3: omp.inner.for.end: | ||||
| // CHECK3-NEXT: store i32 100, ptr [[I]], align 4 | // CHECK3-NEXT: store i32 100, ptr [[I]], align 4 | ||||
| // CHECK3-NEXT: invoke void @_ZN1SC1El(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]], i64 noundef 23) | // CHECK3-NEXT: call unwindabort void @_ZN1SC1El(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]], i64 noundef 23) | ||||
| // CHECK3-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[TERMINATE_LPAD]] | |||||
| // CHECK3: invoke.cont2: | |||||
| // CHECK3-NEXT: [[CALL:%.*]] = call noundef signext i8 @_ZN1ScvcEv(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) | // CHECK3-NEXT: [[CALL:%.*]] = call noundef signext i8 @_ZN1ScvcEv(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) | ||||
| // CHECK3-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]] | // CHECK3-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]] | ||||
| // CHECK3-NEXT: store i8 [[CALL]], ptr [[DOTCAPTURE_EXPR_]], align 1 | // CHECK3-NEXT: store i8 [[CALL]], ptr [[DOTCAPTURE_EXPR_]], align 1 | ||||
| // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB4]], align 4 | // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB3]], align 4 | ||||
| // CHECK3-NEXT: store i32 99, ptr [[DOTOMP_UB5]], align 4 | // CHECK3-NEXT: store i32 99, ptr [[DOTOMP_UB4]], align 4 | ||||
| // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB4]], align 4 | // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB3]], align 4 | ||||
| // CHECK3-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV6]], align 4 | // CHECK3-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV5]], align 4 | ||||
| // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND8:%.*]] | // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND7:%.*]] | ||||
| // CHECK3: omp.inner.for.cond8: | // CHECK3: omp.inner.for.cond7: | ||||
| // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP18:![0-9]+]] | // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV5]], align 4, !llvm.access.group [[ACC_GRP18:![0-9]+]] | ||||
| // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB5]], align 4, !llvm.access.group [[ACC_GRP18]] | // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB4]], align 4, !llvm.access.group [[ACC_GRP18]] | ||||
| // CHECK3-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] | // CHECK3-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] | ||||
| // CHECK3-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY10:%.*]], label [[OMP_INNER_FOR_END17:%.*]] | // CHECK3-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY9:%.*]], label [[OMP_INNER_FOR_END15:%.*]] | ||||
| // CHECK3: omp.inner.for.body10: | // CHECK3: omp.inner.for.body9: | ||||
| // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP18]] | // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV5]], align 4, !llvm.access.group [[ACC_GRP18]] | ||||
| // CHECK3-NEXT: [[MUL11:%.*]] = mul nsw i32 [[TMP8]], 1 | // CHECK3-NEXT: [[MUL10:%.*]] = mul nsw i32 [[TMP8]], 1 | ||||
| // CHECK3-NEXT: [[ADD12:%.*]] = add nsw i32 0, [[MUL11]] | // CHECK3-NEXT: [[ADD11:%.*]] = add nsw i32 0, [[MUL10]] | ||||
| // CHECK3-NEXT: store i32 [[ADD12]], ptr [[I7]], align 4, !llvm.access.group [[ACC_GRP18]] | // CHECK3-NEXT: store i32 [[ADD11]], ptr [[I6]], align 4, !llvm.access.group [[ACC_GRP18]] | ||||
| // CHECK3-NEXT: invoke void @_Z3foov() | // CHECK3-NEXT: call unwindabort void @_Z3foov(), !llvm.access.group [[ACC_GRP18]] | ||||
| // CHECK3-NEXT: to label [[INVOKE_CONT13:%.*]] unwind label [[TERMINATE_LPAD]], !llvm.access.group [[ACC_GRP18]] | // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE12:%.*]] | ||||
| // CHECK3: invoke.cont13: | // CHECK3: omp.body.continue12: | ||||
| // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE14:%.*]] | // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC13:%.*]] | ||||
| // CHECK3: omp.body.continue14: | // CHECK3: omp.inner.for.inc13: | ||||
| // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC15:%.*]] | // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV5]], align 4, !llvm.access.group [[ACC_GRP18]] | ||||
| // CHECK3: omp.inner.for.inc15: | // CHECK3-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP9]], 1 | ||||
| // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP18]] | // CHECK3-NEXT: store i32 [[ADD14]], ptr [[DOTOMP_IV5]], align 4, !llvm.access.group [[ACC_GRP18]] | ||||
| // CHECK3-NEXT: [[ADD16:%.*]] = add nsw i32 [[TMP9]], 1 | // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND7]], !llvm.loop [[LOOP19:![0-9]+]] | ||||
| // CHECK3-NEXT: store i32 [[ADD16]], ptr [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP18]] | // CHECK3: omp.inner.for.end15: | ||||
| // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND8]], !llvm.loop [[LOOP19:![0-9]+]] | // CHECK3-NEXT: store i32 100, ptr [[I6]], align 4 | ||||
| // CHECK3: omp.inner.for.end17: | |||||
| // CHECK3-NEXT: store i32 100, ptr [[I7]], align 4 | |||||
| // CHECK3-NEXT: ret i32 0 | // CHECK3-NEXT: ret i32 0 | ||||
| // CHECK3: terminate.lpad: | |||||
| // CHECK3-NEXT: [[TMP10:%.*]] = landingpad { ptr, i32 } | |||||
| // CHECK3-NEXT: catch ptr null | |||||
| // CHECK3-NEXT: [[TMP11:%.*]] = extractvalue { ptr, i32 } [[TMP10]], 0 | |||||
| // CHECK3-NEXT: call void @__clang_call_terminate(ptr [[TMP11]]) #[[ATTR7]], !llvm.access.group [[ACC_GRP15]] | |||||
| // CHECK3-NEXT: unreachable | |||||
| // | // | ||||
| // | // | ||||
| // CHECK3-LABEL: define {{[^@]+}}@_ZN1SD1Ev | // CHECK3-LABEL: define {{[^@]+}}@_ZN1SD1Ev | ||||
| // CHECK3-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR5:[0-9]+]] comdat align 2 { | // CHECK3-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR5:[0-9]+]] comdat align 2 { | ||||
| // CHECK3-NEXT: entry: | // CHECK3-NEXT: entry: | ||||
| // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 | // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 | ||||
| // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 | // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 | ||||
| // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 | // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 | ||||
| ▲ Show 20 Lines • Show All 63 Lines • ▼ Show 20 Lines | |||||
| // CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 | // CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 | ||||
| // CHECK5-NEXT: store ptr null, ptr [[TMP7]], align 8 | // CHECK5-NEXT: store ptr null, ptr [[TMP7]], align 8 | ||||
| // CHECK5-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 | // CHECK5-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 | ||||
| // CHECK5-NEXT: store i64 100, ptr [[TMP8]], align 8 | // CHECK5-NEXT: store i64 100, ptr [[TMP8]], align 8 | ||||
| // CHECK5-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3:[0-9]+]], i64 -1, i32 0, i32 2, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l50.region_id, ptr [[KERNEL_ARGS]]) | // CHECK5-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3:[0-9]+]], i64 -1, i32 0, i32 2, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l50.region_id, ptr [[KERNEL_ARGS]]) | ||||
| // CHECK5-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 | // CHECK5-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 | ||||
| // CHECK5-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] | // CHECK5-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] | ||||
| // CHECK5: omp_offload.failed: | // CHECK5: omp_offload.failed: | ||||
| // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l50() #[[ATTR6:[0-9]+]] | // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l50() #[[ATTR5:[0-9]+]] | ||||
| // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] | // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] | ||||
| // CHECK5: lpad: | // CHECK5: lpad: | ||||
| // CHECK5-NEXT: [[TMP11:%.*]] = landingpad { ptr, i32 } | // CHECK5-NEXT: [[TMP11:%.*]] = landingpad { ptr, i32 } | ||||
| // CHECK5-NEXT: cleanup | // CHECK5-NEXT: cleanup | ||||
| // CHECK5-NEXT: [[TMP12:%.*]] = extractvalue { ptr, i32 } [[TMP11]], 0 | // CHECK5-NEXT: [[TMP12:%.*]] = extractvalue { ptr, i32 } [[TMP11]], 0 | ||||
| // CHECK5-NEXT: store ptr [[TMP12]], ptr [[EXN_SLOT]], align 8 | // CHECK5-NEXT: store ptr [[TMP12]], ptr [[EXN_SLOT]], align 8 | ||||
| // CHECK5-NEXT: [[TMP13:%.*]] = extractvalue { ptr, i32 } [[TMP11]], 1 | // CHECK5-NEXT: [[TMP13:%.*]] = extractvalue { ptr, i32 } [[TMP11]], 1 | ||||
| // CHECK5-NEXT: store i32 [[TMP13]], ptr [[EHSELECTOR_SLOT]], align 4 | // CHECK5-NEXT: store i32 [[TMP13]], ptr [[EHSELECTOR_SLOT]], align 4 | ||||
| // CHECK5-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR6]] | // CHECK5-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR5]] | ||||
| // CHECK5-NEXT: br label [[EH_RESUME:%.*]] | // CHECK5-NEXT: br label [[EH_RESUME:%.*]] | ||||
| // CHECK5: omp_offload.cont: | // CHECK5: omp_offload.cont: | ||||
| // CHECK5-NEXT: [[TMP14:%.*]] = load i8, ptr [[A]], align 1 | // CHECK5-NEXT: [[TMP14:%.*]] = load i8, ptr [[A]], align 1 | ||||
| // CHECK5-NEXT: store i8 [[TMP14]], ptr [[A_CASTED]], align 1 | // CHECK5-NEXT: store i8 [[TMP14]], ptr [[A_CASTED]], align 1 | ||||
| // CHECK5-NEXT: [[TMP15:%.*]] = load i64, ptr [[A_CASTED]], align 8 | // CHECK5-NEXT: [[TMP15:%.*]] = load i64, ptr [[A_CASTED]], align 8 | ||||
| // CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 | // CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 | ||||
| // CHECK5-NEXT: store i64 [[TMP15]], ptr [[TMP16]], align 8 | // CHECK5-NEXT: store i64 [[TMP15]], ptr [[TMP16]], align 8 | ||||
| // CHECK5-NEXT: [[TMP17:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 | // CHECK5-NEXT: [[TMP17:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 | ||||
| Show All 24 Lines | |||||
| // CHECK5-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 7 | // CHECK5-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 7 | ||||
| // CHECK5-NEXT: store ptr null, ptr [[TMP31]], align 8 | // CHECK5-NEXT: store ptr null, ptr [[TMP31]], align 8 | ||||
| // CHECK5-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 8 | // CHECK5-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 8 | ||||
| // CHECK5-NEXT: store i64 100, ptr [[TMP32]], align 8 | // CHECK5-NEXT: store i64 100, ptr [[TMP32]], align 8 | ||||
| // CHECK5-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 [[TMP23]], ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55.region_id, ptr [[KERNEL_ARGS2]]) | // CHECK5-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 [[TMP23]], ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55.region_id, ptr [[KERNEL_ARGS2]]) | ||||
| // CHECK5-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0 | // CHECK5-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0 | ||||
| // CHECK5-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]] | // CHECK5-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]] | ||||
| // CHECK5: omp_offload.failed3: | // CHECK5: omp_offload.failed3: | ||||
| // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55(i64 [[TMP15]]) #[[ATTR6]] | // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55(i64 [[TMP15]]) #[[ATTR5]] | ||||
| // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT4]] | // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT4]] | ||||
| // CHECK5: omp_offload.cont4: | // CHECK5: omp_offload.cont4: | ||||
| // CHECK5-NEXT: [[TMP35:%.*]] = load i8, ptr [[A]], align 1 | // CHECK5-NEXT: [[TMP35:%.*]] = load i8, ptr [[A]], align 1 | ||||
| // CHECK5-NEXT: [[CONV:%.*]] = sext i8 [[TMP35]] to i32 | // CHECK5-NEXT: [[CONV:%.*]] = sext i8 [[TMP35]] to i32 | ||||
| // CHECK5-NEXT: [[CALL6:%.*]] = invoke noundef signext i32 @_Z5tmainIcLi5EEiv() | // CHECK5-NEXT: [[CALL6:%.*]] = invoke noundef signext i32 @_Z5tmainIcLi5EEiv() | ||||
| // CHECK5-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[LPAD]] | // CHECK5-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[LPAD]] | ||||
| // CHECK5: invoke.cont5: | // CHECK5: invoke.cont5: | ||||
| // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], [[CALL6]] | // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], [[CALL6]] | ||||
| // CHECK5-NEXT: [[CALL8:%.*]] = invoke noundef signext i32 @_Z5tmainI1SLi1EEiv() | // CHECK5-NEXT: [[CALL8:%.*]] = invoke noundef signext i32 @_Z5tmainI1SLi1EEiv() | ||||
| // CHECK5-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD]] | // CHECK5-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD]] | ||||
| // CHECK5: invoke.cont7: | // CHECK5: invoke.cont7: | ||||
| // CHECK5-NEXT: [[ADD9:%.*]] = add nsw i32 [[ADD]], [[CALL8]] | // CHECK5-NEXT: [[ADD9:%.*]] = add nsw i32 [[ADD]], [[CALL8]] | ||||
| // CHECK5-NEXT: store i32 [[ADD9]], ptr [[RETVAL]], align 4 | // CHECK5-NEXT: store i32 [[ADD9]], ptr [[RETVAL]], align 4 | ||||
| // CHECK5-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR6]] | // CHECK5-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR5]] | ||||
| // CHECK5-NEXT: [[TMP36:%.*]] = load i32, ptr [[RETVAL]], align 4 | // CHECK5-NEXT: [[TMP36:%.*]] = load i32, ptr [[RETVAL]], align 4 | ||||
| // CHECK5-NEXT: ret i32 [[TMP36]] | // CHECK5-NEXT: ret i32 [[TMP36]] | ||||
| // CHECK5: eh.resume: | // CHECK5: eh.resume: | ||||
| // CHECK5-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8 | // CHECK5-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8 | ||||
| // CHECK5-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4 | // CHECK5-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4 | ||||
| // CHECK5-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0 | // CHECK5-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0 | ||||
| // CHECK5-NEXT: [[LPAD_VAL10:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1 | // CHECK5-NEXT: [[LPAD_VAL10:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1 | ||||
| // CHECK5-NEXT: resume { ptr, i32 } [[LPAD_VAL10]] | // CHECK5-NEXT: resume { ptr, i32 } [[LPAD_VAL10]] | ||||
| ▲ Show 20 Lines • Show All 149 Lines • ▼ Show 20 Lines | |||||
| // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP13]] | // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP13]] | ||||
| // CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] | // CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] | ||||
| // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | ||||
| // CHECK5: omp.inner.for.body: | // CHECK5: omp.inner.for.body: | ||||
| // CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]] | // CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]] | ||||
| // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 | // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 | ||||
| // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | ||||
| // CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP13]] | // CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP13]] | ||||
| // CHECK5-NEXT: invoke void @_Z3foov() | // CHECK5-NEXT: call unwindabort void @_Z3foov(), !llvm.access.group [[ACC_GRP13]] | ||||
| // CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP13]] | |||||
| // CHECK5: invoke.cont: | |||||
| // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | ||||
| // CHECK5: omp.body.continue: | // CHECK5: omp.body.continue: | ||||
| // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | ||||
| // CHECK5: omp.inner.for.inc: | // CHECK5: omp.inner.for.inc: | ||||
| // CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]] | // CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]] | ||||
| // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 | // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 | ||||
| // CHECK5-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]] | // CHECK5-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]] | ||||
| // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] | // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] | ||||
| // CHECK5: omp.inner.for.end: | // CHECK5: omp.inner.for.end: | ||||
| // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | ||||
| // CHECK5: omp.loop.exit: | // CHECK5: omp.loop.exit: | ||||
| // CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) | // CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) | ||||
| // CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 | // CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 | ||||
| // CHECK5-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 | // CHECK5-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 | ||||
| // CHECK5-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] | // CHECK5-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] | ||||
| // CHECK5: .omp.final.then: | // CHECK5: .omp.final.then: | ||||
| // CHECK5-NEXT: store i32 100, ptr [[I]], align 4 | // CHECK5-NEXT: store i32 100, ptr [[I]], align 4 | ||||
| // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]] | // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]] | ||||
| // CHECK5: .omp.final.done: | // CHECK5: .omp.final.done: | ||||
| // CHECK5-NEXT: ret void | // CHECK5-NEXT: ret void | ||||
| // CHECK5: terminate.lpad: | |||||
| // CHECK5-NEXT: [[TMP13:%.*]] = landingpad { ptr, i32 } | |||||
| // CHECK5-NEXT: catch ptr null | |||||
| // CHECK5-NEXT: [[TMP14:%.*]] = extractvalue { ptr, i32 } [[TMP13]], 0 | |||||
| // CHECK5-NEXT: call void @__clang_call_terminate(ptr [[TMP14]]) #[[ATTR9:[0-9]+]], !llvm.access.group [[ACC_GRP13]] | |||||
| // CHECK5-NEXT: unreachable | |||||
| // | |||||
| // | |||||
| // CHECK5-LABEL: define {{[^@]+}}@__clang_call_terminate | |||||
| // CHECK5-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR5:[0-9]+]] comdat { | |||||
| // CHECK5-NEXT: [[TMP2:%.*]] = call ptr @__cxa_begin_catch(ptr [[TMP0]]) #[[ATTR6]] | |||||
| // CHECK5-NEXT: call void @_ZSt9terminatev() #[[ATTR9]] | |||||
| // CHECK5-NEXT: unreachable | |||||
| // | // | ||||
| // | // | ||||
| // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55 | // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55 | ||||
| // CHECK5-SAME: (i64 noundef [[A:%.*]]) #[[ATTR3]] { | // CHECK5-SAME: (i64 noundef [[A:%.*]]) #[[ATTR3]] { | ||||
| // CHECK5-NEXT: entry: | // CHECK5-NEXT: entry: | ||||
| // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 | // CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 | ||||
| // CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 | // CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 | ||||
| ▲ Show 20 Lines • Show All 129 Lines • ▼ Show 20 Lines | |||||
| // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP21]] | // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP21]] | ||||
| // CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] | // CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] | ||||
| // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | ||||
| // CHECK5: omp.inner.for.body: | // CHECK5: omp.inner.for.body: | ||||
| // CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]] | // CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]] | ||||
| // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 | // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 | ||||
| // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | ||||
| // CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP21]] | // CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP21]] | ||||
| // CHECK5-NEXT: invoke void @_Z3foov() | // CHECK5-NEXT: call unwindabort void @_Z3foov(), !llvm.access.group [[ACC_GRP21]] | ||||
| // CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP21]] | |||||
| // CHECK5: invoke.cont: | |||||
| // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | ||||
| // CHECK5: omp.body.continue: | // CHECK5: omp.body.continue: | ||||
| // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | ||||
| // CHECK5: omp.inner.for.inc: | // CHECK5: omp.inner.for.inc: | ||||
| // CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]] | // CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]] | ||||
| // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 | // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 | ||||
| // CHECK5-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]] | // CHECK5-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]] | ||||
| // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] | // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] | ||||
| // CHECK5: omp.inner.for.end: | // CHECK5: omp.inner.for.end: | ||||
| // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | ||||
| // CHECK5: omp.loop.exit: | // CHECK5: omp.loop.exit: | ||||
| // CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) | // CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) | ||||
| // CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 | // CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 | ||||
| // CHECK5-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 | // CHECK5-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 | ||||
| // CHECK5-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] | // CHECK5-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] | ||||
| // CHECK5: .omp.final.then: | // CHECK5: .omp.final.then: | ||||
| // CHECK5-NEXT: store i32 100, ptr [[I]], align 4 | // CHECK5-NEXT: store i32 100, ptr [[I]], align 4 | ||||
| // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]] | // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]] | ||||
| // CHECK5: .omp.final.done: | // CHECK5: .omp.final.done: | ||||
| // CHECK5-NEXT: ret void | // CHECK5-NEXT: ret void | ||||
| // CHECK5: terminate.lpad: | |||||
| // CHECK5-NEXT: [[TMP13:%.*]] = landingpad { ptr, i32 } | |||||
| // CHECK5-NEXT: catch ptr null | |||||
| // CHECK5-NEXT: [[TMP14:%.*]] = extractvalue { ptr, i32 } [[TMP13]], 0 | |||||
| // CHECK5-NEXT: call void @__clang_call_terminate(ptr [[TMP14]]) #[[ATTR9]], !llvm.access.group [[ACC_GRP21]] | |||||
| // CHECK5-NEXT: unreachable | |||||
| // | // | ||||
| // | // | ||||
| // CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIcLi5EEiv | // CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIcLi5EEiv | ||||
| // CHECK5-SAME: () #[[ATTR2]] comdat { | // CHECK5-SAME: () #[[ATTR2]] comdat { | ||||
| // CHECK5-NEXT: entry: | // CHECK5-NEXT: entry: | ||||
| // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 | // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 | ||||
| // CHECK5-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 | // CHECK5-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 | ||||
| // CHECK5-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 | // CHECK5-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 | ||||
| Show All 14 Lines | |||||
| // CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 | // CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 | ||||
| // CHECK5-NEXT: store ptr null, ptr [[TMP7]], align 8 | // CHECK5-NEXT: store ptr null, ptr [[TMP7]], align 8 | ||||
| // CHECK5-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 | // CHECK5-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 | ||||
| // CHECK5-NEXT: store i64 100, ptr [[TMP8]], align 8 | // CHECK5-NEXT: store i64 100, ptr [[TMP8]], align 8 | ||||
| // CHECK5-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 5, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l36.region_id, ptr [[KERNEL_ARGS]]) | // CHECK5-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 5, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l36.region_id, ptr [[KERNEL_ARGS]]) | ||||
| // CHECK5-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 | // CHECK5-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 | ||||
| // CHECK5-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] | // CHECK5-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] | ||||
| // CHECK5: omp_offload.failed: | // CHECK5: omp_offload.failed: | ||||
| // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l36() #[[ATTR6]] | // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l36() #[[ATTR5]] | ||||
| // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] | // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] | ||||
| // CHECK5: omp_offload.cont: | // CHECK5: omp_offload.cont: | ||||
| // CHECK5-NEXT: [[KERNEL_ARGS2:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 | // CHECK5-NEXT: [[KERNEL_ARGS2:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 | ||||
| // CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 0 | // CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 0 | ||||
| // CHECK5-NEXT: store i32 1, ptr [[TMP11]], align 4 | // CHECK5-NEXT: store i32 1, ptr [[TMP11]], align 4 | ||||
| // CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 1 | // CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 1 | ||||
| // CHECK5-NEXT: store i32 0, ptr [[TMP12]], align 4 | // CHECK5-NEXT: store i32 0, ptr [[TMP12]], align 4 | ||||
| // CHECK5-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 2 | // CHECK5-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 2 | ||||
| Show All 9 Lines | |||||
| // CHECK5-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 7 | // CHECK5-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 7 | ||||
| // CHECK5-NEXT: store ptr null, ptr [[TMP18]], align 8 | // CHECK5-NEXT: store ptr null, ptr [[TMP18]], align 8 | ||||
| // CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 8 | // CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 8 | ||||
| // CHECK5-NEXT: store i64 100, ptr [[TMP19]], align 8 | // CHECK5-NEXT: store i64 100, ptr [[TMP19]], align 8 | ||||
| // CHECK5-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 23, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l40.region_id, ptr [[KERNEL_ARGS2]]) | // CHECK5-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 23, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l40.region_id, ptr [[KERNEL_ARGS2]]) | ||||
| // CHECK5-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 | // CHECK5-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 | ||||
| // CHECK5-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]] | // CHECK5-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]] | ||||
| // CHECK5: omp_offload.failed3: | // CHECK5: omp_offload.failed3: | ||||
| // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l40() #[[ATTR6]] | // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l40() #[[ATTR5]] | ||||
| // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT4]] | // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT4]] | ||||
| // CHECK5: omp_offload.cont4: | // CHECK5: omp_offload.cont4: | ||||
| // CHECK5-NEXT: ret i32 0 | // CHECK5-NEXT: ret i32 0 | ||||
| // | // | ||||
| // | // | ||||
| // CHECK5-LABEL: define {{[^@]+}}@_Z5tmainI1SLi1EEiv | // CHECK5-LABEL: define {{[^@]+}}@_Z5tmainI1SLi1EEiv | ||||
| // CHECK5-SAME: () #[[ATTR2]] comdat personality ptr @__gxx_personality_v0 { | // CHECK5-SAME: () #[[ATTR6:[0-9]+]] comdat personality ptr @__gxx_personality_v0 { | ||||
| // CHECK5-NEXT: entry: | // CHECK5-NEXT: entry: | ||||
| // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 | // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 | ||||
| // CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 | // CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 | ||||
| // CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[STRUCT_S:%.*]], align 8 | // CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[STRUCT_S:%.*]], align 8 | ||||
| // CHECK5-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 | // CHECK5-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 | ||||
| // CHECK5-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 | // CHECK5-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 | ||||
| // CHECK5-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 | // CHECK5-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 | ||||
| // CHECK5-NEXT: store i32 1, ptr [[TMP0]], align 4 | // CHECK5-NEXT: store i32 1, ptr [[TMP0]], align 4 | ||||
| Show All 12 Lines | |||||
| // CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 | // CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 | ||||
| // CHECK5-NEXT: store ptr null, ptr [[TMP7]], align 8 | // CHECK5-NEXT: store ptr null, ptr [[TMP7]], align 8 | ||||
| // CHECK5-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 | // CHECK5-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 | ||||
| // CHECK5-NEXT: store i64 100, ptr [[TMP8]], align 8 | // CHECK5-NEXT: store i64 100, ptr [[TMP8]], align 8 | ||||
| // CHECK5-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l36.region_id, ptr [[KERNEL_ARGS]]) | // CHECK5-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l36.region_id, ptr [[KERNEL_ARGS]]) | ||||
| // CHECK5-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 | // CHECK5-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 | ||||
| // CHECK5-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] | // CHECK5-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] | ||||
| // CHECK5: omp_offload.failed: | // CHECK5: omp_offload.failed: | ||||
| // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l36() #[[ATTR6]] | // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l36() #[[ATTR5]] | ||||
| // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] | // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] | ||||
| // CHECK5: omp_offload.cont: | // CHECK5: omp_offload.cont: | ||||
| // CHECK5-NEXT: invoke void @_ZN1SC1El(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]], i64 noundef 23) | // CHECK5-NEXT: call unwindabort void @_ZN1SC1El(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]], i64 noundef 23) | ||||
| // CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] | |||||
| // CHECK5: invoke.cont: | |||||
| // CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i8 @_ZN1ScvcEv(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) | // CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i8 @_ZN1ScvcEv(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) | ||||
| // CHECK5-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]] | // CHECK5-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR5]] | ||||
| // CHECK5-NEXT: store i8 [[CALL]], ptr [[DOTCAPTURE_EXPR_]], align 1 | // CHECK5-NEXT: store i8 [[CALL]], ptr [[DOTCAPTURE_EXPR_]], align 1 | ||||
| // CHECK5-NEXT: [[TMP11:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 | // CHECK5-NEXT: [[TMP11:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 | ||||
| // CHECK5-NEXT: [[TMP12:%.*]] = zext i8 [[TMP11]] to i32 | // CHECK5-NEXT: [[TMP12:%.*]] = zext i8 [[TMP11]] to i32 | ||||
| // CHECK5-NEXT: [[KERNEL_ARGS2:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 | // CHECK5-NEXT: [[KERNEL_ARGS2:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 | ||||
| // CHECK5-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 0 | // CHECK5-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 0 | ||||
| // CHECK5-NEXT: store i32 1, ptr [[TMP13]], align 4 | // CHECK5-NEXT: store i32 1, ptr [[TMP13]], align 4 | ||||
| // CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 1 | // CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 1 | ||||
| // CHECK5-NEXT: store i32 0, ptr [[TMP14]], align 4 | // CHECK5-NEXT: store i32 0, ptr [[TMP14]], align 4 | ||||
| Show All 10 Lines | |||||
| // CHECK5-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 7 | // CHECK5-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 7 | ||||
| // CHECK5-NEXT: store ptr null, ptr [[TMP20]], align 8 | // CHECK5-NEXT: store ptr null, ptr [[TMP20]], align 8 | ||||
| // CHECK5-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 8 | // CHECK5-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 8 | ||||
| // CHECK5-NEXT: store i64 100, ptr [[TMP21]], align 8 | // CHECK5-NEXT: store i64 100, ptr [[TMP21]], align 8 | ||||
| // CHECK5-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 [[TMP12]], ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l40.region_id, ptr [[KERNEL_ARGS2]]) | // CHECK5-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 [[TMP12]], ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l40.region_id, ptr [[KERNEL_ARGS2]]) | ||||
| // CHECK5-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 | // CHECK5-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 | ||||
| // CHECK5-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]] | // CHECK5-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]] | ||||
| // CHECK5: omp_offload.failed3: | // CHECK5: omp_offload.failed3: | ||||
| // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l40() #[[ATTR6]] | // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l40() #[[ATTR5]] | ||||
| // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT4]] | // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT4]] | ||||
| // CHECK5: omp_offload.cont4: | // CHECK5: omp_offload.cont4: | ||||
| // CHECK5-NEXT: ret i32 0 | // CHECK5-NEXT: ret i32 0 | ||||
| // CHECK5: terminate.lpad: | |||||
| // CHECK5-NEXT: [[TMP24:%.*]] = landingpad { ptr, i32 } | |||||
| // CHECK5-NEXT: catch ptr null | |||||
| // CHECK5-NEXT: [[TMP25:%.*]] = extractvalue { ptr, i32 } [[TMP24]], 0 | |||||
| // CHECK5-NEXT: call void @__clang_call_terminate(ptr [[TMP25]]) #[[ATTR9]] | |||||
| // CHECK5-NEXT: unreachable | |||||
| // | // | ||||
| // | // | ||||
| // CHECK5-LABEL: define {{[^@]+}}@_ZN1SD1Ev | // CHECK5-LABEL: define {{[^@]+}}@_ZN1SD1Ev | ||||
| // CHECK5-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR7:[0-9]+]] comdat align 2 { | // CHECK5-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR7:[0-9]+]] comdat align 2 { | ||||
| // CHECK5-NEXT: entry: | // CHECK5-NEXT: entry: | ||||
| // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 | // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 | ||||
| // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 | // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 | ||||
| // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 | // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 | ||||
| // CHECK5-NEXT: call void @_ZN1SD2Ev(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR6]] | // CHECK5-NEXT: call void @_ZN1SD2Ev(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR5]] | ||||
| // CHECK5-NEXT: ret void | // CHECK5-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK5-LABEL: define {{[^@]+}}@_ZN1SC2El | // CHECK5-LABEL: define {{[^@]+}}@_ZN1SC2El | ||||
| // CHECK5-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR7]] comdat align 2 { | // CHECK5-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR7]] comdat align 2 { | ||||
| // CHECK5-NEXT: entry: | // CHECK5-NEXT: entry: | ||||
| // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 | // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 | ||||
| // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | ||||
| ▲ Show 20 Lines • Show All 131 Lines • ▼ Show 20 Lines | |||||
| // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP27]] | // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP27]] | ||||
| // CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] | // CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] | ||||
| // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | ||||
| // CHECK5: omp.inner.for.body: | // CHECK5: omp.inner.for.body: | ||||
| // CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]] | // CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]] | ||||
| // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 | // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 | ||||
| // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | ||||
| // CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP27]] | // CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP27]] | ||||
| // CHECK5-NEXT: invoke void @_Z3foov() | // CHECK5-NEXT: call unwindabort void @_Z3foov(), !llvm.access.group [[ACC_GRP27]] | ||||
| // CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP27]] | |||||
| // CHECK5: invoke.cont: | |||||
| // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | ||||
| // CHECK5: omp.body.continue: | // CHECK5: omp.body.continue: | ||||
| // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | ||||
| // CHECK5: omp.inner.for.inc: | // CHECK5: omp.inner.for.inc: | ||||
| // CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]] | // CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]] | ||||
| // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 | // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 | ||||
| // CHECK5-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]] | // CHECK5-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]] | ||||
| // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]] | // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]] | ||||
| // CHECK5: omp.inner.for.end: | // CHECK5: omp.inner.for.end: | ||||
| // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | ||||
| // CHECK5: omp.loop.exit: | // CHECK5: omp.loop.exit: | ||||
| // CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) | // CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) | ||||
| // CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 | // CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 | ||||
| // CHECK5-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 | // CHECK5-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 | ||||
| // CHECK5-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] | // CHECK5-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] | ||||
| // CHECK5: .omp.final.then: | // CHECK5: .omp.final.then: | ||||
| // CHECK5-NEXT: store i32 100, ptr [[I]], align 4 | // CHECK5-NEXT: store i32 100, ptr [[I]], align 4 | ||||
| // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]] | // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]] | ||||
| // CHECK5: .omp.final.done: | // CHECK5: .omp.final.done: | ||||
| // CHECK5-NEXT: ret void | // CHECK5-NEXT: ret void | ||||
| // CHECK5: terminate.lpad: | |||||
| // CHECK5-NEXT: [[TMP13:%.*]] = landingpad { ptr, i32 } | |||||
| // CHECK5-NEXT: catch ptr null | |||||
| // CHECK5-NEXT: [[TMP14:%.*]] = extractvalue { ptr, i32 } [[TMP13]], 0 | |||||
| // CHECK5-NEXT: call void @__clang_call_terminate(ptr [[TMP14]]) #[[ATTR9]], !llvm.access.group [[ACC_GRP27]] | |||||
| // CHECK5-NEXT: unreachable | |||||
| // | // | ||||
| // | // | ||||
| // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l40 | // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l40 | ||||
| // CHECK5-SAME: () #[[ATTR3]] { | // CHECK5-SAME: () #[[ATTR3]] { | ||||
| // CHECK5-NEXT: entry: | // CHECK5-NEXT: entry: | ||||
| // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @.omp_outlined..6) | // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @.omp_outlined..6) | ||||
| // CHECK5-NEXT: ret void | // CHECK5-NEXT: ret void | ||||
| // | // | ||||
| ▲ Show 20 Lines • Show All 116 Lines • ▼ Show 20 Lines | |||||
| // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP33]] | // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP33]] | ||||
| // CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] | // CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] | ||||
| // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | ||||
| // CHECK5: omp.inner.for.body: | // CHECK5: omp.inner.for.body: | ||||
| // CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]] | // CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]] | ||||
| // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 | // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 | ||||
| // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | ||||
| // CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP33]] | // CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP33]] | ||||
| // CHECK5-NEXT: invoke void @_Z3foov() | // CHECK5-NEXT: call unwindabort void @_Z3foov(), !llvm.access.group [[ACC_GRP33]] | ||||
| // CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP33]] | |||||
| // CHECK5: invoke.cont: | |||||
| // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | ||||
| // CHECK5: omp.body.continue: | // CHECK5: omp.body.continue: | ||||
| // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | ||||
| // CHECK5: omp.inner.for.inc: | // CHECK5: omp.inner.for.inc: | ||||
| // CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]] | // CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]] | ||||
| // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 | // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 | ||||
| // CHECK5-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]] | // CHECK5-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]] | ||||
| // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]] | // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]] | ||||
| // CHECK5: omp.inner.for.end: | // CHECK5: omp.inner.for.end: | ||||
| // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | ||||
| // CHECK5: omp.loop.exit: | // CHECK5: omp.loop.exit: | ||||
| // CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) | // CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) | ||||
| // CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 | // CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 | ||||
| // CHECK5-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 | // CHECK5-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 | ||||
| // CHECK5-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] | // CHECK5-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] | ||||
| // CHECK5: .omp.final.then: | // CHECK5: .omp.final.then: | ||||
| // CHECK5-NEXT: store i32 100, ptr [[I]], align 4 | // CHECK5-NEXT: store i32 100, ptr [[I]], align 4 | ||||
| // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]] | // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]] | ||||
| // CHECK5: .omp.final.done: | // CHECK5: .omp.final.done: | ||||
| // CHECK5-NEXT: ret void | // CHECK5-NEXT: ret void | ||||
| // CHECK5: terminate.lpad: | |||||
| // CHECK5-NEXT: [[TMP13:%.*]] = landingpad { ptr, i32 } | |||||
| // CHECK5-NEXT: catch ptr null | |||||
| // CHECK5-NEXT: [[TMP14:%.*]] = extractvalue { ptr, i32 } [[TMP13]], 0 | |||||
| // CHECK5-NEXT: call void @__clang_call_terminate(ptr [[TMP14]]) #[[ATTR9]], !llvm.access.group [[ACC_GRP33]] | |||||
| // CHECK5-NEXT: unreachable | |||||
| // | // | ||||
| // | // | ||||
| // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l36 | // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l36 | ||||
| // CHECK5-SAME: () #[[ATTR3]] { | // CHECK5-SAME: () #[[ATTR3]] { | ||||
| // CHECK5-NEXT: entry: | // CHECK5-NEXT: entry: | ||||
| // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @.omp_outlined..8) | // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @.omp_outlined..8) | ||||
| // CHECK5-NEXT: ret void | // CHECK5-NEXT: ret void | ||||
| // | // | ||||
| ▲ Show 20 Lines • Show All 116 Lines • ▼ Show 20 Lines | |||||
| // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP39]] | // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP39]] | ||||
| // CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] | // CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] | ||||
| // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | ||||
| // CHECK5: omp.inner.for.body: | // CHECK5: omp.inner.for.body: | ||||
| // CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP39]] | // CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP39]] | ||||
| // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 | // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 | ||||
| // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | ||||
| // CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP39]] | // CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP39]] | ||||
| // CHECK5-NEXT: invoke void @_Z3foov() | // CHECK5-NEXT: call unwindabort void @_Z3foov(), !llvm.access.group [[ACC_GRP39]] | ||||
| // CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP39]] | |||||
| // CHECK5: invoke.cont: | |||||
| // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | ||||
| // CHECK5: omp.body.continue: | // CHECK5: omp.body.continue: | ||||
| // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | ||||
| // CHECK5: omp.inner.for.inc: | // CHECK5: omp.inner.for.inc: | ||||
| // CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP39]] | // CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP39]] | ||||
| // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 | // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 | ||||
| // CHECK5-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP39]] | // CHECK5-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP39]] | ||||
| // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP40:![0-9]+]] | // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP40:![0-9]+]] | ||||
| // CHECK5: omp.inner.for.end: | // CHECK5: omp.inner.for.end: | ||||
| // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | ||||
| // CHECK5: omp.loop.exit: | // CHECK5: omp.loop.exit: | ||||
| // CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) | // CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) | ||||
| // CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 | // CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 | ||||
| // CHECK5-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 | // CHECK5-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 | ||||
| // CHECK5-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] | // CHECK5-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] | ||||
| // CHECK5: .omp.final.then: | // CHECK5: .omp.final.then: | ||||
| // CHECK5-NEXT: store i32 100, ptr [[I]], align 4 | // CHECK5-NEXT: store i32 100, ptr [[I]], align 4 | ||||
| // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]] | // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]] | ||||
| // CHECK5: .omp.final.done: | // CHECK5: .omp.final.done: | ||||
| // CHECK5-NEXT: ret void | // CHECK5-NEXT: ret void | ||||
| // CHECK5: terminate.lpad: | |||||
| // CHECK5-NEXT: [[TMP13:%.*]] = landingpad { ptr, i32 } | |||||
| // CHECK5-NEXT: catch ptr null | |||||
| // CHECK5-NEXT: [[TMP14:%.*]] = extractvalue { ptr, i32 } [[TMP13]], 0 | |||||
| // CHECK5-NEXT: call void @__clang_call_terminate(ptr [[TMP14]]) #[[ATTR9]], !llvm.access.group [[ACC_GRP39]] | |||||
| // CHECK5-NEXT: unreachable | |||||
| // | // | ||||
| // | // | ||||
| // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l40 | // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l40 | ||||
| // CHECK5-SAME: () #[[ATTR3]] personality ptr @__gxx_personality_v0 { | // CHECK5-SAME: () #[[ATTR3]] personality ptr @__gxx_personality_v0 { | ||||
| // CHECK5-NEXT: entry: | // CHECK5-NEXT: entry: | ||||
| // CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 | // CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 | ||||
| // CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[STRUCT_S:%.*]], align 8 | // CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[STRUCT_S:%.*]], align 8 | ||||
| // CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 | // CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 | ||||
| // CHECK5-NEXT: invoke void @_ZN1SC1El(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]], i64 noundef 23) | // CHECK5-NEXT: call unwindabort void @_ZN1SC1El(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]], i64 noundef 23) | ||||
| // CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] | |||||
| // CHECK5: invoke.cont: | |||||
| // CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i8 @_ZN1ScvcEv(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) | // CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i8 @_ZN1ScvcEv(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) | ||||
| // CHECK5-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]] | // CHECK5-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR5]] | ||||
| // CHECK5-NEXT: store i8 [[CALL]], ptr [[DOTCAPTURE_EXPR_]], align 1 | // CHECK5-NEXT: store i8 [[CALL]], ptr [[DOTCAPTURE_EXPR_]], align 1 | ||||
| // CHECK5-NEXT: [[TMP0:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 | // CHECK5-NEXT: [[TMP0:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 | ||||
| // CHECK5-NEXT: store i8 [[TMP0]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 1 | // CHECK5-NEXT: store i8 [[TMP0]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 1 | ||||
| // CHECK5-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8 | // CHECK5-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8 | ||||
| // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 1, ptr @.omp_outlined..10, i64 [[TMP1]]) | // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 1, ptr @.omp_outlined..10, i64 [[TMP1]]) | ||||
| // CHECK5-NEXT: ret void | // CHECK5-NEXT: ret void | ||||
| // CHECK5: terminate.lpad: | |||||
| // CHECK5-NEXT: [[TMP2:%.*]] = landingpad { ptr, i32 } | |||||
| // CHECK5-NEXT: catch ptr null | |||||
| // CHECK5-NEXT: [[TMP3:%.*]] = extractvalue { ptr, i32 } [[TMP2]], 0 | |||||
| // CHECK5-NEXT: call void @__clang_call_terminate(ptr [[TMP3]]) #[[ATTR9]] | |||||
| // CHECK5-NEXT: unreachable | |||||
| // | // | ||||
| // | // | ||||
| // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..10 | // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..10 | ||||
| // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { | // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { | ||||
| // CHECK5-NEXT: entry: | // CHECK5-NEXT: entry: | ||||
| // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 | // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 | ||||
| // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 | // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 | ||||
| // CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 | // CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 | ||||
| ▲ Show 20 Lines • Show All 113 Lines • ▼ Show 20 Lines | |||||
| // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP45]] | // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP45]] | ||||
| // CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] | // CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] | ||||
| // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | ||||
| // CHECK5: omp.inner.for.body: | // CHECK5: omp.inner.for.body: | ||||
| // CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45]] | // CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45]] | ||||
| // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 | // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 | ||||
| // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | ||||
| // CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP45]] | // CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP45]] | ||||
| // CHECK5-NEXT: invoke void @_Z3foov() | // CHECK5-NEXT: call unwindabort void @_Z3foov(), !llvm.access.group [[ACC_GRP45]] | ||||
| // CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP45]] | |||||
| // CHECK5: invoke.cont: | |||||
| // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | ||||
| // CHECK5: omp.body.continue: | // CHECK5: omp.body.continue: | ||||
| // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | ||||
| // CHECK5: omp.inner.for.inc: | // CHECK5: omp.inner.for.inc: | ||||
| // CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45]] | // CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45]] | ||||
| // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 | // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 | ||||
| // CHECK5-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45]] | // CHECK5-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45]] | ||||
| // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP46:![0-9]+]] | // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP46:![0-9]+]] | ||||
| // CHECK5: omp.inner.for.end: | // CHECK5: omp.inner.for.end: | ||||
| // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | ||||
| // CHECK5: omp.loop.exit: | // CHECK5: omp.loop.exit: | ||||
| // CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) | // CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) | ||||
| // CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 | // CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 | ||||
| // CHECK5-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 | // CHECK5-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 | ||||
| // CHECK5-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] | // CHECK5-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] | ||||
| // CHECK5: .omp.final.then: | // CHECK5: .omp.final.then: | ||||
| // CHECK5-NEXT: store i32 100, ptr [[I]], align 4 | // CHECK5-NEXT: store i32 100, ptr [[I]], align 4 | ||||
| // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]] | // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]] | ||||
| // CHECK5: .omp.final.done: | // CHECK5: .omp.final.done: | ||||
| // CHECK5-NEXT: ret void | // CHECK5-NEXT: ret void | ||||
| // CHECK5: terminate.lpad: | |||||
| // CHECK5-NEXT: [[TMP13:%.*]] = landingpad { ptr, i32 } | |||||
| // CHECK5-NEXT: catch ptr null | |||||
| // CHECK5-NEXT: [[TMP14:%.*]] = extractvalue { ptr, i32 } [[TMP13]], 0 | |||||
| // CHECK5-NEXT: call void @__clang_call_terminate(ptr [[TMP14]]) #[[ATTR9]], !llvm.access.group [[ACC_GRP45]] | |||||
| // CHECK5-NEXT: unreachable | |||||
| // | // | ||||
| // | // | ||||
| // CHECK5-LABEL: define {{[^@]+}}@_ZN1SD2Ev | // CHECK5-LABEL: define {{[^@]+}}@_ZN1SD2Ev | ||||
| // CHECK5-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR7]] comdat align 2 { | // CHECK5-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR7]] comdat align 2 { | ||||
| // CHECK5-NEXT: entry: | // CHECK5-NEXT: entry: | ||||
| // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 | // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 | ||||
| // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 | // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 | ||||
| // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 | // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 | ||||
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