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Differential D141918 Diff 489761 clang/test/OpenMP/simd_codegen.cpp

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clang/test/OpenMP/simd_codegen.cpp

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// Init linear private var. // Init linear private var.
// CHECK: store i32 12, i32* [[LIN_VAR:%[^,]+]] // CHECK: store i32 12, i32* [[LIN_VAR:%[^,]+]]
// CHECK: store i64 0, i64* [[OMP_IV3:%[^,]+]] // CHECK: store i64 0, i64* [[OMP_IV3:%[^,]+]]
// CHECK: [[LIN_LOAD:%.+]] = load i32, i32* [[LIN_VAR]] // CHECK: [[LIN_LOAD:%.+]] = load i32, i32* [[LIN_VAR]]
// CHECK-NEXT: store i32 [[LIN_LOAD]], i32* [[LIN_START:%[^,]+]] // CHECK-NEXT: store i32 [[LIN_LOAD]], i32* [[LIN_START:%[^,]+]]
// Remember linear step. // Remember linear step.
// CHECK: [[CALL_VAL:%.+]] = invoke // CHECK: [[CALL_VAL:%.+]] = call unwindabort
// CHECK: store i64 [[CALL_VAL]], i64* [[LIN_STEP:%[^,]+]] // CHECK: store i64 [[CALL_VAL]], i64* [[LIN_STEP:%[^,]+]]
// CHECK: [[GLIN_LOAD:%.+]] = load double*, double** [[GLIN_VAR:@[^,]+]] // CHECK: [[GLIN_LOAD:%.+]] = load double*, double** [[GLIN_VAR:@[^,]+]]
// CHECK-NEXT: store double* [[GLIN_LOAD]], double** [[GLIN_START:%[^,]+]] // CHECK-NEXT: store double* [[GLIN_LOAD]], double** [[GLIN_START:%[^,]+]]
// CHECK: [[IV3:%.+]] = load i64, i64* [[OMP_IV3]]{{.*}}!llvm.access.group // CHECK: [[IV3:%.+]] = load i64, i64* [[OMP_IV3]]{{.*}}!llvm.access.group
// CHECK-NEXT: [[CMP3:%.+]] = icmp ult i64 [[IV3]], 4 // CHECK-NEXT: [[CMP3:%.+]] = icmp ult i64 [[IV3]], 4
// CHECK-NEXT: br i1 [[CMP3]], label %[[SIMPLE_LOOP3_BODY:.+]], label %[[SIMPLE_LOOP3_END:[^,]+]] // CHECK-NEXT: br i1 [[CMP3]], label %[[SIMPLE_LOOP3_BODY:.+]], label %[[SIMPLE_LOOP3_END:[^,]+]]
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///~IterDouble() {} ///~IterDouble() {}
}; };
// CHECK-LABEL: define {{.*void}} @{{.*}}iter_simple{{.*}} // CHECK-LABEL: define {{.*void}} @{{.*}}iter_simple{{.*}}
void iter_simple(IterDouble ia, IterDouble ib, IterDouble ic) { void iter_simple(IterDouble ia, IterDouble ib, IterDouble ic) {
// //
// Calculate number of iterations before the loop body. // Calculate number of iterations before the loop body.
// CHECK: [[DIFF1:%.+]] = invoke {{.*}}i32 @{{.*}}IterDouble{{.*}} // CHECK: [[DIFF1:%.+]] = call unwindabort {{.*}}i32 @{{.*}}IterDouble{{.*}}
// CHECK: [[DIFF2:%.+]] = sub nsw i32 [[DIFF1]], 1 // CHECK: [[DIFF2:%.+]] = sub nsw i32 [[DIFF1]], 1
// CHECK-NEXT: [[DIFF3:%.+]] = add nsw i32 [[DIFF2]], 1 // CHECK-NEXT: [[DIFF3:%.+]] = add nsw i32 [[DIFF2]], 1
// CHECK-NEXT: [[DIFF4:%.+]] = sdiv i32 [[DIFF3]], 1 // CHECK-NEXT: [[DIFF4:%.+]] = sdiv i32 [[DIFF3]], 1
// CHECK-NEXT: [[DIFF5:%.+]] = sub nsw i32 [[DIFF4]], 1 // CHECK-NEXT: [[DIFF5:%.+]] = sub nsw i32 [[DIFF4]], 1
// CHECK-NEXT: store i32 [[DIFF5]], i32* [[OMP_LAST_IT:%[^,]+]]{{.+}} // CHECK-NEXT: store i32 [[DIFF5]], i32* [[OMP_LAST_IT:%[^,]+]]{{.+}}
// CHECK: store i32 0, i32* [[IT_OMP_IV:%[^,]+]] // CHECK: store i32 0, i32* [[IT_OMP_IV:%[^,]+]]
#pragma omp simd #pragma omp simd
// CHECK: [[IV:%.+]] = load i32, i32* [[IT_OMP_IV]]{{.+}} !llvm.access.group // CHECK: [[IV:%.+]] = load i32, i32* [[IT_OMP_IV]]{{.+}} !llvm.access.group
// CHECK-NEXT: [[LAST_IT:%.+]] = load i32, i32* [[OMP_LAST_IT]]{{.+}}!llvm.access.group // CHECK-NEXT: [[LAST_IT:%.+]] = load i32, i32* [[OMP_LAST_IT]]{{.+}}!llvm.access.group
// CHECK-NEXT: [[NUM_IT:%.+]] = add nsw i32 [[LAST_IT]], 1 // CHECK-NEXT: [[NUM_IT:%.+]] = add nsw i32 [[LAST_IT]], 1
// CHECK-NEXT: [[CMP:%.+]] = icmp slt i32 [[IV]], [[NUM_IT]] // CHECK-NEXT: [[CMP:%.+]] = icmp slt i32 [[IV]], [[NUM_IT]]
// CHECK-NEXT: br i1 [[CMP]], label %[[IT_BODY:[^,]+]], label %[[IT_END:[^,]+]] // CHECK-NEXT: br i1 [[CMP]], label %[[IT_BODY:[^,]+]], label %[[IT_END:[^,]+]]
for (IterDouble i = ia; i < ib; ++i) { for (IterDouble i = ia; i < ib; ++i) {
// CHECK: [[IT_BODY]]: // CHECK: [[IT_BODY]]:
// Start of body: calculate i from index: // Start of body: calculate i from index:
// CHECK: [[IV1:%.+]] = load i32, i32* [[IT_OMP_IV]]{{.+}}!llvm.access.group // CHECK: [[IV1:%.+]] = load i32, i32* [[IT_OMP_IV]]{{.+}}!llvm.access.group
// Call of operator+ (i, IV). // Call of operator+ (i, IV).
// CHECK: {{%.+}} = invoke {{.+}} @{{.*}}IterDouble{{.*}} // CHECK: {{%.+}} = call unwindabort {{.+}} @{{.*}}IterDouble{{.*}}
// ... loop body ... // ... loop body ...
*i = *ic * 0.5; *i = *ic * 0.5;
// Float multiply and save result. // Float multiply and save result.
// CHECK: [[MULR:%.+]] = fmul double {{%.+}}, 5.000000e-01 // CHECK: [[MULR:%.+]] = fmul double {{%.+}}, 5.000000e-01
// CHECK-NEXT: invoke {{.+}} @{{.*}}IterDouble{{.*}} // CHECK-NEXT: call unwindabort {{.+}} @{{.*}}IterDouble{{.*}}
// CHECK: store double [[MULR:%.+]], double* [[RESULT_ADDR:%.+]], !llvm.access.group // CHECK: store double [[MULR:%.+]], double* [[RESULT_ADDR:%.+]], !llvm.access.group
++ic; ++ic;
// //
// CHECK: [[IV2:%.+]] = load i32, i32* [[IT_OMP_IV]]{{.+}}!llvm.access.group // CHECK: [[IV2:%.+]] = load i32, i32* [[IT_OMP_IV]]{{.+}}!llvm.access.group
// CHECK-NEXT: [[ADD2:%.+]] = add nsw i32 [[IV2]], 1 // CHECK-NEXT: [[ADD2:%.+]] = add nsw i32 [[IV2]], 1
// CHECK-NEXT: store i32 [[ADD2]], i32* [[IT_OMP_IV]]{{.+}}!llvm.access.group // CHECK-NEXT: store i32 [[ADD2]], i32* [[IT_OMP_IV]]{{.+}}!llvm.access.group
// br label %{{.*}}, !llvm.loop ![[ITER_LOOP_ID]] // br label %{{.*}}, !llvm.loop ![[ITER_LOOP_ID]]
} }
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// TERM_DEBUG-LABEL: bar // TERM_DEBUG-LABEL: bar
int bar() { extern void mayThrow(); mayThrow(); return 0; }; int bar() { extern void mayThrow(); mayThrow(); return 0; };
// TERM_DEBUG-LABEL: parallel_simd // TERM_DEBUG-LABEL: parallel_simd
void parallel_simd(float *a) { void parallel_simd(float *a) {
#pragma omp parallel #pragma omp parallel
#pragma omp simd #pragma omp simd
// TERM_DEBUG-NOT: __kmpc_global_thread_num // TERM_DEBUG-NOT: __kmpc_global_thread_num
// TERM_DEBUG: invoke noundef i32 {{.*}}bar{{.*}}() // TERM_DEBUG: call unwindabort noundef i32 {{.*}}bar{{.*}}()
// TERM_DEBUG: unwind label %[[TERM_LPAD:[^,]+]],
// TERM_DEBUG-NOT: __kmpc_global_thread_num // TERM_DEBUG-NOT: __kmpc_global_thread_num
// TERM_DEBUG: [[TERM_LPAD]]
// TERM_DEBUG: call void @__clang_call_terminate
// TERM_DEBUG: unreachable
for (unsigned i = 131071; i <= 2147483647; i += 127) for (unsigned i = 131071; i <= 2147483647; i += 127)
a[i] += bar(); a[i] += bar();
} }
// TERM_DEBUG: !{{[0-9]+}} = !DILocation(line: [[@LINE-11]], // TERM_DEBUG: !{{[0-9]+}} = !DILocation(line: [[@LINE-7]],
// CHECK-LABEL: S8 // CHECK-LABEL: S8
// CHECK-DAG: call void @llvm.assume(i1 // CHECK-DAG: call void @llvm.assume(i1
// CHECK-DAG: call void @llvm.assume(i1 // CHECK-DAG: call void @llvm.assume(i1
// CHECK-DAG: call void @llvm.assume(i1 // CHECK-DAG: call void @llvm.assume(i1
// CHECK-DAG: call void @llvm.assume(i1 // CHECK-DAG: call void @llvm.assume(i1
struct SS { struct SS {
SS(): a(0) {} SS(): a(0) {}
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}; };
S8 s8(0); S8 s8(0);
// TERM_DEBUG-NOT: line: 0, // TERM_DEBUG-NOT: line: 0,
// TERM_DEBUG: distinct !DISubprogram(linkageName: "_GLOBAL__sub_I_simd_codegen.cpp", // TERM_DEBUG: distinct !DISubprogram(linkageName: "_GLOBAL__sub_I_simd_codegen.cpp",
// OMP50-DAG: ![[NOVECT:.+]] = !{!"llvm.loop.vectorize.enable", i1 false} // OMP50-DAG: ![[NOVECT:.+]] = !{!"llvm.loop.vectorize.enable", i1 false}
// OMP50-DAG: ![[DISABLE_VECT]] = distinct !{{.*}}![[NOVECT]]{{[,}]}} // OMP50-DAG: ![[DISABLE_VECT]] = distinct !{{.*}}![[NOVECT]]{{[,}]}}
#endif // HEADER #endif // HEADER