Please use GitHub pull requests for new patches. Avoid migrating existing patches. Phabricator shutdown timeline
Changeset View
Changeset View
Standalone View
Standalone View
clang/test/OpenMP/parallel_codegen.cpp
| Show First 20 Lines • Show All 108 Lines • ▼ Show 20 Lines | |||||
| // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 | // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 | ||||
| // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 | // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 | ||||
| // CHECK1-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 | // CHECK1-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 | ||||
| // CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 | // CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 | ||||
| // CHECK1-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 | // CHECK1-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 | ||||
| // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8 | // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8 | ||||
| // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 1 | // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 1 | ||||
| // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 | // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 | ||||
| // CHECK1-NEXT: invoke void @_Z3fooIiEvT_(i32 noundef [[TMP2]]) | // CHECK1-NEXT: call unwindabort void @_Z3fooIiEvT_(i32 noundef [[TMP2]]) | ||||
| // CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] | |||||
| // CHECK1: invoke.cont: | |||||
| // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr @global, align 4 | // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr @global, align 4 | ||||
| // CHECK1-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 1 | // CHECK1-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 1 | ||||
| // CHECK1-NEXT: store i32 [[TMP3]], ptr [[ARRAYIDX1]], align 4 | // CHECK1-NEXT: store i32 [[TMP3]], ptr [[ARRAYIDX1]], align 4 | ||||
| // CHECK1-NEXT: ret void | // CHECK1-NEXT: ret void | ||||
| // CHECK1: terminate.lpad: | |||||
| // CHECK1-NEXT: [[TMP4:%.*]] = landingpad { ptr, i32 } | |||||
| // CHECK1-NEXT: catch ptr null | |||||
| // CHECK1-NEXT: [[TMP5:%.*]] = extractvalue { ptr, i32 } [[TMP4]], 0 | |||||
| // CHECK1-NEXT: call void @__clang_call_terminate(ptr [[TMP5]]) #[[ATTR6:[0-9]+]] | |||||
| // CHECK1-NEXT: unreachable | |||||
| // | // | ||||
| // | // | ||||
| // CHECK1-LABEL: define {{[^@]+}}@_Z3fooIiEvT_ | // CHECK1-LABEL: define {{[^@]+}}@_Z3fooIiEvT_ | ||||
| // CHECK1-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR3:[0-9]+]] comdat { | // CHECK1-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR3:[0-9]+]] comdat { | ||||
| // CHECK1-NEXT: entry: | // CHECK1-NEXT: entry: | ||||
| // CHECK1-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 | // CHECK1-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK1-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 | // CHECK1-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 | ||||
| // CHECK1-NEXT: ret void | // CHECK1-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK1-LABEL: define {{[^@]+}}@__clang_call_terminate | |||||
| // CHECK1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR4:[0-9]+]] comdat { | |||||
| // CHECK1-NEXT: [[TMP2:%.*]] = call ptr @__cxa_begin_catch(ptr [[TMP0]]) #[[ATTR5:[0-9]+]] | |||||
| // CHECK1-NEXT: call void @_ZSt9terminatev() #[[ATTR6]] | |||||
| // CHECK1-NEXT: unreachable | |||||
| // | |||||
| // | |||||
| // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 | // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 | ||||
| // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]]) #[[ATTR2]] { | // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]]) #[[ATTR2]] { | ||||
| // CHECK1-NEXT: entry: | // CHECK1-NEXT: entry: | ||||
| // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 | // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 | ||||
| // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 | // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 | ||||
| // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 | // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK1-NEXT: [[GLOBAL:%.*]] = alloca i32, align 4 | // CHECK1-NEXT: [[GLOBAL:%.*]] = alloca i32, align 4 | ||||
| // CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 | // CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 | ||||
| Show All 25 Lines | |||||
| // CHECK1-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 | // CHECK1-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 | ||||
| // CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 | // CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 | ||||
| // CHECK1-NEXT: store ptr [[GLOBAL]], ptr [[GLOBAL_ADDR]], align 8 | // CHECK1-NEXT: store ptr [[GLOBAL]], ptr [[GLOBAL_ADDR]], align 8 | ||||
| // CHECK1-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 | // CHECK1-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 | ||||
| // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8 | // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8 | ||||
| // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[GLOBAL_ADDR]], align 8 | // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[GLOBAL_ADDR]], align 8 | ||||
| // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 1 | // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 1 | ||||
| // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 | // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 | ||||
| // CHECK1-NEXT: invoke void @_Z3fooIiEvT_(i32 noundef [[TMP3]]) | // CHECK1-NEXT: call unwindabort void @_Z3fooIiEvT_(i32 noundef [[TMP3]]) | ||||
| // CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] | |||||
| // CHECK1: invoke.cont: | |||||
| // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP2]], align 4 | // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP2]], align 4 | ||||
| // CHECK1-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 1 | // CHECK1-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 1 | ||||
| // CHECK1-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX1]], align 4 | // CHECK1-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX1]], align 4 | ||||
| // CHECK1-NEXT: ret void | // CHECK1-NEXT: ret void | ||||
| // CHECK1: terminate.lpad: | |||||
| // CHECK1-NEXT: [[TMP5:%.*]] = landingpad { ptr, i32 } | |||||
| // CHECK1-NEXT: catch ptr null | |||||
| // CHECK1-NEXT: [[TMP6:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 0 | |||||
| // CHECK1-NEXT: call void @__clang_call_terminate(ptr [[TMP6]]) #[[ATTR6]] | |||||
| // CHECK1-NEXT: unreachable | |||||
| // | // | ||||
| // | // | ||||
| // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 | // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 | ||||
| // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { | // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { | ||||
| // CHECK1-NEXT: entry: | // CHECK1-NEXT: entry: | ||||
| // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 | // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 | ||||
| // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 | // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 | ||||
| // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 | // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 | ||||
| Show All 18 Lines | |||||
| // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 | // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 | ||||
| // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 | // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 | ||||
| // CHECK1-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 | // CHECK1-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 | ||||
| // CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 | // CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 | ||||
| // CHECK1-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 | // CHECK1-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 | ||||
| // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8 | // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8 | ||||
| // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 1 | // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 1 | ||||
| // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 | // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 | ||||
| // CHECK1-NEXT: invoke void @_Z3fooIiEvT_(i32 noundef [[TMP2]]) | // CHECK1-NEXT: call unwindabort void @_Z3fooIiEvT_(i32 noundef [[TMP2]]) | ||||
| // CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] | |||||
| // CHECK1: invoke.cont: | |||||
| // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr @global, align 4 | // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr @global, align 4 | ||||
| // CHECK1-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 1 | // CHECK1-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 1 | ||||
| // CHECK1-NEXT: store i32 [[TMP3]], ptr [[ARRAYIDX1]], align 4 | // CHECK1-NEXT: store i32 [[TMP3]], ptr [[ARRAYIDX1]], align 4 | ||||
| // CHECK1-NEXT: ret void | // CHECK1-NEXT: ret void | ||||
| // CHECK1: terminate.lpad: | |||||
| // CHECK1-NEXT: [[TMP4:%.*]] = landingpad { ptr, i32 } | |||||
| // CHECK1-NEXT: catch ptr null | |||||
| // CHECK1-NEXT: [[TMP5:%.*]] = extractvalue { ptr, i32 } [[TMP4]], 0 | |||||
| // CHECK1-NEXT: call void @__clang_call_terminate(ptr [[TMP5]]) #[[ATTR6]] | |||||
| // CHECK1-NEXT: unreachable | |||||
| // | // | ||||
| // | // | ||||
| // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIPPcEiT_ | // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIPPcEiT_ | ||||
| // CHECK1-SAME: (ptr noundef [[ARGC:%.*]]) #[[ATTR3]] comdat { | // CHECK1-SAME: (ptr noundef [[ARGC:%.*]]) #[[ATTR3]] comdat { | ||||
| // CHECK1-NEXT: entry: | // CHECK1-NEXT: entry: | ||||
| // CHECK1-NEXT: [[ARGC_ADDR:%.*]] = alloca ptr, align 8 | // CHECK1-NEXT: [[ARGC_ADDR:%.*]] = alloca ptr, align 8 | ||||
| // CHECK1-NEXT: store ptr [[ARGC]], ptr [[ARGC_ADDR]], align 8 | // CHECK1-NEXT: store ptr [[ARGC]], ptr [[ARGC_ADDR]], align 8 | ||||
| // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARGC_ADDR]], align 8 | // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARGC_ADDR]], align 8 | ||||
| Show All 16 Lines | |||||
| // CHECK1-NEXT: [[VAR:%.*]] = alloca ptr, align 8 | // CHECK1-NEXT: [[VAR:%.*]] = alloca ptr, align 8 | ||||
| // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 | // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 | ||||
| // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 | // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 | ||||
| // CHECK1-NEXT: store ptr [[ARGC]], ptr [[ARGC_ADDR]], align 8 | // CHECK1-NEXT: store ptr [[ARGC]], ptr [[ARGC_ADDR]], align 8 | ||||
| // CHECK1-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 | // CHECK1-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 | ||||
| // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARGC_ADDR]], align 8 | // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARGC_ADDR]], align 8 | ||||
| // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 | // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 | ||||
| // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP0]], align 8 | // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP0]], align 8 | ||||
| // CHECK1-NEXT: invoke void @_Z3fooIPPcEvT_(ptr noundef [[TMP2]]) | // CHECK1-NEXT: call unwindabort void @_Z3fooIPPcEvT_(ptr noundef [[TMP2]]) | ||||
| // CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] | |||||
| // CHECK1: invoke.cont: | |||||
| // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR]], align 8 | // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR]], align 8 | ||||
| // CHECK1-NEXT: [[TMP4:%.*]] = mul nsw i64 0, [[TMP1]] | // CHECK1-NEXT: [[TMP4:%.*]] = mul nsw i64 0, [[TMP1]] | ||||
| // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, ptr [[TMP3]], i64 [[TMP4]] | // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, ptr [[TMP3]], i64 [[TMP4]] | ||||
| // CHECK1-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX]], i64 0 | // CHECK1-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX]], i64 0 | ||||
| // CHECK1-NEXT: ret void | // CHECK1-NEXT: ret void | ||||
| // CHECK1: terminate.lpad: | |||||
| // CHECK1-NEXT: [[TMP5:%.*]] = landingpad { ptr, i32 } | |||||
| // CHECK1-NEXT: catch ptr null | |||||
| // CHECK1-NEXT: [[TMP6:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 0 | |||||
| // CHECK1-NEXT: call void @__clang_call_terminate(ptr [[TMP6]]) #[[ATTR6]] | |||||
| // CHECK1-NEXT: unreachable | |||||
| // | // | ||||
| // | // | ||||
| // CHECK1-LABEL: define {{[^@]+}}@_Z3fooIPPcEvT_ | // CHECK1-LABEL: define {{[^@]+}}@_Z3fooIPPcEvT_ | ||||
| // CHECK1-SAME: (ptr noundef [[ARGC:%.*]]) #[[ATTR3]] comdat { | // CHECK1-SAME: (ptr noundef [[ARGC:%.*]]) #[[ATTR3]] comdat { | ||||
| // CHECK1-NEXT: entry: | // CHECK1-NEXT: entry: | ||||
| // CHECK1-NEXT: [[ARGC_ADDR:%.*]] = alloca ptr, align 8 | // CHECK1-NEXT: [[ARGC_ADDR:%.*]] = alloca ptr, align 8 | ||||
| // CHECK1-NEXT: store ptr [[ARGC]], ptr [[ARGC_ADDR]], align 8 | // CHECK1-NEXT: store ptr [[ARGC]], ptr [[ARGC_ADDR]], align 8 | ||||
| // CHECK1-NEXT: ret void | // CHECK1-NEXT: ret void | ||||
| ▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Lines | |||||
| // CHECK2-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 | // CHECK2-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 | ||||
| // CHECK2-NEXT: call void @llvm.dbg.declare(metadata ptr [[VLA_ADDR]], metadata [[META50:![0-9]+]], metadata !DIExpression()), !dbg [[DBG48]] | // CHECK2-NEXT: call void @llvm.dbg.declare(metadata ptr [[VLA_ADDR]], metadata [[META50:![0-9]+]], metadata !DIExpression()), !dbg [[DBG48]] | ||||
| // CHECK2-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 | // CHECK2-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 | ||||
| // CHECK2-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META51:![0-9]+]], metadata !DIExpression()), !dbg [[DBG52:![0-9]+]] | // CHECK2-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META51:![0-9]+]], metadata !DIExpression()), !dbg [[DBG52:![0-9]+]] | ||||
| // CHECK2-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8, !dbg [[DBG53:![0-9]+]] | // CHECK2-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8, !dbg [[DBG53:![0-9]+]] | ||||
| // CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG53]] | // CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG53]] | ||||
| // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 1, !dbg [[DBG54:![0-9]+]] | // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 1, !dbg [[DBG54:![0-9]+]] | ||||
| // CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !dbg [[DBG54]] | // CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !dbg [[DBG54]] | ||||
| // CHECK2-NEXT: invoke void @_Z3fooIiEvT_(i32 noundef [[TMP2]]) | // CHECK2-NEXT: call unwindabort void @_Z3fooIiEvT_(i32 noundef [[TMP2]]), !dbg [[DBG53]] | ||||
| // CHECK2-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !dbg [[DBG53]] | |||||
| // CHECK2: invoke.cont: | |||||
| // CHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr @global, align 4, !dbg [[DBG55:![0-9]+]] | // CHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr @global, align 4, !dbg [[DBG55:![0-9]+]] | ||||
| // CHECK2-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 1, !dbg [[DBG56:![0-9]+]] | // CHECK2-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 1, !dbg [[DBG56:![0-9]+]] | ||||
| // CHECK2-NEXT: store i32 [[TMP3]], ptr [[ARRAYIDX1]], align 4, !dbg [[DBG57:![0-9]+]] | // CHECK2-NEXT: store i32 [[TMP3]], ptr [[ARRAYIDX1]], align 4, !dbg [[DBG57:![0-9]+]] | ||||
| // CHECK2-NEXT: ret void, !dbg [[DBG55]] | // CHECK2-NEXT: ret void, !dbg [[DBG55]] | ||||
| // CHECK2: terminate.lpad: | |||||
| // CHECK2-NEXT: [[TMP4:%.*]] = landingpad { ptr, i32 } | |||||
| // CHECK2-NEXT: catch ptr null, !dbg [[DBG53]] | |||||
| // CHECK2-NEXT: [[TMP5:%.*]] = extractvalue { ptr, i32 } [[TMP4]], 0, !dbg [[DBG53]] | |||||
| // CHECK2-NEXT: call void @__clang_call_terminate(ptr [[TMP5]]) #[[ATTR7:[0-9]+]], !dbg [[DBG53]] | |||||
| // CHECK2-NEXT: unreachable, !dbg [[DBG53]] | |||||
| // | // | ||||
| // | // | ||||
| // CHECK2-LABEL: define {{[^@]+}}@_Z3fooIiEvT_ | // CHECK2-LABEL: define {{[^@]+}}@_Z3fooIiEvT_ | ||||
| // CHECK2-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat !dbg [[DBG58:![0-9]+]] { | // CHECK2-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR4:[0-9]+]] comdat !dbg [[DBG58:![0-9]+]] { | ||||
| // CHECK2-NEXT: entry: | // CHECK2-NEXT: entry: | ||||
| // CHECK2-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 | // CHECK2-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 | ||||
| // CHECK2-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 | // CHECK2-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 | ||||
| // CHECK2-NEXT: call void @llvm.dbg.declare(metadata ptr [[ARGC_ADDR]], metadata [[META63:![0-9]+]], metadata !DIExpression()), !dbg [[DBG64:![0-9]+]] | // CHECK2-NEXT: call void @llvm.dbg.declare(metadata ptr [[ARGC_ADDR]], metadata [[META63:![0-9]+]], metadata !DIExpression()), !dbg [[DBG64:![0-9]+]] | ||||
| // CHECK2-NEXT: ret void, !dbg [[DBG65:![0-9]+]] | // CHECK2-NEXT: ret void, !dbg [[DBG65:![0-9]+]] | ||||
| // | // | ||||
| // | // | ||||
| // CHECK2-LABEL: define {{[^@]+}}@__clang_call_terminate | |||||
| // CHECK2-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR5:[0-9]+]] comdat { | |||||
| // CHECK2-NEXT: [[TMP2:%.*]] = call ptr @__cxa_begin_catch(ptr [[TMP0]]) #[[ATTR6:[0-9]+]] | |||||
| // CHECK2-NEXT: call void @_ZSt9terminatev() #[[ATTR7]] | |||||
| // CHECK2-NEXT: unreachable | |||||
| // | |||||
| // | |||||
| // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. | // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. | ||||
| // CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR3]] !dbg [[DBG66:![0-9]+]] { | // CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR3]] !dbg [[DBG66:![0-9]+]] { | ||||
| // CHECK2-NEXT: entry: | // CHECK2-NEXT: entry: | ||||
| // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 | // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 | ||||
| // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 | // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 | ||||
| // CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 | // CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 | // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 | ||||
| // CHECK2-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 | // CHECK2-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 | ||||
| // CHECK2-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTGLOBAL_TID__ADDR]], metadata [[META67:![0-9]+]], metadata !DIExpression()), !dbg [[DBG68:![0-9]+]] | // CHECK2-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTGLOBAL_TID__ADDR]], metadata [[META67:![0-9]+]], metadata !DIExpression()), !dbg [[DBG68:![0-9]+]] | ||||
| // CHECK2-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 | // CHECK2-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 | ||||
| // CHECK2-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTBOUND_TID__ADDR]], metadata [[META69:![0-9]+]], metadata !DIExpression()), !dbg [[DBG68]] | // CHECK2-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTBOUND_TID__ADDR]], metadata [[META69:![0-9]+]], metadata !DIExpression()), !dbg [[DBG68]] | ||||
| // CHECK2-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 | // CHECK2-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 | ||||
| // CHECK2-NEXT: call void @llvm.dbg.declare(metadata ptr [[VLA_ADDR]], metadata [[META70:![0-9]+]], metadata !DIExpression()), !dbg [[DBG68]] | // CHECK2-NEXT: call void @llvm.dbg.declare(metadata ptr [[VLA_ADDR]], metadata [[META70:![0-9]+]], metadata !DIExpression()), !dbg [[DBG68]] | ||||
| // CHECK2-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 | // CHECK2-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 | ||||
| // CHECK2-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META71:![0-9]+]], metadata !DIExpression()), !dbg [[DBG68]] | // CHECK2-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META71:![0-9]+]], metadata !DIExpression()), !dbg [[DBG68]] | ||||
| // CHECK2-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8, !dbg [[DBG72:![0-9]+]] | // CHECK2-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8, !dbg [[DBG72:![0-9]+]] | ||||
| // CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG72]] | // CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG72]] | ||||
| // CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG72]] | // CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG72]] | ||||
| // CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTBOUND_TID__ADDR]], align 8, !dbg [[DBG72]] | // CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTBOUND_TID__ADDR]], align 8, !dbg [[DBG72]] | ||||
| // CHECK2-NEXT: [[TMP4:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG72]] | // CHECK2-NEXT: [[TMP4:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG72]] | ||||
| // CHECK2-NEXT: call void @.omp_outlined._debug__(ptr [[TMP2]], ptr [[TMP3]], i64 [[TMP0]], ptr [[TMP4]]) #[[ATTR6]], !dbg [[DBG72]] | // CHECK2-NEXT: call void @.omp_outlined._debug__(ptr [[TMP2]], ptr [[TMP3]], i64 [[TMP0]], ptr [[TMP4]]) #[[ATTR5:[0-9]+]], !dbg [[DBG72]] | ||||
| // CHECK2-NEXT: ret void, !dbg [[DBG72]] | // CHECK2-NEXT: ret void, !dbg [[DBG72]] | ||||
| // | // | ||||
| // | // | ||||
| // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined._debug__.1 | // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined._debug__.1 | ||||
| // CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]]) #[[ATTR3]] !dbg [[DBG75:![0-9]+]] { | // CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]]) #[[ATTR3]] !dbg [[DBG75:![0-9]+]] { | ||||
| // CHECK2-NEXT: entry: | // CHECK2-NEXT: entry: | ||||
| // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 | // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 | ||||
| // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 | // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 | ||||
| Show All 39 Lines | |||||
| // CHECK2-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META96:![0-9]+]], metadata !DIExpression()), !dbg [[DBG97:![0-9]+]] | // CHECK2-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META96:![0-9]+]], metadata !DIExpression()), !dbg [[DBG97:![0-9]+]] | ||||
| // CHECK2-NEXT: store ptr [[GLOBAL]], ptr [[GLOBAL_ADDR]], align 8 | // CHECK2-NEXT: store ptr [[GLOBAL]], ptr [[GLOBAL_ADDR]], align 8 | ||||
| // CHECK2-NEXT: call void @llvm.dbg.declare(metadata ptr [[GLOBAL_ADDR]], metadata [[META98:![0-9]+]], metadata !DIExpression()), !dbg [[DBG99:![0-9]+]] | // CHECK2-NEXT: call void @llvm.dbg.declare(metadata ptr [[GLOBAL_ADDR]], metadata [[META98:![0-9]+]], metadata !DIExpression()), !dbg [[DBG99:![0-9]+]] | ||||
| // CHECK2-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8, !dbg [[DBG100:![0-9]+]] | // CHECK2-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8, !dbg [[DBG100:![0-9]+]] | ||||
| // CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG100]] | // CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG100]] | ||||
| // CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[GLOBAL_ADDR]], align 8, !dbg [[DBG100]] | // CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[GLOBAL_ADDR]], align 8, !dbg [[DBG100]] | ||||
| // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 1, !dbg [[DBG101:![0-9]+]] | // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 1, !dbg [[DBG101:![0-9]+]] | ||||
| // CHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !dbg [[DBG101]] | // CHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !dbg [[DBG101]] | ||||
| // CHECK2-NEXT: invoke void @_Z3fooIiEvT_(i32 noundef [[TMP3]]) | // CHECK2-NEXT: call unwindabort void @_Z3fooIiEvT_(i32 noundef [[TMP3]]), !dbg [[DBG100]] | ||||
| // CHECK2-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !dbg [[DBG100]] | |||||
| // CHECK2: invoke.cont: | |||||
| // CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP2]], align 4, !dbg [[DBG102:![0-9]+]] | // CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP2]], align 4, !dbg [[DBG102:![0-9]+]] | ||||
| // CHECK2-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 1, !dbg [[DBG103:![0-9]+]] | // CHECK2-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 1, !dbg [[DBG103:![0-9]+]] | ||||
| // CHECK2-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX1]], align 4, !dbg [[DBG104:![0-9]+]] | // CHECK2-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX1]], align 4, !dbg [[DBG104:![0-9]+]] | ||||
| // CHECK2-NEXT: ret void, !dbg [[DBG102]] | // CHECK2-NEXT: ret void, !dbg [[DBG102]] | ||||
| // CHECK2: terminate.lpad: | |||||
| // CHECK2-NEXT: [[TMP5:%.*]] = landingpad { ptr, i32 } | |||||
| // CHECK2-NEXT: catch ptr null, !dbg [[DBG100]] | |||||
| // CHECK2-NEXT: [[TMP6:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 0, !dbg [[DBG100]] | |||||
| // CHECK2-NEXT: call void @__clang_call_terminate(ptr [[TMP6]]) #[[ATTR7]], !dbg [[DBG100]] | |||||
| // CHECK2-NEXT: unreachable, !dbg [[DBG100]] | |||||
| // | // | ||||
| // | // | ||||
| // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3 | // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3 | ||||
| // CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[GLOBAL:%.*]]) #[[ATTR3]] !dbg [[DBG105:![0-9]+]] { | // CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[GLOBAL:%.*]]) #[[ATTR3]] !dbg [[DBG105:![0-9]+]] { | ||||
| // CHECK2-NEXT: entry: | // CHECK2-NEXT: entry: | ||||
| // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 | // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 | ||||
| // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 | // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 | ||||
| // CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 | // CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 | ||||
| Show All 11 Lines | |||||
| // CHECK2-NEXT: call void @llvm.dbg.declare(metadata ptr [[GLOBAL_ADDR]], metadata [[META111:![0-9]+]], metadata !DIExpression()), !dbg [[DBG107]] | // CHECK2-NEXT: call void @llvm.dbg.declare(metadata ptr [[GLOBAL_ADDR]], metadata [[META111:![0-9]+]], metadata !DIExpression()), !dbg [[DBG107]] | ||||
| // CHECK2-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8, !dbg [[DBG112:![0-9]+]] | // CHECK2-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8, !dbg [[DBG112:![0-9]+]] | ||||
| // CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG112]] | // CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG112]] | ||||
| // CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[GLOBAL_ADDR]], align 8, !dbg [[DBG112]] | // CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[GLOBAL_ADDR]], align 8, !dbg [[DBG112]] | ||||
| // CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG112]] | // CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG112]] | ||||
| // CHECK2-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTBOUND_TID__ADDR]], align 8, !dbg [[DBG112]] | // CHECK2-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTBOUND_TID__ADDR]], align 8, !dbg [[DBG112]] | ||||
| // CHECK2-NEXT: [[TMP5:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG112]] | // CHECK2-NEXT: [[TMP5:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG112]] | ||||
| // CHECK2-NEXT: [[TMP6:%.*]] = load ptr, ptr [[GLOBAL_ADDR]], align 8, !dbg [[DBG112]] | // CHECK2-NEXT: [[TMP6:%.*]] = load ptr, ptr [[GLOBAL_ADDR]], align 8, !dbg [[DBG112]] | ||||
| // CHECK2-NEXT: call void @.omp_outlined._debug__.2(ptr [[TMP3]], ptr [[TMP4]], i64 [[TMP0]], ptr [[TMP5]], ptr [[TMP6]]) #[[ATTR6]], !dbg [[DBG112]] | // CHECK2-NEXT: call void @.omp_outlined._debug__.2(ptr [[TMP3]], ptr [[TMP4]], i64 [[TMP0]], ptr [[TMP5]], ptr [[TMP6]]) #[[ATTR5]], !dbg [[DBG112]] | ||||
| // CHECK2-NEXT: ret void, !dbg [[DBG112]] | // CHECK2-NEXT: ret void, !dbg [[DBG112]] | ||||
| // | // | ||||
| // | // | ||||
| // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4 | // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4 | ||||
| // CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]]) #[[ATTR3]] !dbg [[DBG113:![0-9]+]] { | // CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]]) #[[ATTR3]] !dbg [[DBG113:![0-9]+]] { | ||||
| // CHECK2-NEXT: entry: | // CHECK2-NEXT: entry: | ||||
| // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 | // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 | ||||
| // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 | // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 | ||||
| // CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 | // CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK2-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 | // CHECK2-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 | ||||
| // CHECK2-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTGLOBAL_TID__ADDR]], metadata [[META114:![0-9]+]], metadata !DIExpression()), !dbg [[DBG115:![0-9]+]] | // CHECK2-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTGLOBAL_TID__ADDR]], metadata [[META114:![0-9]+]], metadata !DIExpression()), !dbg [[DBG115:![0-9]+]] | ||||
| // CHECK2-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 | // CHECK2-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 | ||||
| // CHECK2-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTBOUND_TID__ADDR]], metadata [[META116:![0-9]+]], metadata !DIExpression()), !dbg [[DBG115]] | // CHECK2-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTBOUND_TID__ADDR]], metadata [[META116:![0-9]+]], metadata !DIExpression()), !dbg [[DBG115]] | ||||
| // CHECK2-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 | // CHECK2-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 | ||||
| // CHECK2-NEXT: call void @llvm.dbg.declare(metadata ptr [[VLA_ADDR]], metadata [[META117:![0-9]+]], metadata !DIExpression()), !dbg [[DBG115]] | // CHECK2-NEXT: call void @llvm.dbg.declare(metadata ptr [[VLA_ADDR]], metadata [[META117:![0-9]+]], metadata !DIExpression()), !dbg [[DBG115]] | ||||
| // CHECK2-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8, !dbg [[DBG118:![0-9]+]] | // CHECK2-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8, !dbg [[DBG118:![0-9]+]] | ||||
| // CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG118]] | // CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG118]] | ||||
| // CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTBOUND_TID__ADDR]], align 8, !dbg [[DBG118]] | // CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTBOUND_TID__ADDR]], align 8, !dbg [[DBG118]] | ||||
| // CHECK2-NEXT: call void @.omp_outlined._debug__.1(ptr [[TMP1]], ptr [[TMP2]], i64 [[TMP0]]) #[[ATTR6]], !dbg [[DBG118]] | // CHECK2-NEXT: call void @.omp_outlined._debug__.1(ptr [[TMP1]], ptr [[TMP2]], i64 [[TMP0]]) #[[ATTR5]], !dbg [[DBG118]] | ||||
| // CHECK2-NEXT: ret void, !dbg [[DBG118]] | // CHECK2-NEXT: ret void, !dbg [[DBG118]] | ||||
| // | // | ||||
| // | // | ||||
| // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined._debug__.5 | // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined._debug__.5 | ||||
| // CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR3]] !dbg [[DBG119:![0-9]+]] { | // CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR3]] !dbg [[DBG119:![0-9]+]] { | ||||
| // CHECK2-NEXT: entry: | // CHECK2-NEXT: entry: | ||||
| // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 | // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 | ||||
| // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 | // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 | ||||
| Show All 27 Lines | |||||
| // CHECK2-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 | // CHECK2-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 | ||||
| // CHECK2-NEXT: call void @llvm.dbg.declare(metadata ptr [[VLA_ADDR]], metadata [[META132:![0-9]+]], metadata !DIExpression()), !dbg [[DBG130]] | // CHECK2-NEXT: call void @llvm.dbg.declare(metadata ptr [[VLA_ADDR]], metadata [[META132:![0-9]+]], metadata !DIExpression()), !dbg [[DBG130]] | ||||
| // CHECK2-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 | // CHECK2-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 | ||||
| // CHECK2-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META133:![0-9]+]], metadata !DIExpression()), !dbg [[DBG134:![0-9]+]] | // CHECK2-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META133:![0-9]+]], metadata !DIExpression()), !dbg [[DBG134:![0-9]+]] | ||||
| // CHECK2-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8, !dbg [[DBG135:![0-9]+]] | // CHECK2-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8, !dbg [[DBG135:![0-9]+]] | ||||
| // CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG135]] | // CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG135]] | ||||
| // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 1, !dbg [[DBG136:![0-9]+]] | // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 1, !dbg [[DBG136:![0-9]+]] | ||||
| // CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !dbg [[DBG136]] | // CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !dbg [[DBG136]] | ||||
| // CHECK2-NEXT: invoke void @_Z3fooIiEvT_(i32 noundef [[TMP2]]) | // CHECK2-NEXT: call unwindabort void @_Z3fooIiEvT_(i32 noundef [[TMP2]]), !dbg [[DBG135]] | ||||
| // CHECK2-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !dbg [[DBG135]] | |||||
| // CHECK2: invoke.cont: | |||||
| // CHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr @global, align 4, !dbg [[DBG137:![0-9]+]] | // CHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr @global, align 4, !dbg [[DBG137:![0-9]+]] | ||||
| // CHECK2-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 1, !dbg [[DBG138:![0-9]+]] | // CHECK2-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 1, !dbg [[DBG138:![0-9]+]] | ||||
| // CHECK2-NEXT: store i32 [[TMP3]], ptr [[ARRAYIDX1]], align 4, !dbg [[DBG139:![0-9]+]] | // CHECK2-NEXT: store i32 [[TMP3]], ptr [[ARRAYIDX1]], align 4, !dbg [[DBG139:![0-9]+]] | ||||
| // CHECK2-NEXT: ret void, !dbg [[DBG137]] | // CHECK2-NEXT: ret void, !dbg [[DBG137]] | ||||
| // CHECK2: terminate.lpad: | |||||
| // CHECK2-NEXT: [[TMP4:%.*]] = landingpad { ptr, i32 } | |||||
| // CHECK2-NEXT: catch ptr null, !dbg [[DBG135]] | |||||
| // CHECK2-NEXT: [[TMP5:%.*]] = extractvalue { ptr, i32 } [[TMP4]], 0, !dbg [[DBG135]] | |||||
| // CHECK2-NEXT: call void @__clang_call_terminate(ptr [[TMP5]]) #[[ATTR7]], !dbg [[DBG135]] | |||||
| // CHECK2-NEXT: unreachable, !dbg [[DBG135]] | |||||
| // | // | ||||
| // | // | ||||
| // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..7 | // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..7 | ||||
| // CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR3]] !dbg [[DBG140:![0-9]+]] { | // CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR3]] !dbg [[DBG140:![0-9]+]] { | ||||
| // CHECK2-NEXT: entry: | // CHECK2-NEXT: entry: | ||||
| // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 | // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 | ||||
| // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 | // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 | ||||
| // CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 | // CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 | // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 | ||||
| // CHECK2-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 | // CHECK2-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 | ||||
| // CHECK2-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTGLOBAL_TID__ADDR]], metadata [[META141:![0-9]+]], metadata !DIExpression()), !dbg [[DBG142:![0-9]+]] | // CHECK2-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTGLOBAL_TID__ADDR]], metadata [[META141:![0-9]+]], metadata !DIExpression()), !dbg [[DBG142:![0-9]+]] | ||||
| // CHECK2-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 | // CHECK2-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 | ||||
| // CHECK2-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTBOUND_TID__ADDR]], metadata [[META143:![0-9]+]], metadata !DIExpression()), !dbg [[DBG142]] | // CHECK2-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTBOUND_TID__ADDR]], metadata [[META143:![0-9]+]], metadata !DIExpression()), !dbg [[DBG142]] | ||||
| // CHECK2-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 | // CHECK2-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 | ||||
| // CHECK2-NEXT: call void @llvm.dbg.declare(metadata ptr [[VLA_ADDR]], metadata [[META144:![0-9]+]], metadata !DIExpression()), !dbg [[DBG142]] | // CHECK2-NEXT: call void @llvm.dbg.declare(metadata ptr [[VLA_ADDR]], metadata [[META144:![0-9]+]], metadata !DIExpression()), !dbg [[DBG142]] | ||||
| // CHECK2-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 | // CHECK2-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 | ||||
| // CHECK2-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META145:![0-9]+]], metadata !DIExpression()), !dbg [[DBG142]] | // CHECK2-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META145:![0-9]+]], metadata !DIExpression()), !dbg [[DBG142]] | ||||
| // CHECK2-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8, !dbg [[DBG146:![0-9]+]] | // CHECK2-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8, !dbg [[DBG146:![0-9]+]] | ||||
| // CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG146]] | // CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG146]] | ||||
| // CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG146]] | // CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG146]] | ||||
| // CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTBOUND_TID__ADDR]], align 8, !dbg [[DBG146]] | // CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTBOUND_TID__ADDR]], align 8, !dbg [[DBG146]] | ||||
| // CHECK2-NEXT: [[TMP4:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG146]] | // CHECK2-NEXT: [[TMP4:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG146]] | ||||
| // CHECK2-NEXT: call void @.omp_outlined._debug__.6(ptr [[TMP2]], ptr [[TMP3]], i64 [[TMP0]], ptr [[TMP4]]) #[[ATTR6]], !dbg [[DBG146]] | // CHECK2-NEXT: call void @.omp_outlined._debug__.6(ptr [[TMP2]], ptr [[TMP3]], i64 [[TMP0]], ptr [[TMP4]]) #[[ATTR5]], !dbg [[DBG146]] | ||||
| // CHECK2-NEXT: ret void, !dbg [[DBG146]] | // CHECK2-NEXT: ret void, !dbg [[DBG146]] | ||||
| // | // | ||||
| // | // | ||||
| // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..8 | // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..8 | ||||
| // CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR3]] !dbg [[DBG147:![0-9]+]] { | // CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR3]] !dbg [[DBG147:![0-9]+]] { | ||||
| // CHECK2-NEXT: entry: | // CHECK2-NEXT: entry: | ||||
| // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 | // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 | ||||
| // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 | // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 | ||||
| // CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 | // CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 | // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 | ||||
| // CHECK2-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 | // CHECK2-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 | ||||
| // CHECK2-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTGLOBAL_TID__ADDR]], metadata [[META148:![0-9]+]], metadata !DIExpression()), !dbg [[DBG149:![0-9]+]] | // CHECK2-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTGLOBAL_TID__ADDR]], metadata [[META148:![0-9]+]], metadata !DIExpression()), !dbg [[DBG149:![0-9]+]] | ||||
| // CHECK2-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 | // CHECK2-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 | ||||
| // CHECK2-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTBOUND_TID__ADDR]], metadata [[META150:![0-9]+]], metadata !DIExpression()), !dbg [[DBG149]] | // CHECK2-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTBOUND_TID__ADDR]], metadata [[META150:![0-9]+]], metadata !DIExpression()), !dbg [[DBG149]] | ||||
| // CHECK2-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 | // CHECK2-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 | ||||
| // CHECK2-NEXT: call void @llvm.dbg.declare(metadata ptr [[VLA_ADDR]], metadata [[META151:![0-9]+]], metadata !DIExpression()), !dbg [[DBG149]] | // CHECK2-NEXT: call void @llvm.dbg.declare(metadata ptr [[VLA_ADDR]], metadata [[META151:![0-9]+]], metadata !DIExpression()), !dbg [[DBG149]] | ||||
| // CHECK2-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 | // CHECK2-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 | ||||
| // CHECK2-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META152:![0-9]+]], metadata !DIExpression()), !dbg [[DBG149]] | // CHECK2-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META152:![0-9]+]], metadata !DIExpression()), !dbg [[DBG149]] | ||||
| // CHECK2-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8, !dbg [[DBG153:![0-9]+]] | // CHECK2-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8, !dbg [[DBG153:![0-9]+]] | ||||
| // CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG153]] | // CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG153]] | ||||
| // CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG153]] | // CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG153]] | ||||
| // CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTBOUND_TID__ADDR]], align 8, !dbg [[DBG153]] | // CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTBOUND_TID__ADDR]], align 8, !dbg [[DBG153]] | ||||
| // CHECK2-NEXT: [[TMP4:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG153]] | // CHECK2-NEXT: [[TMP4:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG153]] | ||||
| // CHECK2-NEXT: call void @.omp_outlined._debug__.5(ptr [[TMP2]], ptr [[TMP3]], i64 [[TMP0]], ptr [[TMP4]]) #[[ATTR6]], !dbg [[DBG153]] | // CHECK2-NEXT: call void @.omp_outlined._debug__.5(ptr [[TMP2]], ptr [[TMP3]], i64 [[TMP0]], ptr [[TMP4]]) #[[ATTR5]], !dbg [[DBG153]] | ||||
| // CHECK2-NEXT: ret void, !dbg [[DBG153]] | // CHECK2-NEXT: ret void, !dbg [[DBG153]] | ||||
| // | // | ||||
| // | // | ||||
| // CHECK2-LABEL: define {{[^@]+}}@_Z5tmainIPPcEiT_ | // CHECK2-LABEL: define {{[^@]+}}@_Z5tmainIPPcEiT_ | ||||
| // CHECK2-SAME: (ptr noundef [[ARGC:%.*]]) #[[ATTR4]] comdat !dbg [[DBG154:![0-9]+]] { | // CHECK2-SAME: (ptr noundef [[ARGC:%.*]]) #[[ATTR4]] comdat !dbg [[DBG154:![0-9]+]] { | ||||
| // CHECK2-NEXT: entry: | // CHECK2-NEXT: entry: | ||||
| // CHECK2-NEXT: [[ARGC_ADDR:%.*]] = alloca ptr, align 8 | // CHECK2-NEXT: [[ARGC_ADDR:%.*]] = alloca ptr, align 8 | ||||
| // CHECK2-NEXT: store ptr [[ARGC]], ptr [[ARGC_ADDR]], align 8 | // CHECK2-NEXT: store ptr [[ARGC]], ptr [[ARGC_ADDR]], align 8 | ||||
| Show All 22 Lines | |||||
| // CHECK2-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTBOUND_TID__ADDR]], metadata [[META171:![0-9]+]], metadata !DIExpression()), !dbg [[DBG170]] | // CHECK2-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTBOUND_TID__ADDR]], metadata [[META171:![0-9]+]], metadata !DIExpression()), !dbg [[DBG170]] | ||||
| // CHECK2-NEXT: store ptr [[ARGC]], ptr [[ARGC_ADDR]], align 8 | // CHECK2-NEXT: store ptr [[ARGC]], ptr [[ARGC_ADDR]], align 8 | ||||
| // CHECK2-NEXT: call void @llvm.dbg.declare(metadata ptr [[ARGC_ADDR]], metadata [[META172:![0-9]+]], metadata !DIExpression()), !dbg [[DBG173:![0-9]+]] | // CHECK2-NEXT: call void @llvm.dbg.declare(metadata ptr [[ARGC_ADDR]], metadata [[META172:![0-9]+]], metadata !DIExpression()), !dbg [[DBG173:![0-9]+]] | ||||
| // CHECK2-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 | // CHECK2-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 | ||||
| // CHECK2-NEXT: call void @llvm.dbg.declare(metadata ptr [[VLA_ADDR]], metadata [[META174:![0-9]+]], metadata !DIExpression()), !dbg [[DBG170]] | // CHECK2-NEXT: call void @llvm.dbg.declare(metadata ptr [[VLA_ADDR]], metadata [[META174:![0-9]+]], metadata !DIExpression()), !dbg [[DBG170]] | ||||
| // CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARGC_ADDR]], align 8, !dbg [[DBG175:![0-9]+]] | // CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARGC_ADDR]], align 8, !dbg [[DBG175:![0-9]+]] | ||||
| // CHECK2-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8, !dbg [[DBG175]] | // CHECK2-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8, !dbg [[DBG175]] | ||||
| // CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP0]], align 8, !dbg [[DBG176:![0-9]+]] | // CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP0]], align 8, !dbg [[DBG176:![0-9]+]] | ||||
| // CHECK2-NEXT: invoke void @_Z3fooIPPcEvT_(ptr noundef [[TMP2]]) | // CHECK2-NEXT: call unwindabort void @_Z3fooIPPcEvT_(ptr noundef [[TMP2]]), !dbg [[DBG178:![0-9]+]] | ||||
| // CHECK2-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !dbg [[DBG178:![0-9]+]] | |||||
| // CHECK2: invoke.cont: | |||||
| // CHECK2-NEXT: call void @llvm.dbg.declare(metadata ptr [[VAR]], metadata [[META179:![0-9]+]], metadata !DIExpression()), !dbg [[DBG186:![0-9]+]] | // CHECK2-NEXT: call void @llvm.dbg.declare(metadata ptr [[VAR]], metadata [[META179:![0-9]+]], metadata !DIExpression()), !dbg [[DBG186:![0-9]+]] | ||||
| // CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR]], align 8, !dbg [[DBG187:![0-9]+]] | // CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR]], align 8, !dbg [[DBG187:![0-9]+]] | ||||
| // CHECK2-NEXT: [[TMP4:%.*]] = mul nsw i64 0, [[TMP1]], !dbg [[DBG187]] | // CHECK2-NEXT: [[TMP4:%.*]] = mul nsw i64 0, [[TMP1]], !dbg [[DBG187]] | ||||
| // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, ptr [[TMP3]], i64 [[TMP4]], !dbg [[DBG187]] | // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, ptr [[TMP3]], i64 [[TMP4]], !dbg [[DBG187]] | ||||
| // CHECK2-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX]], i64 0, !dbg [[DBG187]] | // CHECK2-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX]], i64 0, !dbg [[DBG187]] | ||||
| // CHECK2-NEXT: ret void, !dbg [[DBG188:![0-9]+]] | // CHECK2-NEXT: ret void, !dbg [[DBG188:![0-9]+]] | ||||
| // CHECK2: terminate.lpad: | |||||
| // CHECK2-NEXT: [[TMP5:%.*]] = landingpad { ptr, i32 } | |||||
| // CHECK2-NEXT: catch ptr null, !dbg [[DBG178]] | |||||
| // CHECK2-NEXT: [[TMP6:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 0, !dbg [[DBG178]] | |||||
| // CHECK2-NEXT: call void @__clang_call_terminate(ptr [[TMP6]]) #[[ATTR7]], !dbg [[DBG178]] | |||||
| // CHECK2-NEXT: unreachable, !dbg [[DBG178]] | |||||
| // | // | ||||
| // | // | ||||
| // CHECK2-LABEL: define {{[^@]+}}@_Z3fooIPPcEvT_ | // CHECK2-LABEL: define {{[^@]+}}@_Z3fooIPPcEvT_ | ||||
| // CHECK2-SAME: (ptr noundef [[ARGC:%.*]]) #[[ATTR4]] comdat !dbg [[DBG189:![0-9]+]] { | // CHECK2-SAME: (ptr noundef [[ARGC:%.*]]) #[[ATTR4]] comdat !dbg [[DBG189:![0-9]+]] { | ||||
| // CHECK2-NEXT: entry: | // CHECK2-NEXT: entry: | ||||
| // CHECK2-NEXT: [[ARGC_ADDR:%.*]] = alloca ptr, align 8 | // CHECK2-NEXT: [[ARGC_ADDR:%.*]] = alloca ptr, align 8 | ||||
| // CHECK2-NEXT: store ptr [[ARGC]], ptr [[ARGC_ADDR]], align 8 | // CHECK2-NEXT: store ptr [[ARGC]], ptr [[ARGC_ADDR]], align 8 | ||||
| // CHECK2-NEXT: call void @llvm.dbg.declare(metadata ptr [[ARGC_ADDR]], metadata [[META192:![0-9]+]], metadata !DIExpression()), !dbg [[DBG193:![0-9]+]] | // CHECK2-NEXT: call void @llvm.dbg.declare(metadata ptr [[ARGC_ADDR]], metadata [[META192:![0-9]+]], metadata !DIExpression()), !dbg [[DBG193:![0-9]+]] | ||||
| Show All 15 Lines | |||||
| // CHECK2-NEXT: call void @llvm.dbg.declare(metadata ptr [[ARGC_ADDR]], metadata [[META199:![0-9]+]], metadata !DIExpression()), !dbg [[DBG197]] | // CHECK2-NEXT: call void @llvm.dbg.declare(metadata ptr [[ARGC_ADDR]], metadata [[META199:![0-9]+]], metadata !DIExpression()), !dbg [[DBG197]] | ||||
| // CHECK2-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 | // CHECK2-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 | ||||
| // CHECK2-NEXT: call void @llvm.dbg.declare(metadata ptr [[VLA_ADDR]], metadata [[META200:![0-9]+]], metadata !DIExpression()), !dbg [[DBG197]] | // CHECK2-NEXT: call void @llvm.dbg.declare(metadata ptr [[VLA_ADDR]], metadata [[META200:![0-9]+]], metadata !DIExpression()), !dbg [[DBG197]] | ||||
| // CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARGC_ADDR]], align 8, !dbg [[DBG201:![0-9]+]] | // CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARGC_ADDR]], align 8, !dbg [[DBG201:![0-9]+]] | ||||
| // CHECK2-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8, !dbg [[DBG201]] | // CHECK2-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8, !dbg [[DBG201]] | ||||
| // CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG201]] | // CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG201]] | ||||
| // CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTBOUND_TID__ADDR]], align 8, !dbg [[DBG201]] | // CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTBOUND_TID__ADDR]], align 8, !dbg [[DBG201]] | ||||
| // CHECK2-NEXT: [[TMP4:%.*]] = load ptr, ptr [[ARGC_ADDR]], align 8, !dbg [[DBG201]] | // CHECK2-NEXT: [[TMP4:%.*]] = load ptr, ptr [[ARGC_ADDR]], align 8, !dbg [[DBG201]] | ||||
| // CHECK2-NEXT: call void @.omp_outlined._debug__.9(ptr [[TMP2]], ptr [[TMP3]], ptr [[TMP4]], i64 [[TMP1]]) #[[ATTR6]], !dbg [[DBG201]] | // CHECK2-NEXT: call void @.omp_outlined._debug__.9(ptr [[TMP2]], ptr [[TMP3]], ptr [[TMP4]], i64 [[TMP1]]) #[[ATTR5]], !dbg [[DBG201]] | ||||
| // CHECK2-NEXT: ret void, !dbg [[DBG201]] | // CHECK2-NEXT: ret void, !dbg [[DBG201]] | ||||
| // | // | ||||
| // | // | ||||
| // CHECK3-LABEL: define {{[^@]+}}@main | // CHECK3-LABEL: define {{[^@]+}}@main | ||||
| // CHECK3-SAME: (i32 noundef [[ARGC:%.*]], ptr noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { | // CHECK3-SAME: (i32 noundef [[ARGC:%.*]], ptr noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { | ||||
| // CHECK3-NEXT: entry: | // CHECK3-NEXT: entry: | ||||
| // CHECK3-NEXT: [[STRUCTARG:%.*]] = alloca { ptr }, align 8 | // CHECK3-NEXT: [[STRUCTARG:%.*]] = alloca { ptr }, align 8 | ||||
| // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 | // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 | ||||
| ▲ Show 20 Lines • Show All 278 Lines • Show Last 20 Lines | |||||