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clang/test/OpenMP/distribute_parallel_for_num_threads_codegen.cpp
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| // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 | // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 | ||||
| // CHECK1-NEXT: store ptr null, ptr [[TMP7]], align 8 | // CHECK1-NEXT: store ptr null, ptr [[TMP7]], align 8 | ||||
| // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 | // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 | ||||
| // CHECK1-NEXT: store i64 100, ptr [[TMP8]], align 8 | // CHECK1-NEXT: store i64 100, ptr [[TMP8]], align 8 | ||||
| // CHECK1-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.region_id, ptr [[KERNEL_ARGS]]) | // CHECK1-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.region_id, ptr [[KERNEL_ARGS]]) | ||||
| // CHECK1-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 | // CHECK1-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 | ||||
| // CHECK1-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] | // CHECK1-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] | ||||
| // CHECK1: omp_offload.failed: | // CHECK1: omp_offload.failed: | ||||
| // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68() #[[ATTR6:[0-9]+]] | // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68() #[[ATTR5:[0-9]+]] | ||||
| // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] | // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] | ||||
| // CHECK1: lpad: | // CHECK1: lpad: | ||||
| // CHECK1-NEXT: [[TMP11:%.*]] = landingpad { ptr, i32 } | // CHECK1-NEXT: [[TMP11:%.*]] = landingpad { ptr, i32 } | ||||
| // CHECK1-NEXT: cleanup | // CHECK1-NEXT: cleanup | ||||
| // CHECK1-NEXT: [[TMP12:%.*]] = extractvalue { ptr, i32 } [[TMP11]], 0 | // CHECK1-NEXT: [[TMP12:%.*]] = extractvalue { ptr, i32 } [[TMP11]], 0 | ||||
| // CHECK1-NEXT: store ptr [[TMP12]], ptr [[EXN_SLOT]], align 8 | // CHECK1-NEXT: store ptr [[TMP12]], ptr [[EXN_SLOT]], align 8 | ||||
| // CHECK1-NEXT: [[TMP13:%.*]] = extractvalue { ptr, i32 } [[TMP11]], 1 | // CHECK1-NEXT: [[TMP13:%.*]] = extractvalue { ptr, i32 } [[TMP11]], 1 | ||||
| // CHECK1-NEXT: store i32 [[TMP13]], ptr [[EHSELECTOR_SLOT]], align 4 | // CHECK1-NEXT: store i32 [[TMP13]], ptr [[EHSELECTOR_SLOT]], align 4 | ||||
| // CHECK1-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR6]] | // CHECK1-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR5]] | ||||
| // CHECK1-NEXT: br label [[EH_RESUME:%.*]] | // CHECK1-NEXT: br label [[EH_RESUME:%.*]] | ||||
| // CHECK1: omp_offload.cont: | // CHECK1: omp_offload.cont: | ||||
| // CHECK1-NEXT: [[TMP14:%.*]] = load i8, ptr [[A]], align 1 | // CHECK1-NEXT: [[TMP14:%.*]] = load i8, ptr [[A]], align 1 | ||||
| // CHECK1-NEXT: store i8 [[TMP14]], ptr [[A_CASTED]], align 1 | // CHECK1-NEXT: store i8 [[TMP14]], ptr [[A_CASTED]], align 1 | ||||
| // CHECK1-NEXT: [[TMP15:%.*]] = load i64, ptr [[A_CASTED]], align 8 | // CHECK1-NEXT: [[TMP15:%.*]] = load i64, ptr [[A_CASTED]], align 8 | ||||
| // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 | // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 | ||||
| // CHECK1-NEXT: store i64 [[TMP15]], ptr [[TMP16]], align 8 | // CHECK1-NEXT: store i64 [[TMP15]], ptr [[TMP16]], align 8 | ||||
| // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 | // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 | ||||
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| // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 7 | // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 7 | ||||
| // CHECK1-NEXT: store ptr null, ptr [[TMP28]], align 8 | // CHECK1-NEXT: store ptr null, ptr [[TMP28]], align 8 | ||||
| // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 8 | // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 8 | ||||
| // CHECK1-NEXT: store i64 100, ptr [[TMP29]], align 8 | // CHECK1-NEXT: store i64 100, ptr [[TMP29]], align 8 | ||||
| // CHECK1-NEXT: [[TMP30:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74.region_id, ptr [[KERNEL_ARGS2]]) | // CHECK1-NEXT: [[TMP30:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74.region_id, ptr [[KERNEL_ARGS2]]) | ||||
| // CHECK1-NEXT: [[TMP31:%.*]] = icmp ne i32 [[TMP30]], 0 | // CHECK1-NEXT: [[TMP31:%.*]] = icmp ne i32 [[TMP30]], 0 | ||||
| // CHECK1-NEXT: br i1 [[TMP31]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]] | // CHECK1-NEXT: br i1 [[TMP31]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]] | ||||
| // CHECK1: omp_offload.failed3: | // CHECK1: omp_offload.failed3: | ||||
| // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74(i64 [[TMP15]]) #[[ATTR6]] | // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74(i64 [[TMP15]]) #[[ATTR5]] | ||||
| // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT4]] | // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT4]] | ||||
| // CHECK1: omp_offload.cont4: | // CHECK1: omp_offload.cont4: | ||||
| // CHECK1-NEXT: [[TMP32:%.*]] = load i8, ptr [[A]], align 1 | // CHECK1-NEXT: [[TMP32:%.*]] = load i8, ptr [[A]], align 1 | ||||
| // CHECK1-NEXT: [[CONV:%.*]] = sext i8 [[TMP32]] to i32 | // CHECK1-NEXT: [[CONV:%.*]] = sext i8 [[TMP32]] to i32 | ||||
| // CHECK1-NEXT: [[CALL6:%.*]] = invoke noundef i32 @_Z5tmainIcLi5EEiv() | // CHECK1-NEXT: [[CALL6:%.*]] = invoke noundef i32 @_Z5tmainIcLi5EEiv() | ||||
| // CHECK1-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[LPAD]] | // CHECK1-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[LPAD]] | ||||
| // CHECK1: invoke.cont5: | // CHECK1: invoke.cont5: | ||||
| // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], [[CALL6]] | // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], [[CALL6]] | ||||
| // CHECK1-NEXT: [[CALL8:%.*]] = invoke noundef i32 @_Z5tmainI1SLi1EEiv() | // CHECK1-NEXT: [[CALL8:%.*]] = invoke noundef i32 @_Z5tmainI1SLi1EEiv() | ||||
| // CHECK1-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD]] | // CHECK1-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD]] | ||||
| // CHECK1: invoke.cont7: | // CHECK1: invoke.cont7: | ||||
| // CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 [[ADD]], [[CALL8]] | // CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 [[ADD]], [[CALL8]] | ||||
| // CHECK1-NEXT: store i32 [[ADD9]], ptr [[RETVAL]], align 4 | // CHECK1-NEXT: store i32 [[ADD9]], ptr [[RETVAL]], align 4 | ||||
| // CHECK1-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR6]] | // CHECK1-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR5]] | ||||
| // CHECK1-NEXT: [[TMP33:%.*]] = load i32, ptr [[RETVAL]], align 4 | // CHECK1-NEXT: [[TMP33:%.*]] = load i32, ptr [[RETVAL]], align 4 | ||||
| // CHECK1-NEXT: ret i32 [[TMP33]] | // CHECK1-NEXT: ret i32 [[TMP33]] | ||||
| // CHECK1: eh.resume: | // CHECK1: eh.resume: | ||||
| // CHECK1-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8 | // CHECK1-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8 | ||||
| // CHECK1-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4 | // CHECK1-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4 | ||||
| // CHECK1-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0 | // CHECK1-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0 | ||||
| // CHECK1-NEXT: [[LPAD_VAL10:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1 | // CHECK1-NEXT: [[LPAD_VAL10:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1 | ||||
| // CHECK1-NEXT: resume { ptr, i32 } [[LPAD_VAL10]] | // CHECK1-NEXT: resume { ptr, i32 } [[LPAD_VAL10]] | ||||
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| // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 | // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 | ||||
| // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] | // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] | ||||
| // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | ||||
| // CHECK1: omp.inner.for.body: | // CHECK1: omp.inner.for.body: | ||||
| // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | ||||
| // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 | // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 | ||||
| // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | ||||
| // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4 | // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4 | ||||
| // CHECK1-NEXT: invoke void @_Z3foov() | // CHECK1-NEXT: call unwindabort void @_Z3foov() | ||||
| // CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] | |||||
| // CHECK1: invoke.cont: | |||||
| // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | ||||
| // CHECK1: omp.body.continue: | // CHECK1: omp.body.continue: | ||||
| // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | ||||
| // CHECK1: omp.inner.for.inc: | // CHECK1: omp.inner.for.inc: | ||||
| // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | ||||
| // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 | // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 | ||||
| // CHECK1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4 | // CHECK1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4 | ||||
| // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] | // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] | ||||
| // CHECK1: omp.inner.for.end: | // CHECK1: omp.inner.for.end: | ||||
| // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | ||||
| // CHECK1: omp.loop.exit: | // CHECK1: omp.loop.exit: | ||||
| // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) | // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) | ||||
| // CHECK1-NEXT: ret void | // CHECK1-NEXT: ret void | ||||
| // CHECK1: terminate.lpad: | |||||
| // CHECK1-NEXT: [[TMP11:%.*]] = landingpad { ptr, i32 } | |||||
| // CHECK1-NEXT: catch ptr null | |||||
| // CHECK1-NEXT: [[TMP12:%.*]] = extractvalue { ptr, i32 } [[TMP11]], 0 | |||||
| // CHECK1-NEXT: call void @__clang_call_terminate(ptr [[TMP12]]) #[[ATTR10:[0-9]+]] | |||||
| // CHECK1-NEXT: unreachable | |||||
| // | |||||
| // | |||||
| // CHECK1-LABEL: define {{[^@]+}}@__clang_call_terminate | |||||
| // CHECK1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR5:[0-9]+]] comdat { | |||||
| // CHECK1-NEXT: [[TMP2:%.*]] = call ptr @__cxa_begin_catch(ptr [[TMP0]]) #[[ATTR6]] | |||||
| // CHECK1-NEXT: call void @_ZSt9terminatev() #[[ATTR10]] | |||||
| // CHECK1-NEXT: unreachable | |||||
| // | // | ||||
| // | // | ||||
| // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74 | // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74 | ||||
| // CHECK1-SAME: (i64 noundef [[A:%.*]]) #[[ATTR3]] { | // CHECK1-SAME: (i64 noundef [[A:%.*]]) #[[ATTR3]] { | ||||
| // CHECK1-NEXT: entry: | // CHECK1-NEXT: entry: | ||||
| // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 | // CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 | ||||
| // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 1, ptr @.omp_outlined..2, ptr [[A_ADDR]]) | // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 1, ptr @.omp_outlined..2, ptr [[A_ADDR]]) | ||||
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| // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 | // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 | ||||
| // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] | // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] | ||||
| // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | ||||
| // CHECK1: omp.inner.for.body: | // CHECK1: omp.inner.for.body: | ||||
| // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | ||||
| // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 | // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 | ||||
| // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | ||||
| // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4 | // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4 | ||||
| // CHECK1-NEXT: invoke void @_Z3foov() | // CHECK1-NEXT: call unwindabort void @_Z3foov() | ||||
| // CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] | |||||
| // CHECK1: invoke.cont: | |||||
| // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | ||||
| // CHECK1: omp.body.continue: | // CHECK1: omp.body.continue: | ||||
| // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | ||||
| // CHECK1: omp.inner.for.inc: | // CHECK1: omp.inner.for.inc: | ||||
| // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | ||||
| // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 | // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 | ||||
| // CHECK1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4 | // CHECK1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4 | ||||
| // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] | // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] | ||||
| // CHECK1: omp.inner.for.end: | // CHECK1: omp.inner.for.end: | ||||
| // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | ||||
| // CHECK1: omp.loop.exit: | // CHECK1: omp.loop.exit: | ||||
| // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) | // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) | ||||
| // CHECK1-NEXT: ret void | // CHECK1-NEXT: ret void | ||||
| // CHECK1: terminate.lpad: | |||||
| // CHECK1-NEXT: [[TMP11:%.*]] = landingpad { ptr, i32 } | |||||
| // CHECK1-NEXT: catch ptr null | |||||
| // CHECK1-NEXT: [[TMP12:%.*]] = extractvalue { ptr, i32 } [[TMP11]], 0 | |||||
| // CHECK1-NEXT: call void @__clang_call_terminate(ptr [[TMP12]]) #[[ATTR10]] | |||||
| // CHECK1-NEXT: unreachable | |||||
| // | // | ||||
| // | // | ||||
| // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIcLi5EEiv | // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIcLi5EEiv | ||||
| // CHECK1-SAME: () #[[ATTR7:[0-9]+]] comdat { | // CHECK1-SAME: () #[[ATTR6:[0-9]+]] comdat { | ||||
| // CHECK1-NEXT: entry: | // CHECK1-NEXT: entry: | ||||
| // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 | // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 | ||||
| // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 | // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 | ||||
| // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 | // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 | ||||
| // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 | // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 | ||||
| // CHECK1-NEXT: store i32 1, ptr [[TMP0]], align 4 | // CHECK1-NEXT: store i32 1, ptr [[TMP0]], align 4 | ||||
| // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 | // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 | ||||
| // CHECK1-NEXT: store i32 0, ptr [[TMP1]], align 4 | // CHECK1-NEXT: store i32 0, ptr [[TMP1]], align 4 | ||||
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| // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 | // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 | ||||
| // CHECK1-NEXT: store ptr null, ptr [[TMP7]], align 8 | // CHECK1-NEXT: store ptr null, ptr [[TMP7]], align 8 | ||||
| // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 | // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 | ||||
| // CHECK1-NEXT: store i64 100, ptr [[TMP8]], align 8 | // CHECK1-NEXT: store i64 100, ptr [[TMP8]], align 8 | ||||
| // CHECK1-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l52.region_id, ptr [[KERNEL_ARGS]]) | // CHECK1-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l52.region_id, ptr [[KERNEL_ARGS]]) | ||||
| // CHECK1-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 | // CHECK1-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 | ||||
| // CHECK1-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] | // CHECK1-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] | ||||
| // CHECK1: omp_offload.failed: | // CHECK1: omp_offload.failed: | ||||
| // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l52() #[[ATTR6]] | // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l52() #[[ATTR5]] | ||||
| // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] | // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] | ||||
| // CHECK1: omp_offload.cont: | // CHECK1: omp_offload.cont: | ||||
| // CHECK1-NEXT: [[KERNEL_ARGS2:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 | // CHECK1-NEXT: [[KERNEL_ARGS2:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 | ||||
| // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 0 | // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 0 | ||||
| // CHECK1-NEXT: store i32 1, ptr [[TMP11]], align 4 | // CHECK1-NEXT: store i32 1, ptr [[TMP11]], align 4 | ||||
| // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 1 | // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 1 | ||||
| // CHECK1-NEXT: store i32 0, ptr [[TMP12]], align 4 | // CHECK1-NEXT: store i32 0, ptr [[TMP12]], align 4 | ||||
| // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 2 | // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 2 | ||||
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| // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 7 | // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 7 | ||||
| // CHECK1-NEXT: store ptr null, ptr [[TMP18]], align 8 | // CHECK1-NEXT: store ptr null, ptr [[TMP18]], align 8 | ||||
| // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 8 | // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 8 | ||||
| // CHECK1-NEXT: store i64 100, ptr [[TMP19]], align 8 | // CHECK1-NEXT: store i64 100, ptr [[TMP19]], align 8 | ||||
| // CHECK1-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l57.region_id, ptr [[KERNEL_ARGS2]]) | // CHECK1-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l57.region_id, ptr [[KERNEL_ARGS2]]) | ||||
| // CHECK1-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 | // CHECK1-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 | ||||
| // CHECK1-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]] | // CHECK1-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]] | ||||
| // CHECK1: omp_offload.failed3: | // CHECK1: omp_offload.failed3: | ||||
| // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l57() #[[ATTR6]] | // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l57() #[[ATTR5]] | ||||
| // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT4]] | // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT4]] | ||||
| // CHECK1: omp_offload.cont4: | // CHECK1: omp_offload.cont4: | ||||
| // CHECK1-NEXT: ret i32 0 | // CHECK1-NEXT: ret i32 0 | ||||
| // | // | ||||
| // | // | ||||
| // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainI1SLi1EEiv | // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainI1SLi1EEiv | ||||
| // CHECK1-SAME: () #[[ATTR7]] comdat { | // CHECK1-SAME: () #[[ATTR6]] comdat { | ||||
| // CHECK1-NEXT: entry: | // CHECK1-NEXT: entry: | ||||
| // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 | // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 | ||||
| // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 | // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 | ||||
| // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 | // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 | ||||
| // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 | // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 | ||||
| // CHECK1-NEXT: store i32 1, ptr [[TMP0]], align 4 | // CHECK1-NEXT: store i32 1, ptr [[TMP0]], align 4 | ||||
| // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 | // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 | ||||
| // CHECK1-NEXT: store i32 0, ptr [[TMP1]], align 4 | // CHECK1-NEXT: store i32 0, ptr [[TMP1]], align 4 | ||||
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| // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 | // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 | ||||
| // CHECK1-NEXT: store ptr null, ptr [[TMP7]], align 8 | // CHECK1-NEXT: store ptr null, ptr [[TMP7]], align 8 | ||||
| // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 | // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 | ||||
| // CHECK1-NEXT: store i64 100, ptr [[TMP8]], align 8 | // CHECK1-NEXT: store i64 100, ptr [[TMP8]], align 8 | ||||
| // CHECK1-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l52.region_id, ptr [[KERNEL_ARGS]]) | // CHECK1-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l52.region_id, ptr [[KERNEL_ARGS]]) | ||||
| // CHECK1-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 | // CHECK1-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 | ||||
| // CHECK1-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] | // CHECK1-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] | ||||
| // CHECK1: omp_offload.failed: | // CHECK1: omp_offload.failed: | ||||
| // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l52() #[[ATTR6]] | // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l52() #[[ATTR5]] | ||||
| // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] | // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] | ||||
| // CHECK1: omp_offload.cont: | // CHECK1: omp_offload.cont: | ||||
| // CHECK1-NEXT: [[KERNEL_ARGS2:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 | // CHECK1-NEXT: [[KERNEL_ARGS2:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 | ||||
| // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 0 | // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 0 | ||||
| // CHECK1-NEXT: store i32 1, ptr [[TMP11]], align 4 | // CHECK1-NEXT: store i32 1, ptr [[TMP11]], align 4 | ||||
| // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 1 | // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 1 | ||||
| // CHECK1-NEXT: store i32 0, ptr [[TMP12]], align 4 | // CHECK1-NEXT: store i32 0, ptr [[TMP12]], align 4 | ||||
| // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 2 | // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 2 | ||||
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| // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 7 | // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 7 | ||||
| // CHECK1-NEXT: store ptr null, ptr [[TMP18]], align 8 | // CHECK1-NEXT: store ptr null, ptr [[TMP18]], align 8 | ||||
| // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 8 | // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 8 | ||||
| // CHECK1-NEXT: store i64 100, ptr [[TMP19]], align 8 | // CHECK1-NEXT: store i64 100, ptr [[TMP19]], align 8 | ||||
| // CHECK1-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l57.region_id, ptr [[KERNEL_ARGS2]]) | // CHECK1-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l57.region_id, ptr [[KERNEL_ARGS2]]) | ||||
| // CHECK1-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 | // CHECK1-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 | ||||
| // CHECK1-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]] | // CHECK1-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]] | ||||
| // CHECK1: omp_offload.failed3: | // CHECK1: omp_offload.failed3: | ||||
| // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l57() #[[ATTR6]] | // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l57() #[[ATTR5]] | ||||
| // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT4]] | // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT4]] | ||||
| // CHECK1: omp_offload.cont4: | // CHECK1: omp_offload.cont4: | ||||
| // CHECK1-NEXT: ret i32 0 | // CHECK1-NEXT: ret i32 0 | ||||
| // | // | ||||
| // | // | ||||
| // CHECK1-LABEL: define {{[^@]+}}@_ZN1SD1Ev | // CHECK1-LABEL: define {{[^@]+}}@_ZN1SD1Ev | ||||
| // CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR8:[0-9]+]] comdat align 2 { | // CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR7:[0-9]+]] comdat align 2 { | ||||
| // CHECK1-NEXT: entry: | // CHECK1-NEXT: entry: | ||||
| // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 | // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 | ||||
| // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 | // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 | ||||
| // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 | // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 | ||||
| // CHECK1-NEXT: call void @_ZN1SD2Ev(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR6]] | // CHECK1-NEXT: call void @_ZN1SD2Ev(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR5]] | ||||
| // CHECK1-NEXT: ret void | // CHECK1-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK1-LABEL: define {{[^@]+}}@_ZN1SC2El | // CHECK1-LABEL: define {{[^@]+}}@_ZN1SC2El | ||||
| // CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR8]] comdat align 2 { | // CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR7]] comdat align 2 { | ||||
| // CHECK1-NEXT: entry: | // CHECK1-NEXT: entry: | ||||
| // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 | // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 | ||||
| // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 | // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 | ||||
| // CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 | // CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 | ||||
| // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 | // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 | ||||
| // CHECK1-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 | // CHECK1-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 | ||||
| // CHECK1-NEXT: [[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8 | // CHECK1-NEXT: [[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8 | ||||
| // CHECK1-NEXT: store i64 [[TMP0]], ptr [[A2]], align 8 | // CHECK1-NEXT: store i64 [[TMP0]], ptr [[A2]], align 8 | ||||
| // CHECK1-NEXT: ret void | // CHECK1-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK1-LABEL: define {{[^@]+}}@_ZN1SD2Ev | // CHECK1-LABEL: define {{[^@]+}}@_ZN1SD2Ev | ||||
| // CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR8]] comdat align 2 { | // CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR7]] comdat align 2 { | ||||
| // CHECK1-NEXT: entry: | // CHECK1-NEXT: entry: | ||||
| // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 | // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 | ||||
| // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 | // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 | ||||
| // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 | // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 | ||||
| // CHECK1-NEXT: ret void | // CHECK1-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l52 | // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l52 | ||||
| ▲ Show 20 Lines • Show All 114 Lines • ▼ Show 20 Lines | |||||
| // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 | // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 | ||||
| // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] | // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] | ||||
| // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | ||||
| // CHECK1: omp.inner.for.body: | // CHECK1: omp.inner.for.body: | ||||
| // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | ||||
| // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 | // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 | ||||
| // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | ||||
| // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4 | // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4 | ||||
| // CHECK1-NEXT: invoke void @_Z3foov() | // CHECK1-NEXT: call unwindabort void @_Z3foov() | ||||
| // CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] | |||||
| // CHECK1: invoke.cont: | |||||
| // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | ||||
| // CHECK1: omp.body.continue: | // CHECK1: omp.body.continue: | ||||
| // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | ||||
| // CHECK1: omp.inner.for.inc: | // CHECK1: omp.inner.for.inc: | ||||
| // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | ||||
| // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 | // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 | ||||
| // CHECK1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4 | // CHECK1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4 | ||||
| // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] | // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] | ||||
| // CHECK1: omp.inner.for.end: | // CHECK1: omp.inner.for.end: | ||||
| // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | ||||
| // CHECK1: omp.loop.exit: | // CHECK1: omp.loop.exit: | ||||
| // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) | // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) | ||||
| // CHECK1-NEXT: ret void | // CHECK1-NEXT: ret void | ||||
| // CHECK1: terminate.lpad: | |||||
| // CHECK1-NEXT: [[TMP11:%.*]] = landingpad { ptr, i32 } | |||||
| // CHECK1-NEXT: catch ptr null | |||||
| // CHECK1-NEXT: [[TMP12:%.*]] = extractvalue { ptr, i32 } [[TMP11]], 0 | |||||
| // CHECK1-NEXT: call void @__clang_call_terminate(ptr [[TMP12]]) #[[ATTR10]] | |||||
| // CHECK1-NEXT: unreachable | |||||
| // | // | ||||
| // | // | ||||
| // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l57 | // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l57 | ||||
| // CHECK1-SAME: () #[[ATTR3]] { | // CHECK1-SAME: () #[[ATTR3]] { | ||||
| // CHECK1-NEXT: entry: | // CHECK1-NEXT: entry: | ||||
| // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @.omp_outlined..6) | // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @.omp_outlined..6) | ||||
| // CHECK1-NEXT: ret void | // CHECK1-NEXT: ret void | ||||
| // | // | ||||
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| // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 | // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 | ||||
| // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] | // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] | ||||
| // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | ||||
| // CHECK1: omp.inner.for.body: | // CHECK1: omp.inner.for.body: | ||||
| // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | ||||
| // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 | // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 | ||||
| // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | ||||
| // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4 | // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4 | ||||
| // CHECK1-NEXT: invoke void @_Z3foov() | // CHECK1-NEXT: call unwindabort void @_Z3foov() | ||||
| // CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] | |||||
| // CHECK1: invoke.cont: | |||||
| // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | ||||
| // CHECK1: omp.body.continue: | // CHECK1: omp.body.continue: | ||||
| // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | ||||
| // CHECK1: omp.inner.for.inc: | // CHECK1: omp.inner.for.inc: | ||||
| // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | ||||
| // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 | // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 | ||||
| // CHECK1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4 | // CHECK1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4 | ||||
| // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] | // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] | ||||
| // CHECK1: omp.inner.for.end: | // CHECK1: omp.inner.for.end: | ||||
| // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | ||||
| // CHECK1: omp.loop.exit: | // CHECK1: omp.loop.exit: | ||||
| // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) | // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) | ||||
| // CHECK1-NEXT: ret void | // CHECK1-NEXT: ret void | ||||
| // CHECK1: terminate.lpad: | |||||
| // CHECK1-NEXT: [[TMP11:%.*]] = landingpad { ptr, i32 } | |||||
| // CHECK1-NEXT: catch ptr null | |||||
| // CHECK1-NEXT: [[TMP12:%.*]] = extractvalue { ptr, i32 } [[TMP11]], 0 | |||||
| // CHECK1-NEXT: call void @__clang_call_terminate(ptr [[TMP12]]) #[[ATTR10]] | |||||
| // CHECK1-NEXT: unreachable | |||||
| // | // | ||||
| // | // | ||||
| // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l52 | // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l52 | ||||
| // CHECK1-SAME: () #[[ATTR3]] { | // CHECK1-SAME: () #[[ATTR3]] { | ||||
| // CHECK1-NEXT: entry: | // CHECK1-NEXT: entry: | ||||
| // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @.omp_outlined..8) | // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @.omp_outlined..8) | ||||
| // CHECK1-NEXT: ret void | // CHECK1-NEXT: ret void | ||||
| // | // | ||||
| ▲ Show 20 Lines • Show All 109 Lines • ▼ Show 20 Lines | |||||
| // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 | // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 | ||||
| // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] | // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] | ||||
| // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | ||||
| // CHECK1: omp.inner.for.body: | // CHECK1: omp.inner.for.body: | ||||
| // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | ||||
| // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 | // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 | ||||
| // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | ||||
| // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4 | // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4 | ||||
| // CHECK1-NEXT: invoke void @_Z3foov() | // CHECK1-NEXT: call unwindabort void @_Z3foov() | ||||
| // CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] | |||||
| // CHECK1: invoke.cont: | |||||
| // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | ||||
| // CHECK1: omp.body.continue: | // CHECK1: omp.body.continue: | ||||
| // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | ||||
| // CHECK1: omp.inner.for.inc: | // CHECK1: omp.inner.for.inc: | ||||
| // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | ||||
| // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 | // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 | ||||
| // CHECK1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4 | // CHECK1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4 | ||||
| // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] | // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] | ||||
| // CHECK1: omp.inner.for.end: | // CHECK1: omp.inner.for.end: | ||||
| // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | ||||
| // CHECK1: omp.loop.exit: | // CHECK1: omp.loop.exit: | ||||
| // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) | // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) | ||||
| // CHECK1-NEXT: ret void | // CHECK1-NEXT: ret void | ||||
| // CHECK1: terminate.lpad: | |||||
| // CHECK1-NEXT: [[TMP11:%.*]] = landingpad { ptr, i32 } | |||||
| // CHECK1-NEXT: catch ptr null | |||||
| // CHECK1-NEXT: [[TMP12:%.*]] = extractvalue { ptr, i32 } [[TMP11]], 0 | |||||
| // CHECK1-NEXT: call void @__clang_call_terminate(ptr [[TMP12]]) #[[ATTR10]] | |||||
| // CHECK1-NEXT: unreachable | |||||
| // | // | ||||
| // | // | ||||
| // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l57 | // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l57 | ||||
| // CHECK1-SAME: () #[[ATTR3]] { | // CHECK1-SAME: () #[[ATTR3]] { | ||||
| // CHECK1-NEXT: entry: | // CHECK1-NEXT: entry: | ||||
| // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @.omp_outlined..10) | // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @.omp_outlined..10) | ||||
| // CHECK1-NEXT: ret void | // CHECK1-NEXT: ret void | ||||
| // | // | ||||
| Show All 35 Lines | |||||
| // CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 | // CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 | ||||
| // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] | // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] | ||||
| // CHECK1: omp.inner.for.cond: | // CHECK1: omp.inner.for.cond: | ||||
| // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | ||||
| // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 | // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 | ||||
| // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] | // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] | ||||
| // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | ||||
| // CHECK1: omp.inner.for.body: | // CHECK1: omp.inner.for.body: | ||||
| // CHECK1-NEXT: invoke void @_ZN1SC1El(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]], i64 noundef 23) | // CHECK1-NEXT: call unwindabort void @_ZN1SC1El(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]], i64 noundef 23) | ||||
| // CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] | // CHECK1-NEXT: [[CALL:%.*]] = call unwindabort noundef signext i8 @_ZN1ScvcEv(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) | ||||
| // CHECK1: invoke.cont: | |||||
| // CHECK1-NEXT: [[CALL:%.*]] = invoke noundef signext i8 @_ZN1ScvcEv(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) | |||||
| // CHECK1-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[TERMINATE_LPAD]] | |||||
| // CHECK1: invoke.cont2: | |||||
| // CHECK1-NEXT: [[TMP7:%.*]] = sext i8 [[CALL]] to i32 | // CHECK1-NEXT: [[TMP7:%.*]] = sext i8 [[CALL]] to i32 | ||||
| // CHECK1-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP1]], i32 [[TMP7]]) | // CHECK1-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP1]], i32 [[TMP7]]) | ||||
| // CHECK1-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]] | // CHECK1-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR5]] | ||||
| // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 | // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 | ||||
| // CHECK1-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 | // CHECK1-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 | ||||
| // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 | // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 | ||||
| // CHECK1-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 | // CHECK1-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 | ||||
| // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @.omp_outlined..11, i64 [[TMP9]], i64 [[TMP11]]) | // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @.omp_outlined..11, i64 [[TMP9]], i64 [[TMP11]]) | ||||
| // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | ||||
| // CHECK1: omp.inner.for.inc: | // CHECK1: omp.inner.for.inc: | ||||
| // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | ||||
| // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 | // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 | ||||
| // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] | // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] | ||||
| // CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 | // CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 | ||||
| // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] | // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] | ||||
| // CHECK1: omp.inner.for.end: | // CHECK1: omp.inner.for.end: | ||||
| // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | ||||
| // CHECK1: omp.loop.exit: | // CHECK1: omp.loop.exit: | ||||
| // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) | // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) | ||||
| // CHECK1-NEXT: ret void | // CHECK1-NEXT: ret void | ||||
| // CHECK1: terminate.lpad: | |||||
| // CHECK1-NEXT: [[TMP14:%.*]] = landingpad { ptr, i32 } | |||||
| // CHECK1-NEXT: catch ptr null | |||||
| // CHECK1-NEXT: [[TMP15:%.*]] = extractvalue { ptr, i32 } [[TMP14]], 0 | |||||
| // CHECK1-NEXT: call void @__clang_call_terminate(ptr [[TMP15]]) #[[ATTR10]] | |||||
| // CHECK1-NEXT: unreachable | |||||
| // | // | ||||
| // | // | ||||
| // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..11 | // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..11 | ||||
| // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality ptr @__gxx_personality_v0 { | // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality ptr @__gxx_personality_v0 { | ||||
| // CHECK1-NEXT: entry: | // CHECK1-NEXT: entry: | ||||
| // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 | // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 | ||||
| // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 | // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 | ||||
| // CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 | // CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 | ||||
| ▲ Show 20 Lines • Show All 41 Lines • ▼ Show 20 Lines | |||||
| // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 | // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 | ||||
| // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] | // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] | ||||
| // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | ||||
| // CHECK1: omp.inner.for.body: | // CHECK1: omp.inner.for.body: | ||||
| // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | ||||
| // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 | // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 | ||||
| // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | ||||
| // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4 | // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4 | ||||
| // CHECK1-NEXT: invoke void @_Z3foov() | // CHECK1-NEXT: call unwindabort void @_Z3foov() | ||||
| // CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] | |||||
| // CHECK1: invoke.cont: | |||||
| // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | ||||
| // CHECK1: omp.body.continue: | // CHECK1: omp.body.continue: | ||||
| // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | ||||
| // CHECK1: omp.inner.for.inc: | // CHECK1: omp.inner.for.inc: | ||||
| // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | ||||
| // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 | // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 | ||||
| // CHECK1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4 | // CHECK1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4 | ||||
| // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] | // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] | ||||
| // CHECK1: omp.inner.for.end: | // CHECK1: omp.inner.for.end: | ||||
| // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | ||||
| // CHECK1: omp.loop.exit: | // CHECK1: omp.loop.exit: | ||||
| // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) | // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) | ||||
| // CHECK1-NEXT: ret void | // CHECK1-NEXT: ret void | ||||
| // CHECK1: terminate.lpad: | |||||
| // CHECK1-NEXT: [[TMP11:%.*]] = landingpad { ptr, i32 } | |||||
| // CHECK1-NEXT: catch ptr null | |||||
| // CHECK1-NEXT: [[TMP12:%.*]] = extractvalue { ptr, i32 } [[TMP11]], 0 | |||||
| // CHECK1-NEXT: call void @__clang_call_terminate(ptr [[TMP12]]) #[[ATTR10]] | |||||
| // CHECK1-NEXT: unreachable | |||||
| // | // | ||||
| // | // | ||||
| // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg | // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg | ||||
| // CHECK1-SAME: () #[[ATTR9:[0-9]+]] { | // CHECK1-SAME: () #[[ATTR8:[0-9]+]] { | ||||
| // CHECK1-NEXT: entry: | // CHECK1-NEXT: entry: | ||||
| // CHECK1-NEXT: call void @__tgt_register_requires(i64 1) | // CHECK1-NEXT: call void @__tgt_register_requires(i64 1) | ||||
| // CHECK1-NEXT: ret void | // CHECK1-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK5-LABEL: define {{[^@]+}}@main | // CHECK5-LABEL: define {{[^@]+}}@main | ||||
| // CHECK5-SAME: () #[[ATTR0:[0-9]+]] personality ptr @__gxx_personality_v0 { | // CHECK5-SAME: () #[[ATTR0:[0-9]+]] personality ptr @__gxx_personality_v0 { | ||||
| // CHECK5-NEXT: entry: | // CHECK5-NEXT: entry: | ||||
| Show All 32 Lines | |||||
| // CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 | // CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 | ||||
| // CHECK5-NEXT: store ptr null, ptr [[TMP7]], align 8 | // CHECK5-NEXT: store ptr null, ptr [[TMP7]], align 8 | ||||
| // CHECK5-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 | // CHECK5-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 | ||||
| // CHECK5-NEXT: store i64 100, ptr [[TMP8]], align 8 | // CHECK5-NEXT: store i64 100, ptr [[TMP8]], align 8 | ||||
| // CHECK5-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.region_id, ptr [[KERNEL_ARGS]]) | // CHECK5-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.region_id, ptr [[KERNEL_ARGS]]) | ||||
| // CHECK5-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 | // CHECK5-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 | ||||
| // CHECK5-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] | // CHECK5-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] | ||||
| // CHECK5: omp_offload.failed: | // CHECK5: omp_offload.failed: | ||||
| // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68() #[[ATTR6:[0-9]+]] | // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68() #[[ATTR5:[0-9]+]] | ||||
| // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] | // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] | ||||
| // CHECK5: lpad: | // CHECK5: lpad: | ||||
| // CHECK5-NEXT: [[TMP11:%.*]] = landingpad { ptr, i32 } | // CHECK5-NEXT: [[TMP11:%.*]] = landingpad { ptr, i32 } | ||||
| // CHECK5-NEXT: cleanup | // CHECK5-NEXT: cleanup | ||||
| // CHECK5-NEXT: [[TMP12:%.*]] = extractvalue { ptr, i32 } [[TMP11]], 0 | // CHECK5-NEXT: [[TMP12:%.*]] = extractvalue { ptr, i32 } [[TMP11]], 0 | ||||
| // CHECK5-NEXT: store ptr [[TMP12]], ptr [[EXN_SLOT]], align 8 | // CHECK5-NEXT: store ptr [[TMP12]], ptr [[EXN_SLOT]], align 8 | ||||
| // CHECK5-NEXT: [[TMP13:%.*]] = extractvalue { ptr, i32 } [[TMP11]], 1 | // CHECK5-NEXT: [[TMP13:%.*]] = extractvalue { ptr, i32 } [[TMP11]], 1 | ||||
| // CHECK5-NEXT: store i32 [[TMP13]], ptr [[EHSELECTOR_SLOT]], align 4 | // CHECK5-NEXT: store i32 [[TMP13]], ptr [[EHSELECTOR_SLOT]], align 4 | ||||
| // CHECK5-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR6]] | // CHECK5-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR5]] | ||||
| // CHECK5-NEXT: br label [[EH_RESUME:%.*]] | // CHECK5-NEXT: br label [[EH_RESUME:%.*]] | ||||
| // CHECK5: omp_offload.cont: | // CHECK5: omp_offload.cont: | ||||
| // CHECK5-NEXT: [[TMP14:%.*]] = load i8, ptr [[A]], align 1 | // CHECK5-NEXT: [[TMP14:%.*]] = load i8, ptr [[A]], align 1 | ||||
| // CHECK5-NEXT: store i8 [[TMP14]], ptr [[A_CASTED]], align 1 | // CHECK5-NEXT: store i8 [[TMP14]], ptr [[A_CASTED]], align 1 | ||||
| // CHECK5-NEXT: [[TMP15:%.*]] = load i64, ptr [[A_CASTED]], align 8 | // CHECK5-NEXT: [[TMP15:%.*]] = load i64, ptr [[A_CASTED]], align 8 | ||||
| // CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 | // CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 | ||||
| // CHECK5-NEXT: store i64 [[TMP15]], ptr [[TMP16]], align 8 | // CHECK5-NEXT: store i64 [[TMP15]], ptr [[TMP16]], align 8 | ||||
| // CHECK5-NEXT: [[TMP17:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 | // CHECK5-NEXT: [[TMP17:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 | ||||
| Show All 20 Lines | |||||
| // CHECK5-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 7 | // CHECK5-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 7 | ||||
| // CHECK5-NEXT: store ptr null, ptr [[TMP28]], align 8 | // CHECK5-NEXT: store ptr null, ptr [[TMP28]], align 8 | ||||
| // CHECK5-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 8 | // CHECK5-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 8 | ||||
| // CHECK5-NEXT: store i64 100, ptr [[TMP29]], align 8 | // CHECK5-NEXT: store i64 100, ptr [[TMP29]], align 8 | ||||
| // CHECK5-NEXT: [[TMP30:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74.region_id, ptr [[KERNEL_ARGS2]]) | // CHECK5-NEXT: [[TMP30:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74.region_id, ptr [[KERNEL_ARGS2]]) | ||||
| // CHECK5-NEXT: [[TMP31:%.*]] = icmp ne i32 [[TMP30]], 0 | // CHECK5-NEXT: [[TMP31:%.*]] = icmp ne i32 [[TMP30]], 0 | ||||
| // CHECK5-NEXT: br i1 [[TMP31]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]] | // CHECK5-NEXT: br i1 [[TMP31]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]] | ||||
| // CHECK5: omp_offload.failed3: | // CHECK5: omp_offload.failed3: | ||||
| // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74(i64 [[TMP15]]) #[[ATTR6]] | // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74(i64 [[TMP15]]) #[[ATTR5]] | ||||
| // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT4]] | // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT4]] | ||||
| // CHECK5: omp_offload.cont4: | // CHECK5: omp_offload.cont4: | ||||
| // CHECK5-NEXT: [[TMP32:%.*]] = load i8, ptr [[A]], align 1 | // CHECK5-NEXT: [[TMP32:%.*]] = load i8, ptr [[A]], align 1 | ||||
| // CHECK5-NEXT: [[CONV:%.*]] = sext i8 [[TMP32]] to i32 | // CHECK5-NEXT: [[CONV:%.*]] = sext i8 [[TMP32]] to i32 | ||||
| // CHECK5-NEXT: [[CALL6:%.*]] = invoke noundef i32 @_Z5tmainIcLi5EEiv() | // CHECK5-NEXT: [[CALL6:%.*]] = invoke noundef i32 @_Z5tmainIcLi5EEiv() | ||||
| // CHECK5-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[LPAD]] | // CHECK5-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[LPAD]] | ||||
| // CHECK5: invoke.cont5: | // CHECK5: invoke.cont5: | ||||
| // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], [[CALL6]] | // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], [[CALL6]] | ||||
| // CHECK5-NEXT: [[CALL8:%.*]] = invoke noundef i32 @_Z5tmainI1SLi1EEiv() | // CHECK5-NEXT: [[CALL8:%.*]] = invoke noundef i32 @_Z5tmainI1SLi1EEiv() | ||||
| // CHECK5-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD]] | // CHECK5-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD]] | ||||
| // CHECK5: invoke.cont7: | // CHECK5: invoke.cont7: | ||||
| // CHECK5-NEXT: [[ADD9:%.*]] = add nsw i32 [[ADD]], [[CALL8]] | // CHECK5-NEXT: [[ADD9:%.*]] = add nsw i32 [[ADD]], [[CALL8]] | ||||
| // CHECK5-NEXT: store i32 [[ADD9]], ptr [[RETVAL]], align 4 | // CHECK5-NEXT: store i32 [[ADD9]], ptr [[RETVAL]], align 4 | ||||
| // CHECK5-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR6]] | // CHECK5-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR5]] | ||||
| // CHECK5-NEXT: [[TMP33:%.*]] = load i32, ptr [[RETVAL]], align 4 | // CHECK5-NEXT: [[TMP33:%.*]] = load i32, ptr [[RETVAL]], align 4 | ||||
| // CHECK5-NEXT: ret i32 [[TMP33]] | // CHECK5-NEXT: ret i32 [[TMP33]] | ||||
| // CHECK5: eh.resume: | // CHECK5: eh.resume: | ||||
| // CHECK5-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8 | // CHECK5-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8 | ||||
| // CHECK5-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4 | // CHECK5-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4 | ||||
| // CHECK5-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0 | // CHECK5-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0 | ||||
| // CHECK5-NEXT: [[LPAD_VAL10:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1 | // CHECK5-NEXT: [[LPAD_VAL10:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1 | ||||
| // CHECK5-NEXT: resume { ptr, i32 } [[LPAD_VAL10]] | // CHECK5-NEXT: resume { ptr, i32 } [[LPAD_VAL10]] | ||||
| ▲ Show 20 Lines • Show All 143 Lines • ▼ Show 20 Lines | |||||
| // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 | // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 | ||||
| // CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] | // CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] | ||||
| // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | ||||
| // CHECK5: omp.inner.for.body: | // CHECK5: omp.inner.for.body: | ||||
| // CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | // CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | ||||
| // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 | // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 | ||||
| // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | ||||
| // CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4 | // CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4 | ||||
| // CHECK5-NEXT: invoke void @_Z3foov() | // CHECK5-NEXT: call unwindabort void @_Z3foov() | ||||
| // CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] | |||||
| // CHECK5: invoke.cont: | |||||
| // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | ||||
| // CHECK5: omp.body.continue: | // CHECK5: omp.body.continue: | ||||
| // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | ||||
| // CHECK5: omp.inner.for.inc: | // CHECK5: omp.inner.for.inc: | ||||
| // CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | // CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | ||||
| // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 | // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 | ||||
| // CHECK5-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4 | // CHECK5-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4 | ||||
| // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] | // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] | ||||
| // CHECK5: omp.inner.for.end: | // CHECK5: omp.inner.for.end: | ||||
| // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | ||||
| // CHECK5: omp.loop.exit: | // CHECK5: omp.loop.exit: | ||||
| // CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) | // CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) | ||||
| // CHECK5-NEXT: ret void | // CHECK5-NEXT: ret void | ||||
| // CHECK5: terminate.lpad: | |||||
| // CHECK5-NEXT: [[TMP11:%.*]] = landingpad { ptr, i32 } | |||||
| // CHECK5-NEXT: catch ptr null | |||||
| // CHECK5-NEXT: [[TMP12:%.*]] = extractvalue { ptr, i32 } [[TMP11]], 0 | |||||
| // CHECK5-NEXT: call void @__clang_call_terminate(ptr [[TMP12]]) #[[ATTR10:[0-9]+]] | |||||
| // CHECK5-NEXT: unreachable | |||||
| // | |||||
| // | |||||
| // CHECK5-LABEL: define {{[^@]+}}@__clang_call_terminate | |||||
| // CHECK5-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR5:[0-9]+]] comdat { | |||||
| // CHECK5-NEXT: [[TMP2:%.*]] = call ptr @__cxa_begin_catch(ptr [[TMP0]]) #[[ATTR6]] | |||||
| // CHECK5-NEXT: call void @_ZSt9terminatev() #[[ATTR10]] | |||||
| // CHECK5-NEXT: unreachable | |||||
| // | // | ||||
| // | // | ||||
| // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74 | // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74 | ||||
| // CHECK5-SAME: (i64 noundef [[A:%.*]]) #[[ATTR3]] { | // CHECK5-SAME: (i64 noundef [[A:%.*]]) #[[ATTR3]] { | ||||
| // CHECK5-NEXT: entry: | // CHECK5-NEXT: entry: | ||||
| // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK5-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 | // CHECK5-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 | ||||
| // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 1, ptr @.omp_outlined..2, ptr [[A_ADDR]]) | // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 1, ptr @.omp_outlined..2, ptr [[A_ADDR]]) | ||||
| ▲ Show 20 Lines • Show All 116 Lines • ▼ Show 20 Lines | |||||
| // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 | // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 | ||||
| // CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] | // CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] | ||||
| // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | ||||
| // CHECK5: omp.inner.for.body: | // CHECK5: omp.inner.for.body: | ||||
| // CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | // CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | ||||
| // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 | // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 | ||||
| // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | ||||
| // CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4 | // CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4 | ||||
| // CHECK5-NEXT: invoke void @_Z3foov() | // CHECK5-NEXT: call unwindabort void @_Z3foov() | ||||
| // CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] | |||||
| // CHECK5: invoke.cont: | |||||
| // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | ||||
| // CHECK5: omp.body.continue: | // CHECK5: omp.body.continue: | ||||
| // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | ||||
| // CHECK5: omp.inner.for.inc: | // CHECK5: omp.inner.for.inc: | ||||
| // CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | // CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | ||||
| // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 | // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 | ||||
| // CHECK5-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4 | // CHECK5-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4 | ||||
| // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] | // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] | ||||
| // CHECK5: omp.inner.for.end: | // CHECK5: omp.inner.for.end: | ||||
| // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | ||||
| // CHECK5: omp.loop.exit: | // CHECK5: omp.loop.exit: | ||||
| // CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) | // CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) | ||||
| // CHECK5-NEXT: ret void | // CHECK5-NEXT: ret void | ||||
| // CHECK5: terminate.lpad: | |||||
| // CHECK5-NEXT: [[TMP11:%.*]] = landingpad { ptr, i32 } | |||||
| // CHECK5-NEXT: catch ptr null | |||||
| // CHECK5-NEXT: [[TMP12:%.*]] = extractvalue { ptr, i32 } [[TMP11]], 0 | |||||
| // CHECK5-NEXT: call void @__clang_call_terminate(ptr [[TMP12]]) #[[ATTR10]] | |||||
| // CHECK5-NEXT: unreachable | |||||
| // | // | ||||
| // | // | ||||
| // CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIcLi5EEiv | // CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIcLi5EEiv | ||||
| // CHECK5-SAME: () #[[ATTR7:[0-9]+]] comdat { | // CHECK5-SAME: () #[[ATTR6:[0-9]+]] comdat { | ||||
| // CHECK5-NEXT: entry: | // CHECK5-NEXT: entry: | ||||
| // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 | // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 | ||||
| // CHECK5-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 | // CHECK5-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 | ||||
| // CHECK5-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 | // CHECK5-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 | ||||
| // CHECK5-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 | // CHECK5-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 | ||||
| // CHECK5-NEXT: store i32 1, ptr [[TMP0]], align 4 | // CHECK5-NEXT: store i32 1, ptr [[TMP0]], align 4 | ||||
| // CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 | // CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 | ||||
| // CHECK5-NEXT: store i32 0, ptr [[TMP1]], align 4 | // CHECK5-NEXT: store i32 0, ptr [[TMP1]], align 4 | ||||
| Show All 10 Lines | |||||
| // CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 | // CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 | ||||
| // CHECK5-NEXT: store ptr null, ptr [[TMP7]], align 8 | // CHECK5-NEXT: store ptr null, ptr [[TMP7]], align 8 | ||||
| // CHECK5-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 | // CHECK5-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 | ||||
| // CHECK5-NEXT: store i64 100, ptr [[TMP8]], align 8 | // CHECK5-NEXT: store i64 100, ptr [[TMP8]], align 8 | ||||
| // CHECK5-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l52.region_id, ptr [[KERNEL_ARGS]]) | // CHECK5-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l52.region_id, ptr [[KERNEL_ARGS]]) | ||||
| // CHECK5-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 | // CHECK5-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 | ||||
| // CHECK5-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] | // CHECK5-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] | ||||
| // CHECK5: omp_offload.failed: | // CHECK5: omp_offload.failed: | ||||
| // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l52() #[[ATTR6]] | // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l52() #[[ATTR5]] | ||||
| // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] | // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] | ||||
| // CHECK5: omp_offload.cont: | // CHECK5: omp_offload.cont: | ||||
| // CHECK5-NEXT: [[KERNEL_ARGS2:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 | // CHECK5-NEXT: [[KERNEL_ARGS2:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 | ||||
| // CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 0 | // CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 0 | ||||
| // CHECK5-NEXT: store i32 1, ptr [[TMP11]], align 4 | // CHECK5-NEXT: store i32 1, ptr [[TMP11]], align 4 | ||||
| // CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 1 | // CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 1 | ||||
| // CHECK5-NEXT: store i32 0, ptr [[TMP12]], align 4 | // CHECK5-NEXT: store i32 0, ptr [[TMP12]], align 4 | ||||
| // CHECK5-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 2 | // CHECK5-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 2 | ||||
| Show All 9 Lines | |||||
| // CHECK5-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 7 | // CHECK5-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 7 | ||||
| // CHECK5-NEXT: store ptr null, ptr [[TMP18]], align 8 | // CHECK5-NEXT: store ptr null, ptr [[TMP18]], align 8 | ||||
| // CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 8 | // CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 8 | ||||
| // CHECK5-NEXT: store i64 100, ptr [[TMP19]], align 8 | // CHECK5-NEXT: store i64 100, ptr [[TMP19]], align 8 | ||||
| // CHECK5-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l57.region_id, ptr [[KERNEL_ARGS2]]) | // CHECK5-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l57.region_id, ptr [[KERNEL_ARGS2]]) | ||||
| // CHECK5-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 | // CHECK5-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 | ||||
| // CHECK5-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]] | // CHECK5-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]] | ||||
| // CHECK5: omp_offload.failed3: | // CHECK5: omp_offload.failed3: | ||||
| // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l57() #[[ATTR6]] | // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l57() #[[ATTR5]] | ||||
| // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT4]] | // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT4]] | ||||
| // CHECK5: omp_offload.cont4: | // CHECK5: omp_offload.cont4: | ||||
| // CHECK5-NEXT: ret i32 0 | // CHECK5-NEXT: ret i32 0 | ||||
| // | // | ||||
| // | // | ||||
| // CHECK5-LABEL: define {{[^@]+}}@_Z5tmainI1SLi1EEiv | // CHECK5-LABEL: define {{[^@]+}}@_Z5tmainI1SLi1EEiv | ||||
| // CHECK5-SAME: () #[[ATTR7]] comdat { | // CHECK5-SAME: () #[[ATTR6]] comdat { | ||||
| // CHECK5-NEXT: entry: | // CHECK5-NEXT: entry: | ||||
| // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 | // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 | ||||
| // CHECK5-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 | // CHECK5-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 | ||||
| // CHECK5-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 | // CHECK5-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 | ||||
| // CHECK5-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 | // CHECK5-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 | ||||
| // CHECK5-NEXT: store i32 1, ptr [[TMP0]], align 4 | // CHECK5-NEXT: store i32 1, ptr [[TMP0]], align 4 | ||||
| // CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 | // CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 | ||||
| // CHECK5-NEXT: store i32 0, ptr [[TMP1]], align 4 | // CHECK5-NEXT: store i32 0, ptr [[TMP1]], align 4 | ||||
| Show All 10 Lines | |||||
| // CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 | // CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 | ||||
| // CHECK5-NEXT: store ptr null, ptr [[TMP7]], align 8 | // CHECK5-NEXT: store ptr null, ptr [[TMP7]], align 8 | ||||
| // CHECK5-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 | // CHECK5-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 | ||||
| // CHECK5-NEXT: store i64 100, ptr [[TMP8]], align 8 | // CHECK5-NEXT: store i64 100, ptr [[TMP8]], align 8 | ||||
| // CHECK5-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l52.region_id, ptr [[KERNEL_ARGS]]) | // CHECK5-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l52.region_id, ptr [[KERNEL_ARGS]]) | ||||
| // CHECK5-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 | // CHECK5-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 | ||||
| // CHECK5-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] | // CHECK5-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] | ||||
| // CHECK5: omp_offload.failed: | // CHECK5: omp_offload.failed: | ||||
| // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l52() #[[ATTR6]] | // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l52() #[[ATTR5]] | ||||
| // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] | // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] | ||||
| // CHECK5: omp_offload.cont: | // CHECK5: omp_offload.cont: | ||||
| // CHECK5-NEXT: [[KERNEL_ARGS2:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 | // CHECK5-NEXT: [[KERNEL_ARGS2:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 | ||||
| // CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 0 | // CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 0 | ||||
| // CHECK5-NEXT: store i32 1, ptr [[TMP11]], align 4 | // CHECK5-NEXT: store i32 1, ptr [[TMP11]], align 4 | ||||
| // CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 1 | // CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 1 | ||||
| // CHECK5-NEXT: store i32 0, ptr [[TMP12]], align 4 | // CHECK5-NEXT: store i32 0, ptr [[TMP12]], align 4 | ||||
| // CHECK5-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 2 | // CHECK5-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 2 | ||||
| Show All 9 Lines | |||||
| // CHECK5-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 7 | // CHECK5-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 7 | ||||
| // CHECK5-NEXT: store ptr null, ptr [[TMP18]], align 8 | // CHECK5-NEXT: store ptr null, ptr [[TMP18]], align 8 | ||||
| // CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 8 | // CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 8 | ||||
| // CHECK5-NEXT: store i64 100, ptr [[TMP19]], align 8 | // CHECK5-NEXT: store i64 100, ptr [[TMP19]], align 8 | ||||
| // CHECK5-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l57.region_id, ptr [[KERNEL_ARGS2]]) | // CHECK5-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l57.region_id, ptr [[KERNEL_ARGS2]]) | ||||
| // CHECK5-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 | // CHECK5-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 | ||||
| // CHECK5-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]] | // CHECK5-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]] | ||||
| // CHECK5: omp_offload.failed3: | // CHECK5: omp_offload.failed3: | ||||
| // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l57() #[[ATTR6]] | // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l57() #[[ATTR5]] | ||||
| // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT4]] | // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT4]] | ||||
| // CHECK5: omp_offload.cont4: | // CHECK5: omp_offload.cont4: | ||||
| // CHECK5-NEXT: ret i32 0 | // CHECK5-NEXT: ret i32 0 | ||||
| // | // | ||||
| // | // | ||||
| // CHECK5-LABEL: define {{[^@]+}}@_ZN1SD1Ev | // CHECK5-LABEL: define {{[^@]+}}@_ZN1SD1Ev | ||||
| // CHECK5-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR8:[0-9]+]] comdat align 2 { | // CHECK5-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR7:[0-9]+]] comdat align 2 { | ||||
| // CHECK5-NEXT: entry: | // CHECK5-NEXT: entry: | ||||
| // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 | // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 | ||||
| // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 | // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 | ||||
| // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 | // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 | ||||
| // CHECK5-NEXT: call void @_ZN1SD2Ev(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR6]] | // CHECK5-NEXT: call void @_ZN1SD2Ev(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR5]] | ||||
| // CHECK5-NEXT: ret void | // CHECK5-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK5-LABEL: define {{[^@]+}}@_ZN1SC2El | // CHECK5-LABEL: define {{[^@]+}}@_ZN1SC2El | ||||
| // CHECK5-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR8]] comdat align 2 { | // CHECK5-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR7]] comdat align 2 { | ||||
| // CHECK5-NEXT: entry: | // CHECK5-NEXT: entry: | ||||
| // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 | // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 | ||||
| // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 | // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 | ||||
| // CHECK5-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 | // CHECK5-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 | ||||
| // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 | // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 | ||||
| // CHECK5-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 | // CHECK5-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 | ||||
| // CHECK5-NEXT: [[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8 | // CHECK5-NEXT: [[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8 | ||||
| ▲ Show 20 Lines • Show All 119 Lines • ▼ Show 20 Lines | |||||
| // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 | // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 | ||||
| // CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] | // CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] | ||||
| // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | ||||
| // CHECK5: omp.inner.for.body: | // CHECK5: omp.inner.for.body: | ||||
| // CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | // CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | ||||
| // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 | // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 | ||||
| // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | ||||
| // CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4 | // CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4 | ||||
| // CHECK5-NEXT: invoke void @_Z3foov() | // CHECK5-NEXT: call unwindabort void @_Z3foov() | ||||
| // CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] | |||||
| // CHECK5: invoke.cont: | |||||
| // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | ||||
| // CHECK5: omp.body.continue: | // CHECK5: omp.body.continue: | ||||
| // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | ||||
| // CHECK5: omp.inner.for.inc: | // CHECK5: omp.inner.for.inc: | ||||
| // CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | // CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | ||||
| // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 | // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 | ||||
| // CHECK5-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4 | // CHECK5-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4 | ||||
| // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] | // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] | ||||
| // CHECK5: omp.inner.for.end: | // CHECK5: omp.inner.for.end: | ||||
| // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | ||||
| // CHECK5: omp.loop.exit: | // CHECK5: omp.loop.exit: | ||||
| // CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) | // CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) | ||||
| // CHECK5-NEXT: ret void | // CHECK5-NEXT: ret void | ||||
| // CHECK5: terminate.lpad: | |||||
| // CHECK5-NEXT: [[TMP11:%.*]] = landingpad { ptr, i32 } | |||||
| // CHECK5-NEXT: catch ptr null | |||||
| // CHECK5-NEXT: [[TMP12:%.*]] = extractvalue { ptr, i32 } [[TMP11]], 0 | |||||
| // CHECK5-NEXT: call void @__clang_call_terminate(ptr [[TMP12]]) #[[ATTR10]] | |||||
| // CHECK5-NEXT: unreachable | |||||
| // | // | ||||
| // | // | ||||
| // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l57 | // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l57 | ||||
| // CHECK5-SAME: () #[[ATTR3]] { | // CHECK5-SAME: () #[[ATTR3]] { | ||||
| // CHECK5-NEXT: entry: | // CHECK5-NEXT: entry: | ||||
| // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @.omp_outlined..6) | // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @.omp_outlined..6) | ||||
| // CHECK5-NEXT: ret void | // CHECK5-NEXT: ret void | ||||
| // | // | ||||
| ▲ Show 20 Lines • Show All 109 Lines • ▼ Show 20 Lines | |||||
| // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 | // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 | ||||
| // CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] | // CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] | ||||
| // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | ||||
| // CHECK5: omp.inner.for.body: | // CHECK5: omp.inner.for.body: | ||||
| // CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | // CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | ||||
| // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 | // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 | ||||
| // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | ||||
| // CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4 | // CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4 | ||||
| // CHECK5-NEXT: invoke void @_Z3foov() | // CHECK5-NEXT: call unwindabort void @_Z3foov() | ||||
| // CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] | |||||
| // CHECK5: invoke.cont: | |||||
| // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | ||||
| // CHECK5: omp.body.continue: | // CHECK5: omp.body.continue: | ||||
| // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | ||||
| // CHECK5: omp.inner.for.inc: | // CHECK5: omp.inner.for.inc: | ||||
| // CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | // CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | ||||
| // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 | // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 | ||||
| // CHECK5-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4 | // CHECK5-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4 | ||||
| // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] | // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] | ||||
| // CHECK5: omp.inner.for.end: | // CHECK5: omp.inner.for.end: | ||||
| // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | ||||
| // CHECK5: omp.loop.exit: | // CHECK5: omp.loop.exit: | ||||
| // CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) | // CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) | ||||
| // CHECK5-NEXT: ret void | // CHECK5-NEXT: ret void | ||||
| // CHECK5: terminate.lpad: | |||||
| // CHECK5-NEXT: [[TMP11:%.*]] = landingpad { ptr, i32 } | |||||
| // CHECK5-NEXT: catch ptr null | |||||
| // CHECK5-NEXT: [[TMP12:%.*]] = extractvalue { ptr, i32 } [[TMP11]], 0 | |||||
| // CHECK5-NEXT: call void @__clang_call_terminate(ptr [[TMP12]]) #[[ATTR10]] | |||||
| // CHECK5-NEXT: unreachable | |||||
| // | // | ||||
| // | // | ||||
| // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l52 | // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l52 | ||||
| // CHECK5-SAME: () #[[ATTR3]] { | // CHECK5-SAME: () #[[ATTR3]] { | ||||
| // CHECK5-NEXT: entry: | // CHECK5-NEXT: entry: | ||||
| // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @.omp_outlined..8) | // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @.omp_outlined..8) | ||||
| // CHECK5-NEXT: ret void | // CHECK5-NEXT: ret void | ||||
| // | // | ||||
| ▲ Show 20 Lines • Show All 109 Lines • ▼ Show 20 Lines | |||||
| // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 | // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 | ||||
| // CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] | // CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] | ||||
| // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | ||||
| // CHECK5: omp.inner.for.body: | // CHECK5: omp.inner.for.body: | ||||
| // CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | // CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | ||||
| // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 | // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 | ||||
| // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | ||||
| // CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4 | // CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4 | ||||
| // CHECK5-NEXT: invoke void @_Z3foov() | // CHECK5-NEXT: call unwindabort void @_Z3foov() | ||||
| // CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] | |||||
| // CHECK5: invoke.cont: | |||||
| // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | ||||
| // CHECK5: omp.body.continue: | // CHECK5: omp.body.continue: | ||||
| // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | ||||
| // CHECK5: omp.inner.for.inc: | // CHECK5: omp.inner.for.inc: | ||||
| // CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | // CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | ||||
| // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 | // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 | ||||
| // CHECK5-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4 | // CHECK5-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4 | ||||
| // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] | // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] | ||||
| // CHECK5: omp.inner.for.end: | // CHECK5: omp.inner.for.end: | ||||
| // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | ||||
| // CHECK5: omp.loop.exit: | // CHECK5: omp.loop.exit: | ||||
| // CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) | // CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) | ||||
| // CHECK5-NEXT: ret void | // CHECK5-NEXT: ret void | ||||
| // CHECK5: terminate.lpad: | |||||
| // CHECK5-NEXT: [[TMP11:%.*]] = landingpad { ptr, i32 } | |||||
| // CHECK5-NEXT: catch ptr null | |||||
| // CHECK5-NEXT: [[TMP12:%.*]] = extractvalue { ptr, i32 } [[TMP11]], 0 | |||||
| // CHECK5-NEXT: call void @__clang_call_terminate(ptr [[TMP12]]) #[[ATTR10]] | |||||
| // CHECK5-NEXT: unreachable | |||||
| // | // | ||||
| // | // | ||||
| // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l57 | // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l57 | ||||
| // CHECK5-SAME: () #[[ATTR3]] { | // CHECK5-SAME: () #[[ATTR3]] { | ||||
| // CHECK5-NEXT: entry: | // CHECK5-NEXT: entry: | ||||
| // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @.omp_outlined..10) | // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @.omp_outlined..10) | ||||
| // CHECK5-NEXT: ret void | // CHECK5-NEXT: ret void | ||||
| // | // | ||||
| Show All 35 Lines | |||||
| // CHECK5-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 | // CHECK5-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 | ||||
| // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] | // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] | ||||
| // CHECK5: omp.inner.for.cond: | // CHECK5: omp.inner.for.cond: | ||||
| // CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | // CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | ||||
| // CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 | // CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 | ||||
| // CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] | // CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] | ||||
| // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | ||||
| // CHECK5: omp.inner.for.body: | // CHECK5: omp.inner.for.body: | ||||
| // CHECK5-NEXT: invoke void @_ZN1SC1El(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]], i64 noundef 23) | // CHECK5-NEXT: call unwindabort void @_ZN1SC1El(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]], i64 noundef 23) | ||||
| // CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] | // CHECK5-NEXT: [[CALL:%.*]] = call unwindabort noundef signext i8 @_ZN1ScvcEv(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) | ||||
| // CHECK5: invoke.cont: | |||||
| // CHECK5-NEXT: [[CALL:%.*]] = invoke noundef signext i8 @_ZN1ScvcEv(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) | |||||
| // CHECK5-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[TERMINATE_LPAD]] | |||||
| // CHECK5: invoke.cont2: | |||||
| // CHECK5-NEXT: [[TMP7:%.*]] = sext i8 [[CALL]] to i32 | // CHECK5-NEXT: [[TMP7:%.*]] = sext i8 [[CALL]] to i32 | ||||
| // CHECK5-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP1]], i32 [[TMP7]]) | // CHECK5-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP1]], i32 [[TMP7]]) | ||||
| // CHECK5-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]] | // CHECK5-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR5]] | ||||
| // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 | // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 | ||||
| // CHECK5-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 | // CHECK5-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 | ||||
| // CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 | // CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 | ||||
| // CHECK5-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 | // CHECK5-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 | ||||
| // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @.omp_outlined..11, i64 [[TMP9]], i64 [[TMP11]]) | // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @.omp_outlined..11, i64 [[TMP9]], i64 [[TMP11]]) | ||||
| // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | ||||
| // CHECK5: omp.inner.for.inc: | // CHECK5: omp.inner.for.inc: | ||||
| // CHECK5-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | // CHECK5-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | ||||
| // CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 | // CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 | ||||
| // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] | // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] | ||||
| // CHECK5-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 | // CHECK5-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 | ||||
| // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] | // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] | ||||
| // CHECK5: omp.inner.for.end: | // CHECK5: omp.inner.for.end: | ||||
| // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | ||||
| // CHECK5: omp.loop.exit: | // CHECK5: omp.loop.exit: | ||||
| // CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) | // CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) | ||||
| // CHECK5-NEXT: ret void | // CHECK5-NEXT: ret void | ||||
| // CHECK5: terminate.lpad: | |||||
| // CHECK5-NEXT: [[TMP14:%.*]] = landingpad { ptr, i32 } | |||||
| // CHECK5-NEXT: catch ptr null | |||||
| // CHECK5-NEXT: [[TMP15:%.*]] = extractvalue { ptr, i32 } [[TMP14]], 0 | |||||
| // CHECK5-NEXT: call void @__clang_call_terminate(ptr [[TMP15]]) #[[ATTR10]] | |||||
| // CHECK5-NEXT: unreachable | |||||
| // | // | ||||
| // | // | ||||
| // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..11 | // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..11 | ||||
| // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality ptr @__gxx_personality_v0 { | // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality ptr @__gxx_personality_v0 { | ||||
| // CHECK5-NEXT: entry: | // CHECK5-NEXT: entry: | ||||
| // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 | // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 | ||||
| // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 | // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 | ||||
| // CHECK5-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 | // CHECK5-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 | ||||
| ▲ Show 20 Lines • Show All 41 Lines • ▼ Show 20 Lines | |||||
| // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 | // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 | ||||
| // CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] | // CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] | ||||
| // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | ||||
| // CHECK5: omp.inner.for.body: | // CHECK5: omp.inner.for.body: | ||||
| // CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | // CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | ||||
| // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 | // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 | ||||
| // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | ||||
| // CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4 | // CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4 | ||||
| // CHECK5-NEXT: invoke void @_Z3foov() | // CHECK5-NEXT: call unwindabort void @_Z3foov() | ||||
| // CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] | |||||
| // CHECK5: invoke.cont: | |||||
| // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | ||||
| // CHECK5: omp.body.continue: | // CHECK5: omp.body.continue: | ||||
| // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | ||||
| // CHECK5: omp.inner.for.inc: | // CHECK5: omp.inner.for.inc: | ||||
| // CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | // CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | ||||
| // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 | // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 | ||||
| // CHECK5-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4 | // CHECK5-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4 | ||||
| // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] | // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] | ||||
| // CHECK5: omp.inner.for.end: | // CHECK5: omp.inner.for.end: | ||||
| // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | ||||
| // CHECK5: omp.loop.exit: | // CHECK5: omp.loop.exit: | ||||
| // CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) | // CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) | ||||
| // CHECK5-NEXT: ret void | // CHECK5-NEXT: ret void | ||||
| // CHECK5: terminate.lpad: | |||||
| // CHECK5-NEXT: [[TMP11:%.*]] = landingpad { ptr, i32 } | |||||
| // CHECK5-NEXT: catch ptr null | |||||
| // CHECK5-NEXT: [[TMP12:%.*]] = extractvalue { ptr, i32 } [[TMP11]], 0 | |||||
| // CHECK5-NEXT: call void @__clang_call_terminate(ptr [[TMP12]]) #[[ATTR10]] | |||||
| // CHECK5-NEXT: unreachable | |||||
| // | // | ||||
| // | // | ||||
| // CHECK5-LABEL: define {{[^@]+}}@_ZN1SD2Ev | // CHECK5-LABEL: define {{[^@]+}}@_ZN1SD2Ev | ||||
| // CHECK5-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR8]] comdat align 2 { | // CHECK5-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR7]] comdat align 2 { | ||||
| // CHECK5-NEXT: entry: | // CHECK5-NEXT: entry: | ||||
| // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 | // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 | ||||
| // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 | // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 | ||||
| // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 | // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 | ||||
| // CHECK5-NEXT: ret void | // CHECK5-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK5-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg | // CHECK5-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg | ||||
| // CHECK5-SAME: () #[[ATTR9:[0-9]+]] { | // CHECK5-SAME: () #[[ATTR8:[0-9]+]] { | ||||
| // CHECK5-NEXT: entry: | // CHECK5-NEXT: entry: | ||||
| // CHECK5-NEXT: call void @__tgt_register_requires(i64 1) | // CHECK5-NEXT: call void @__tgt_register_requires(i64 1) | ||||
| // CHECK5-NEXT: ret void | // CHECK5-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK9-LABEL: define {{[^@]+}}@main | // CHECK9-LABEL: define {{[^@]+}}@main | ||||
| // CHECK9-SAME: () #[[ATTR0:[0-9]+]] personality ptr @__gxx_personality_v0 { | // CHECK9-SAME: () #[[ATTR0:[0-9]+]] personality ptr @__gxx_personality_v0 { | ||||
| // CHECK9-NEXT: entry: | // CHECK9-NEXT: entry: | ||||
| Show All 32 Lines | |||||
| // CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 | // CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 | ||||
| // CHECK9-NEXT: store ptr null, ptr [[TMP7]], align 8 | // CHECK9-NEXT: store ptr null, ptr [[TMP7]], align 8 | ||||
| // CHECK9-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 | // CHECK9-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 | ||||
| // CHECK9-NEXT: store i64 100, ptr [[TMP8]], align 8 | // CHECK9-NEXT: store i64 100, ptr [[TMP8]], align 8 | ||||
| // CHECK9-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.region_id, ptr [[KERNEL_ARGS]]) | // CHECK9-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.region_id, ptr [[KERNEL_ARGS]]) | ||||
| // CHECK9-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 | // CHECK9-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 | ||||
| // CHECK9-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] | // CHECK9-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] | ||||
| // CHECK9: omp_offload.failed: | // CHECK9: omp_offload.failed: | ||||
| // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68() #[[ATTR6:[0-9]+]] | // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68() #[[ATTR5:[0-9]+]] | ||||
| // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] | // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] | ||||
| // CHECK9: lpad: | // CHECK9: lpad: | ||||
| // CHECK9-NEXT: [[TMP11:%.*]] = landingpad { ptr, i32 } | // CHECK9-NEXT: [[TMP11:%.*]] = landingpad { ptr, i32 } | ||||
| // CHECK9-NEXT: cleanup | // CHECK9-NEXT: cleanup | ||||
| // CHECK9-NEXT: [[TMP12:%.*]] = extractvalue { ptr, i32 } [[TMP11]], 0 | // CHECK9-NEXT: [[TMP12:%.*]] = extractvalue { ptr, i32 } [[TMP11]], 0 | ||||
| // CHECK9-NEXT: store ptr [[TMP12]], ptr [[EXN_SLOT]], align 8 | // CHECK9-NEXT: store ptr [[TMP12]], ptr [[EXN_SLOT]], align 8 | ||||
| // CHECK9-NEXT: [[TMP13:%.*]] = extractvalue { ptr, i32 } [[TMP11]], 1 | // CHECK9-NEXT: [[TMP13:%.*]] = extractvalue { ptr, i32 } [[TMP11]], 1 | ||||
| // CHECK9-NEXT: store i32 [[TMP13]], ptr [[EHSELECTOR_SLOT]], align 4 | // CHECK9-NEXT: store i32 [[TMP13]], ptr [[EHSELECTOR_SLOT]], align 4 | ||||
| // CHECK9-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR6]] | // CHECK9-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR5]] | ||||
| // CHECK9-NEXT: br label [[EH_RESUME:%.*]] | // CHECK9-NEXT: br label [[EH_RESUME:%.*]] | ||||
| // CHECK9: omp_offload.cont: | // CHECK9: omp_offload.cont: | ||||
| // CHECK9-NEXT: [[TMP14:%.*]] = load i8, ptr [[A]], align 1 | // CHECK9-NEXT: [[TMP14:%.*]] = load i8, ptr [[A]], align 1 | ||||
| // CHECK9-NEXT: store i8 [[TMP14]], ptr [[A_CASTED]], align 1 | // CHECK9-NEXT: store i8 [[TMP14]], ptr [[A_CASTED]], align 1 | ||||
| // CHECK9-NEXT: [[TMP15:%.*]] = load i64, ptr [[A_CASTED]], align 8 | // CHECK9-NEXT: [[TMP15:%.*]] = load i64, ptr [[A_CASTED]], align 8 | ||||
| // CHECK9-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 | // CHECK9-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 | ||||
| // CHECK9-NEXT: store i64 [[TMP15]], ptr [[TMP16]], align 8 | // CHECK9-NEXT: store i64 [[TMP15]], ptr [[TMP16]], align 8 | ||||
| // CHECK9-NEXT: [[TMP17:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 | // CHECK9-NEXT: [[TMP17:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 | ||||
| Show All 20 Lines | |||||
| // CHECK9-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 7 | // CHECK9-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 7 | ||||
| // CHECK9-NEXT: store ptr null, ptr [[TMP28]], align 8 | // CHECK9-NEXT: store ptr null, ptr [[TMP28]], align 8 | ||||
| // CHECK9-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 8 | // CHECK9-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 8 | ||||
| // CHECK9-NEXT: store i64 100, ptr [[TMP29]], align 8 | // CHECK9-NEXT: store i64 100, ptr [[TMP29]], align 8 | ||||
| // CHECK9-NEXT: [[TMP30:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74.region_id, ptr [[KERNEL_ARGS2]]) | // CHECK9-NEXT: [[TMP30:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74.region_id, ptr [[KERNEL_ARGS2]]) | ||||
| // CHECK9-NEXT: [[TMP31:%.*]] = icmp ne i32 [[TMP30]], 0 | // CHECK9-NEXT: [[TMP31:%.*]] = icmp ne i32 [[TMP30]], 0 | ||||
| // CHECK9-NEXT: br i1 [[TMP31]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]] | // CHECK9-NEXT: br i1 [[TMP31]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]] | ||||
| // CHECK9: omp_offload.failed3: | // CHECK9: omp_offload.failed3: | ||||
| // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74(i64 [[TMP15]]) #[[ATTR6]] | // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74(i64 [[TMP15]]) #[[ATTR5]] | ||||
| // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT4]] | // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT4]] | ||||
| // CHECK9: omp_offload.cont4: | // CHECK9: omp_offload.cont4: | ||||
| // CHECK9-NEXT: [[TMP32:%.*]] = load i8, ptr [[A]], align 1 | // CHECK9-NEXT: [[TMP32:%.*]] = load i8, ptr [[A]], align 1 | ||||
| // CHECK9-NEXT: [[CONV:%.*]] = sext i8 [[TMP32]] to i32 | // CHECK9-NEXT: [[CONV:%.*]] = sext i8 [[TMP32]] to i32 | ||||
| // CHECK9-NEXT: [[CALL6:%.*]] = invoke noundef i32 @_Z5tmainIcLi5EEiv() | // CHECK9-NEXT: [[CALL6:%.*]] = invoke noundef i32 @_Z5tmainIcLi5EEiv() | ||||
| // CHECK9-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[LPAD]] | // CHECK9-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[LPAD]] | ||||
| // CHECK9: invoke.cont5: | // CHECK9: invoke.cont5: | ||||
| // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], [[CALL6]] | // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], [[CALL6]] | ||||
| // CHECK9-NEXT: [[CALL8:%.*]] = invoke noundef i32 @_Z5tmainI1SLi1EEiv() | // CHECK9-NEXT: [[CALL8:%.*]] = invoke noundef i32 @_Z5tmainI1SLi1EEiv() | ||||
| // CHECK9-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD]] | // CHECK9-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD]] | ||||
| // CHECK9: invoke.cont7: | // CHECK9: invoke.cont7: | ||||
| // CHECK9-NEXT: [[ADD9:%.*]] = add nsw i32 [[ADD]], [[CALL8]] | // CHECK9-NEXT: [[ADD9:%.*]] = add nsw i32 [[ADD]], [[CALL8]] | ||||
| // CHECK9-NEXT: store i32 [[ADD9]], ptr [[RETVAL]], align 4 | // CHECK9-NEXT: store i32 [[ADD9]], ptr [[RETVAL]], align 4 | ||||
| // CHECK9-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR6]] | // CHECK9-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR5]] | ||||
| // CHECK9-NEXT: [[TMP33:%.*]] = load i32, ptr [[RETVAL]], align 4 | // CHECK9-NEXT: [[TMP33:%.*]] = load i32, ptr [[RETVAL]], align 4 | ||||
| // CHECK9-NEXT: ret i32 [[TMP33]] | // CHECK9-NEXT: ret i32 [[TMP33]] | ||||
| // CHECK9: eh.resume: | // CHECK9: eh.resume: | ||||
| // CHECK9-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8 | // CHECK9-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8 | ||||
| // CHECK9-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4 | // CHECK9-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4 | ||||
| // CHECK9-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0 | // CHECK9-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0 | ||||
| // CHECK9-NEXT: [[LPAD_VAL10:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1 | // CHECK9-NEXT: [[LPAD_VAL10:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1 | ||||
| // CHECK9-NEXT: resume { ptr, i32 } [[LPAD_VAL10]] | // CHECK9-NEXT: resume { ptr, i32 } [[LPAD_VAL10]] | ||||
| ▲ Show 20 Lines • Show All 143 Lines • ▼ Show 20 Lines | |||||
| // CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 | // CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 | ||||
| // CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] | // CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] | ||||
| // CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | // CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | ||||
| // CHECK9: omp.inner.for.body: | // CHECK9: omp.inner.for.body: | ||||
| // CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | // CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | ||||
| // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 | // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 | ||||
| // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | ||||
| // CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4 | // CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4 | ||||
| // CHECK9-NEXT: invoke void @_Z3foov() | // CHECK9-NEXT: call unwindabort void @_Z3foov() | ||||
| // CHECK9-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] | |||||
| // CHECK9: invoke.cont: | |||||
| // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | ||||
| // CHECK9: omp.body.continue: | // CHECK9: omp.body.continue: | ||||
| // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | ||||
| // CHECK9: omp.inner.for.inc: | // CHECK9: omp.inner.for.inc: | ||||
| // CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | // CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | ||||
| // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 | // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 | ||||
| // CHECK9-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4 | // CHECK9-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4 | ||||
| // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] | // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] | ||||
| // CHECK9: omp.inner.for.end: | // CHECK9: omp.inner.for.end: | ||||
| // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | ||||
| // CHECK9: omp.loop.exit: | // CHECK9: omp.loop.exit: | ||||
| // CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) | // CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) | ||||
| // CHECK9-NEXT: ret void | // CHECK9-NEXT: ret void | ||||
| // CHECK9: terminate.lpad: | |||||
| // CHECK9-NEXT: [[TMP11:%.*]] = landingpad { ptr, i32 } | |||||
| // CHECK9-NEXT: catch ptr null | |||||
| // CHECK9-NEXT: [[TMP12:%.*]] = extractvalue { ptr, i32 } [[TMP11]], 0 | |||||
| // CHECK9-NEXT: call void @__clang_call_terminate(ptr [[TMP12]]) #[[ATTR10:[0-9]+]] | |||||
| // CHECK9-NEXT: unreachable | |||||
| // | |||||
| // | |||||
| // CHECK9-LABEL: define {{[^@]+}}@__clang_call_terminate | |||||
| // CHECK9-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR5:[0-9]+]] comdat { | |||||
| // CHECK9-NEXT: [[TMP2:%.*]] = call ptr @__cxa_begin_catch(ptr [[TMP0]]) #[[ATTR6]] | |||||
| // CHECK9-NEXT: call void @_ZSt9terminatev() #[[ATTR10]] | |||||
| // CHECK9-NEXT: unreachable | |||||
| // | // | ||||
| // | // | ||||
| // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74 | // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74 | ||||
| // CHECK9-SAME: (i64 noundef [[A:%.*]]) #[[ATTR3]] { | // CHECK9-SAME: (i64 noundef [[A:%.*]]) #[[ATTR3]] { | ||||
| // CHECK9-NEXT: entry: | // CHECK9-NEXT: entry: | ||||
| // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 | // CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 | ||||
| // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 1, ptr @.omp_outlined..2, ptr [[A_ADDR]]) | // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 1, ptr @.omp_outlined..2, ptr [[A_ADDR]]) | ||||
| ▲ Show 20 Lines • Show All 116 Lines • ▼ Show 20 Lines | |||||
| // CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 | // CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 | ||||
| // CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] | // CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] | ||||
| // CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | // CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | ||||
| // CHECK9: omp.inner.for.body: | // CHECK9: omp.inner.for.body: | ||||
| // CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | // CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | ||||
| // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 | // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 | ||||
| // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | ||||
| // CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4 | // CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4 | ||||
| // CHECK9-NEXT: invoke void @_Z3foov() | // CHECK9-NEXT: call unwindabort void @_Z3foov() | ||||
| // CHECK9-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] | |||||
| // CHECK9: invoke.cont: | |||||
| // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | ||||
| // CHECK9: omp.body.continue: | // CHECK9: omp.body.continue: | ||||
| // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | ||||
| // CHECK9: omp.inner.for.inc: | // CHECK9: omp.inner.for.inc: | ||||
| // CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | // CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | ||||
| // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 | // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 | ||||
| // CHECK9-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4 | // CHECK9-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4 | ||||
| // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] | // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] | ||||
| // CHECK9: omp.inner.for.end: | // CHECK9: omp.inner.for.end: | ||||
| // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | ||||
| // CHECK9: omp.loop.exit: | // CHECK9: omp.loop.exit: | ||||
| // CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) | // CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) | ||||
| // CHECK9-NEXT: ret void | // CHECK9-NEXT: ret void | ||||
| // CHECK9: terminate.lpad: | |||||
| // CHECK9-NEXT: [[TMP11:%.*]] = landingpad { ptr, i32 } | |||||
| // CHECK9-NEXT: catch ptr null | |||||
| // CHECK9-NEXT: [[TMP12:%.*]] = extractvalue { ptr, i32 } [[TMP11]], 0 | |||||
| // CHECK9-NEXT: call void @__clang_call_terminate(ptr [[TMP12]]) #[[ATTR10]] | |||||
| // CHECK9-NEXT: unreachable | |||||
| // | // | ||||
| // | // | ||||
| // CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIcLi5EEiv | // CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIcLi5EEiv | ||||
| // CHECK9-SAME: () #[[ATTR7:[0-9]+]] comdat { | // CHECK9-SAME: () #[[ATTR6:[0-9]+]] comdat { | ||||
| // CHECK9-NEXT: entry: | // CHECK9-NEXT: entry: | ||||
| // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 | // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 | ||||
| // CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 | // CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 | ||||
| // CHECK9-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 | // CHECK9-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 | ||||
| // CHECK9-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 | // CHECK9-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 | ||||
| // CHECK9-NEXT: store i32 1, ptr [[TMP0]], align 4 | // CHECK9-NEXT: store i32 1, ptr [[TMP0]], align 4 | ||||
| // CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 | // CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 | ||||
| // CHECK9-NEXT: store i32 0, ptr [[TMP1]], align 4 | // CHECK9-NEXT: store i32 0, ptr [[TMP1]], align 4 | ||||
| Show All 10 Lines | |||||
| // CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 | // CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 | ||||
| // CHECK9-NEXT: store ptr null, ptr [[TMP7]], align 8 | // CHECK9-NEXT: store ptr null, ptr [[TMP7]], align 8 | ||||
| // CHECK9-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 | // CHECK9-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 | ||||
| // CHECK9-NEXT: store i64 100, ptr [[TMP8]], align 8 | // CHECK9-NEXT: store i64 100, ptr [[TMP8]], align 8 | ||||
| // CHECK9-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l52.region_id, ptr [[KERNEL_ARGS]]) | // CHECK9-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l52.region_id, ptr [[KERNEL_ARGS]]) | ||||
| // CHECK9-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 | // CHECK9-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 | ||||
| // CHECK9-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] | // CHECK9-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] | ||||
| // CHECK9: omp_offload.failed: | // CHECK9: omp_offload.failed: | ||||
| // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l52() #[[ATTR6]] | // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l52() #[[ATTR5]] | ||||
| // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] | // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] | ||||
| // CHECK9: omp_offload.cont: | // CHECK9: omp_offload.cont: | ||||
| // CHECK9-NEXT: [[KERNEL_ARGS2:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 | // CHECK9-NEXT: [[KERNEL_ARGS2:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 | ||||
| // CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 0 | // CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 0 | ||||
| // CHECK9-NEXT: store i32 1, ptr [[TMP11]], align 4 | // CHECK9-NEXT: store i32 1, ptr [[TMP11]], align 4 | ||||
| // CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 1 | // CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 1 | ||||
| // CHECK9-NEXT: store i32 0, ptr [[TMP12]], align 4 | // CHECK9-NEXT: store i32 0, ptr [[TMP12]], align 4 | ||||
| // CHECK9-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 2 | // CHECK9-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 2 | ||||
| Show All 9 Lines | |||||
| // CHECK9-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 7 | // CHECK9-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 7 | ||||
| // CHECK9-NEXT: store ptr null, ptr [[TMP18]], align 8 | // CHECK9-NEXT: store ptr null, ptr [[TMP18]], align 8 | ||||
| // CHECK9-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 8 | // CHECK9-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 8 | ||||
| // CHECK9-NEXT: store i64 100, ptr [[TMP19]], align 8 | // CHECK9-NEXT: store i64 100, ptr [[TMP19]], align 8 | ||||
| // CHECK9-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l57.region_id, ptr [[KERNEL_ARGS2]]) | // CHECK9-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l57.region_id, ptr [[KERNEL_ARGS2]]) | ||||
| // CHECK9-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 | // CHECK9-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 | ||||
| // CHECK9-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]] | // CHECK9-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]] | ||||
| // CHECK9: omp_offload.failed3: | // CHECK9: omp_offload.failed3: | ||||
| // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l57() #[[ATTR6]] | // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l57() #[[ATTR5]] | ||||
| // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT4]] | // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT4]] | ||||
| // CHECK9: omp_offload.cont4: | // CHECK9: omp_offload.cont4: | ||||
| // CHECK9-NEXT: ret i32 0 | // CHECK9-NEXT: ret i32 0 | ||||
| // | // | ||||
| // | // | ||||
| // CHECK9-LABEL: define {{[^@]+}}@_Z5tmainI1SLi1EEiv | // CHECK9-LABEL: define {{[^@]+}}@_Z5tmainI1SLi1EEiv | ||||
| // CHECK9-SAME: () #[[ATTR7]] comdat { | // CHECK9-SAME: () #[[ATTR6]] comdat { | ||||
| // CHECK9-NEXT: entry: | // CHECK9-NEXT: entry: | ||||
| // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 | // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 | ||||
| // CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 | // CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 | ||||
| // CHECK9-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 | // CHECK9-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 | ||||
| // CHECK9-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 | // CHECK9-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 | ||||
| // CHECK9-NEXT: store i32 1, ptr [[TMP0]], align 4 | // CHECK9-NEXT: store i32 1, ptr [[TMP0]], align 4 | ||||
| // CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 | // CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 | ||||
| // CHECK9-NEXT: store i32 0, ptr [[TMP1]], align 4 | // CHECK9-NEXT: store i32 0, ptr [[TMP1]], align 4 | ||||
| Show All 10 Lines | |||||
| // CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 | // CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 | ||||
| // CHECK9-NEXT: store ptr null, ptr [[TMP7]], align 8 | // CHECK9-NEXT: store ptr null, ptr [[TMP7]], align 8 | ||||
| // CHECK9-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 | // CHECK9-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 | ||||
| // CHECK9-NEXT: store i64 100, ptr [[TMP8]], align 8 | // CHECK9-NEXT: store i64 100, ptr [[TMP8]], align 8 | ||||
| // CHECK9-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l52.region_id, ptr [[KERNEL_ARGS]]) | // CHECK9-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l52.region_id, ptr [[KERNEL_ARGS]]) | ||||
| // CHECK9-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 | // CHECK9-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 | ||||
| // CHECK9-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] | // CHECK9-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] | ||||
| // CHECK9: omp_offload.failed: | // CHECK9: omp_offload.failed: | ||||
| // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l52() #[[ATTR6]] | // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l52() #[[ATTR5]] | ||||
| // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] | // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] | ||||
| // CHECK9: omp_offload.cont: | // CHECK9: omp_offload.cont: | ||||
| // CHECK9-NEXT: [[KERNEL_ARGS2:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 | // CHECK9-NEXT: [[KERNEL_ARGS2:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 | ||||
| // CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 0 | // CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 0 | ||||
| // CHECK9-NEXT: store i32 1, ptr [[TMP11]], align 4 | // CHECK9-NEXT: store i32 1, ptr [[TMP11]], align 4 | ||||
| // CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 1 | // CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 1 | ||||
| // CHECK9-NEXT: store i32 0, ptr [[TMP12]], align 4 | // CHECK9-NEXT: store i32 0, ptr [[TMP12]], align 4 | ||||
| // CHECK9-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 2 | // CHECK9-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 2 | ||||
| Show All 9 Lines | |||||
| // CHECK9-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 7 | // CHECK9-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 7 | ||||
| // CHECK9-NEXT: store ptr null, ptr [[TMP18]], align 8 | // CHECK9-NEXT: store ptr null, ptr [[TMP18]], align 8 | ||||
| // CHECK9-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 8 | // CHECK9-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 8 | ||||
| // CHECK9-NEXT: store i64 100, ptr [[TMP19]], align 8 | // CHECK9-NEXT: store i64 100, ptr [[TMP19]], align 8 | ||||
| // CHECK9-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l57.region_id, ptr [[KERNEL_ARGS2]]) | // CHECK9-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l57.region_id, ptr [[KERNEL_ARGS2]]) | ||||
| // CHECK9-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 | // CHECK9-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 | ||||
| // CHECK9-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]] | // CHECK9-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]] | ||||
| // CHECK9: omp_offload.failed3: | // CHECK9: omp_offload.failed3: | ||||
| // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l57() #[[ATTR6]] | // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l57() #[[ATTR5]] | ||||
| // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT4]] | // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT4]] | ||||
| // CHECK9: omp_offload.cont4: | // CHECK9: omp_offload.cont4: | ||||
| // CHECK9-NEXT: ret i32 0 | // CHECK9-NEXT: ret i32 0 | ||||
| // | // | ||||
| // | // | ||||
| // CHECK9-LABEL: define {{[^@]+}}@_ZN1SD1Ev | // CHECK9-LABEL: define {{[^@]+}}@_ZN1SD1Ev | ||||
| // CHECK9-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR8:[0-9]+]] comdat align 2 { | // CHECK9-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR7:[0-9]+]] comdat align 2 { | ||||
| // CHECK9-NEXT: entry: | // CHECK9-NEXT: entry: | ||||
| // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 | // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 | ||||
| // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 | // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 | ||||
| // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 | // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 | ||||
| // CHECK9-NEXT: call void @_ZN1SD2Ev(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR6]] | // CHECK9-NEXT: call void @_ZN1SD2Ev(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR5]] | ||||
| // CHECK9-NEXT: ret void | // CHECK9-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK9-LABEL: define {{[^@]+}}@_ZN1SC2El | // CHECK9-LABEL: define {{[^@]+}}@_ZN1SC2El | ||||
| // CHECK9-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR8]] comdat align 2 { | // CHECK9-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR7]] comdat align 2 { | ||||
| // CHECK9-NEXT: entry: | // CHECK9-NEXT: entry: | ||||
| // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 | // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 | ||||
| // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 | // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 | ||||
| // CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 | // CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 | ||||
| // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 | // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 | ||||
| // CHECK9-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 | // CHECK9-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 | ||||
| // CHECK9-NEXT: [[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8 | // CHECK9-NEXT: [[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8 | ||||
| // CHECK9-NEXT: store i64 [[TMP0]], ptr [[A2]], align 8 | // CHECK9-NEXT: store i64 [[TMP0]], ptr [[A2]], align 8 | ||||
| // CHECK9-NEXT: ret void | // CHECK9-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK9-LABEL: define {{[^@]+}}@_ZN1SD2Ev | // CHECK9-LABEL: define {{[^@]+}}@_ZN1SD2Ev | ||||
| // CHECK9-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR8]] comdat align 2 { | // CHECK9-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR7]] comdat align 2 { | ||||
| // CHECK9-NEXT: entry: | // CHECK9-NEXT: entry: | ||||
| // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 | // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 | ||||
| // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 | // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 | ||||
| // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 | // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 | ||||
| // CHECK9-NEXT: ret void | // CHECK9-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l52 | // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l52 | ||||
| ▲ Show 20 Lines • Show All 114 Lines • ▼ Show 20 Lines | |||||
| // CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 | // CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 | ||||
| // CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] | // CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] | ||||
| // CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | // CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | ||||
| // CHECK9: omp.inner.for.body: | // CHECK9: omp.inner.for.body: | ||||
| // CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | // CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | ||||
| // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 | // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 | ||||
| // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | ||||
| // CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4 | // CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4 | ||||
| // CHECK9-NEXT: invoke void @_Z3foov() | // CHECK9-NEXT: call unwindabort void @_Z3foov() | ||||
| // CHECK9-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] | |||||
| // CHECK9: invoke.cont: | |||||
| // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | ||||
| // CHECK9: omp.body.continue: | // CHECK9: omp.body.continue: | ||||
| // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | ||||
| // CHECK9: omp.inner.for.inc: | // CHECK9: omp.inner.for.inc: | ||||
| // CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | // CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | ||||
| // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 | // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 | ||||
| // CHECK9-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4 | // CHECK9-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4 | ||||
| // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] | // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] | ||||
| // CHECK9: omp.inner.for.end: | // CHECK9: omp.inner.for.end: | ||||
| // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | ||||
| // CHECK9: omp.loop.exit: | // CHECK9: omp.loop.exit: | ||||
| // CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) | // CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) | ||||
| // CHECK9-NEXT: ret void | // CHECK9-NEXT: ret void | ||||
| // CHECK9: terminate.lpad: | |||||
| // CHECK9-NEXT: [[TMP11:%.*]] = landingpad { ptr, i32 } | |||||
| // CHECK9-NEXT: catch ptr null | |||||
| // CHECK9-NEXT: [[TMP12:%.*]] = extractvalue { ptr, i32 } [[TMP11]], 0 | |||||
| // CHECK9-NEXT: call void @__clang_call_terminate(ptr [[TMP12]]) #[[ATTR10]] | |||||
| // CHECK9-NEXT: unreachable | |||||
| // | // | ||||
| // | // | ||||
| // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l57 | // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l57 | ||||
| // CHECK9-SAME: () #[[ATTR3]] { | // CHECK9-SAME: () #[[ATTR3]] { | ||||
| // CHECK9-NEXT: entry: | // CHECK9-NEXT: entry: | ||||
| // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @.omp_outlined..6) | // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @.omp_outlined..6) | ||||
| // CHECK9-NEXT: ret void | // CHECK9-NEXT: ret void | ||||
| // | // | ||||
| ▲ Show 20 Lines • Show All 109 Lines • ▼ Show 20 Lines | |||||
| // CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 | // CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 | ||||
| // CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] | // CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] | ||||
| // CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | // CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | ||||
| // CHECK9: omp.inner.for.body: | // CHECK9: omp.inner.for.body: | ||||
| // CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | // CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | ||||
| // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 | // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 | ||||
| // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | ||||
| // CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4 | // CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4 | ||||
| // CHECK9-NEXT: invoke void @_Z3foov() | // CHECK9-NEXT: call unwindabort void @_Z3foov() | ||||
| // CHECK9-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] | |||||
| // CHECK9: invoke.cont: | |||||
| // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | ||||
| // CHECK9: omp.body.continue: | // CHECK9: omp.body.continue: | ||||
| // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | ||||
| // CHECK9: omp.inner.for.inc: | // CHECK9: omp.inner.for.inc: | ||||
| // CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | // CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | ||||
| // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 | // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 | ||||
| // CHECK9-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4 | // CHECK9-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4 | ||||
| // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] | // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] | ||||
| // CHECK9: omp.inner.for.end: | // CHECK9: omp.inner.for.end: | ||||
| // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | ||||
| // CHECK9: omp.loop.exit: | // CHECK9: omp.loop.exit: | ||||
| // CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) | // CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) | ||||
| // CHECK9-NEXT: ret void | // CHECK9-NEXT: ret void | ||||
| // CHECK9: terminate.lpad: | |||||
| // CHECK9-NEXT: [[TMP11:%.*]] = landingpad { ptr, i32 } | |||||
| // CHECK9-NEXT: catch ptr null | |||||
| // CHECK9-NEXT: [[TMP12:%.*]] = extractvalue { ptr, i32 } [[TMP11]], 0 | |||||
| // CHECK9-NEXT: call void @__clang_call_terminate(ptr [[TMP12]]) #[[ATTR10]] | |||||
| // CHECK9-NEXT: unreachable | |||||
| // | // | ||||
| // | // | ||||
| // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l52 | // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l52 | ||||
| // CHECK9-SAME: () #[[ATTR3]] { | // CHECK9-SAME: () #[[ATTR3]] { | ||||
| // CHECK9-NEXT: entry: | // CHECK9-NEXT: entry: | ||||
| // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @.omp_outlined..8) | // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @.omp_outlined..8) | ||||
| // CHECK9-NEXT: ret void | // CHECK9-NEXT: ret void | ||||
| // | // | ||||
| ▲ Show 20 Lines • Show All 109 Lines • ▼ Show 20 Lines | |||||
| // CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 | // CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 | ||||
| // CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] | // CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] | ||||
| // CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | // CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | ||||
| // CHECK9: omp.inner.for.body: | // CHECK9: omp.inner.for.body: | ||||
| // CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | // CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | ||||
| // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 | // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 | ||||
| // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | ||||
| // CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4 | // CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4 | ||||
| // CHECK9-NEXT: invoke void @_Z3foov() | // CHECK9-NEXT: call unwindabort void @_Z3foov() | ||||
| // CHECK9-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] | |||||
| // CHECK9: invoke.cont: | |||||
| // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | ||||
| // CHECK9: omp.body.continue: | // CHECK9: omp.body.continue: | ||||
| // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | ||||
| // CHECK9: omp.inner.for.inc: | // CHECK9: omp.inner.for.inc: | ||||
| // CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | // CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | ||||
| // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 | // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 | ||||
| // CHECK9-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4 | // CHECK9-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4 | ||||
| // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] | // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] | ||||
| // CHECK9: omp.inner.for.end: | // CHECK9: omp.inner.for.end: | ||||
| // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | ||||
| // CHECK9: omp.loop.exit: | // CHECK9: omp.loop.exit: | ||||
| // CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) | // CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) | ||||
| // CHECK9-NEXT: ret void | // CHECK9-NEXT: ret void | ||||
| // CHECK9: terminate.lpad: | |||||
| // CHECK9-NEXT: [[TMP11:%.*]] = landingpad { ptr, i32 } | |||||
| // CHECK9-NEXT: catch ptr null | |||||
| // CHECK9-NEXT: [[TMP12:%.*]] = extractvalue { ptr, i32 } [[TMP11]], 0 | |||||
| // CHECK9-NEXT: call void @__clang_call_terminate(ptr [[TMP12]]) #[[ATTR10]] | |||||
| // CHECK9-NEXT: unreachable | |||||
| // | // | ||||
| // | // | ||||
| // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l57 | // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l57 | ||||
| // CHECK9-SAME: () #[[ATTR3]] { | // CHECK9-SAME: () #[[ATTR3]] { | ||||
| // CHECK9-NEXT: entry: | // CHECK9-NEXT: entry: | ||||
| // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @.omp_outlined..10) | // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @.omp_outlined..10) | ||||
| // CHECK9-NEXT: ret void | // CHECK9-NEXT: ret void | ||||
| // | // | ||||
| Show All 35 Lines | |||||
| // CHECK9-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 | // CHECK9-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 | ||||
| // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] | // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] | ||||
| // CHECK9: omp.inner.for.cond: | // CHECK9: omp.inner.for.cond: | ||||
| // CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | // CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | ||||
| // CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 | // CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 | ||||
| // CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] | // CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] | ||||
| // CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | // CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | ||||
| // CHECK9: omp.inner.for.body: | // CHECK9: omp.inner.for.body: | ||||
| // CHECK9-NEXT: invoke void @_ZN1SC1El(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]], i64 noundef 23) | // CHECK9-NEXT: call unwindabort void @_ZN1SC1El(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]], i64 noundef 23) | ||||
| // CHECK9-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] | // CHECK9-NEXT: [[CALL:%.*]] = call unwindabort noundef i8 @_ZN1ScvcEv(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) | ||||
| // CHECK9: invoke.cont: | |||||
| // CHECK9-NEXT: [[CALL:%.*]] = invoke noundef i8 @_ZN1ScvcEv(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) | |||||
| // CHECK9-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[TERMINATE_LPAD]] | |||||
| // CHECK9: invoke.cont2: | |||||
| // CHECK9-NEXT: [[TMP7:%.*]] = sext i8 [[CALL]] to i32 | // CHECK9-NEXT: [[TMP7:%.*]] = sext i8 [[CALL]] to i32 | ||||
| // CHECK9-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP1]], i32 [[TMP7]]) | // CHECK9-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP1]], i32 [[TMP7]]) | ||||
| // CHECK9-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]] | // CHECK9-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR5]] | ||||
| // CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 | // CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 | ||||
| // CHECK9-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 | // CHECK9-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 | ||||
| // CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 | // CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 | ||||
| // CHECK9-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 | // CHECK9-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 | ||||
| // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @.omp_outlined..11, i64 [[TMP9]], i64 [[TMP11]]) | // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @.omp_outlined..11, i64 [[TMP9]], i64 [[TMP11]]) | ||||
| // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | ||||
| // CHECK9: omp.inner.for.inc: | // CHECK9: omp.inner.for.inc: | ||||
| // CHECK9-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | // CHECK9-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | ||||
| // CHECK9-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 | // CHECK9-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 | ||||
| // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] | // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] | ||||
| // CHECK9-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 | // CHECK9-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 | ||||
| // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] | // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] | ||||
| // CHECK9: omp.inner.for.end: | // CHECK9: omp.inner.for.end: | ||||
| // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | ||||
| // CHECK9: omp.loop.exit: | // CHECK9: omp.loop.exit: | ||||
| // CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) | // CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) | ||||
| // CHECK9-NEXT: ret void | // CHECK9-NEXT: ret void | ||||
| // CHECK9: terminate.lpad: | |||||
| // CHECK9-NEXT: [[TMP14:%.*]] = landingpad { ptr, i32 } | |||||
| // CHECK9-NEXT: catch ptr null | |||||
| // CHECK9-NEXT: [[TMP15:%.*]] = extractvalue { ptr, i32 } [[TMP14]], 0 | |||||
| // CHECK9-NEXT: call void @__clang_call_terminate(ptr [[TMP15]]) #[[ATTR10]] | |||||
| // CHECK9-NEXT: unreachable | |||||
| // | // | ||||
| // | // | ||||
| // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..11 | // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..11 | ||||
| // CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality ptr @__gxx_personality_v0 { | // CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality ptr @__gxx_personality_v0 { | ||||
| // CHECK9-NEXT: entry: | // CHECK9-NEXT: entry: | ||||
| // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 | // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 | ||||
| // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 | // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 | ||||
| // CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 | // CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 | ||||
| ▲ Show 20 Lines • Show All 41 Lines • ▼ Show 20 Lines | |||||
| // CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 | // CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 | ||||
| // CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] | // CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] | ||||
| // CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | // CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | ||||
| // CHECK9: omp.inner.for.body: | // CHECK9: omp.inner.for.body: | ||||
| // CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | // CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | ||||
| // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 | // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 | ||||
| // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | ||||
| // CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4 | // CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4 | ||||
| // CHECK9-NEXT: invoke void @_Z3foov() | // CHECK9-NEXT: call unwindabort void @_Z3foov() | ||||
| // CHECK9-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] | |||||
| // CHECK9: invoke.cont: | |||||
| // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | ||||
| // CHECK9: omp.body.continue: | // CHECK9: omp.body.continue: | ||||
| // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | ||||
| // CHECK9: omp.inner.for.inc: | // CHECK9: omp.inner.for.inc: | ||||
| // CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | // CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | ||||
| // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 | // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 | ||||
| // CHECK9-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4 | // CHECK9-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4 | ||||
| // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] | // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] | ||||
| // CHECK9: omp.inner.for.end: | // CHECK9: omp.inner.for.end: | ||||
| // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | ||||
| // CHECK9: omp.loop.exit: | // CHECK9: omp.loop.exit: | ||||
| // CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) | // CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) | ||||
| // CHECK9-NEXT: ret void | // CHECK9-NEXT: ret void | ||||
| // CHECK9: terminate.lpad: | |||||
| // CHECK9-NEXT: [[TMP11:%.*]] = landingpad { ptr, i32 } | |||||
| // CHECK9-NEXT: catch ptr null | |||||
| // CHECK9-NEXT: [[TMP12:%.*]] = extractvalue { ptr, i32 } [[TMP11]], 0 | |||||
| // CHECK9-NEXT: call void @__clang_call_terminate(ptr [[TMP12]]) #[[ATTR10]] | |||||
| // CHECK9-NEXT: unreachable | |||||
| // | // | ||||
| // | // | ||||
| // CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg | // CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg | ||||
| // CHECK9-SAME: () #[[ATTR9:[0-9]+]] { | // CHECK9-SAME: () #[[ATTR8:[0-9]+]] { | ||||
| // CHECK9-NEXT: entry: | // CHECK9-NEXT: entry: | ||||
| // CHECK9-NEXT: call void @__tgt_register_requires(i64 1) | // CHECK9-NEXT: call void @__tgt_register_requires(i64 1) | ||||
| // CHECK9-NEXT: ret void | // CHECK9-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK13-LABEL: define {{[^@]+}}@main | // CHECK13-LABEL: define {{[^@]+}}@main | ||||
| // CHECK13-SAME: () #[[ATTR0:[0-9]+]] personality ptr @__gxx_personality_v0 { | // CHECK13-SAME: () #[[ATTR0:[0-9]+]] personality ptr @__gxx_personality_v0 { | ||||
| // CHECK13-NEXT: entry: | // CHECK13-NEXT: entry: | ||||
| Show All 32 Lines | |||||
| // CHECK13-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 | // CHECK13-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 | ||||
| // CHECK13-NEXT: store ptr null, ptr [[TMP7]], align 8 | // CHECK13-NEXT: store ptr null, ptr [[TMP7]], align 8 | ||||
| // CHECK13-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 | // CHECK13-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 | ||||
| // CHECK13-NEXT: store i64 100, ptr [[TMP8]], align 8 | // CHECK13-NEXT: store i64 100, ptr [[TMP8]], align 8 | ||||
| // CHECK13-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.region_id, ptr [[KERNEL_ARGS]]) | // CHECK13-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.region_id, ptr [[KERNEL_ARGS]]) | ||||
| // CHECK13-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 | // CHECK13-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 | ||||
| // CHECK13-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] | // CHECK13-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] | ||||
| // CHECK13: omp_offload.failed: | // CHECK13: omp_offload.failed: | ||||
| // CHECK13-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68() #[[ATTR6:[0-9]+]] | // CHECK13-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68() #[[ATTR5:[0-9]+]] | ||||
| // CHECK13-NEXT: br label [[OMP_OFFLOAD_CONT]] | // CHECK13-NEXT: br label [[OMP_OFFLOAD_CONT]] | ||||
| // CHECK13: lpad: | // CHECK13: lpad: | ||||
| // CHECK13-NEXT: [[TMP11:%.*]] = landingpad { ptr, i32 } | // CHECK13-NEXT: [[TMP11:%.*]] = landingpad { ptr, i32 } | ||||
| // CHECK13-NEXT: cleanup | // CHECK13-NEXT: cleanup | ||||
| // CHECK13-NEXT: [[TMP12:%.*]] = extractvalue { ptr, i32 } [[TMP11]], 0 | // CHECK13-NEXT: [[TMP12:%.*]] = extractvalue { ptr, i32 } [[TMP11]], 0 | ||||
| // CHECK13-NEXT: store ptr [[TMP12]], ptr [[EXN_SLOT]], align 8 | // CHECK13-NEXT: store ptr [[TMP12]], ptr [[EXN_SLOT]], align 8 | ||||
| // CHECK13-NEXT: [[TMP13:%.*]] = extractvalue { ptr, i32 } [[TMP11]], 1 | // CHECK13-NEXT: [[TMP13:%.*]] = extractvalue { ptr, i32 } [[TMP11]], 1 | ||||
| // CHECK13-NEXT: store i32 [[TMP13]], ptr [[EHSELECTOR_SLOT]], align 4 | // CHECK13-NEXT: store i32 [[TMP13]], ptr [[EHSELECTOR_SLOT]], align 4 | ||||
| // CHECK13-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR6]] | // CHECK13-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR5]] | ||||
| // CHECK13-NEXT: br label [[EH_RESUME:%.*]] | // CHECK13-NEXT: br label [[EH_RESUME:%.*]] | ||||
| // CHECK13: omp_offload.cont: | // CHECK13: omp_offload.cont: | ||||
| // CHECK13-NEXT: [[TMP14:%.*]] = load i8, ptr [[A]], align 1 | // CHECK13-NEXT: [[TMP14:%.*]] = load i8, ptr [[A]], align 1 | ||||
| // CHECK13-NEXT: store i8 [[TMP14]], ptr [[A_CASTED]], align 1 | // CHECK13-NEXT: store i8 [[TMP14]], ptr [[A_CASTED]], align 1 | ||||
| // CHECK13-NEXT: [[TMP15:%.*]] = load i64, ptr [[A_CASTED]], align 8 | // CHECK13-NEXT: [[TMP15:%.*]] = load i64, ptr [[A_CASTED]], align 8 | ||||
| // CHECK13-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 | // CHECK13-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 | ||||
| // CHECK13-NEXT: store i64 [[TMP15]], ptr [[TMP16]], align 8 | // CHECK13-NEXT: store i64 [[TMP15]], ptr [[TMP16]], align 8 | ||||
| // CHECK13-NEXT: [[TMP17:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 | // CHECK13-NEXT: [[TMP17:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 | ||||
| Show All 20 Lines | |||||
| // CHECK13-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 7 | // CHECK13-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 7 | ||||
| // CHECK13-NEXT: store ptr null, ptr [[TMP28]], align 8 | // CHECK13-NEXT: store ptr null, ptr [[TMP28]], align 8 | ||||
| // CHECK13-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 8 | // CHECK13-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 8 | ||||
| // CHECK13-NEXT: store i64 100, ptr [[TMP29]], align 8 | // CHECK13-NEXT: store i64 100, ptr [[TMP29]], align 8 | ||||
| // CHECK13-NEXT: [[TMP30:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74.region_id, ptr [[KERNEL_ARGS2]]) | // CHECK13-NEXT: [[TMP30:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74.region_id, ptr [[KERNEL_ARGS2]]) | ||||
| // CHECK13-NEXT: [[TMP31:%.*]] = icmp ne i32 [[TMP30]], 0 | // CHECK13-NEXT: [[TMP31:%.*]] = icmp ne i32 [[TMP30]], 0 | ||||
| // CHECK13-NEXT: br i1 [[TMP31]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]] | // CHECK13-NEXT: br i1 [[TMP31]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]] | ||||
| // CHECK13: omp_offload.failed3: | // CHECK13: omp_offload.failed3: | ||||
| // CHECK13-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74(i64 [[TMP15]]) #[[ATTR6]] | // CHECK13-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74(i64 [[TMP15]]) #[[ATTR5]] | ||||
| // CHECK13-NEXT: br label [[OMP_OFFLOAD_CONT4]] | // CHECK13-NEXT: br label [[OMP_OFFLOAD_CONT4]] | ||||
| // CHECK13: omp_offload.cont4: | // CHECK13: omp_offload.cont4: | ||||
| // CHECK13-NEXT: [[TMP32:%.*]] = load i8, ptr [[A]], align 1 | // CHECK13-NEXT: [[TMP32:%.*]] = load i8, ptr [[A]], align 1 | ||||
| // CHECK13-NEXT: [[CONV:%.*]] = sext i8 [[TMP32]] to i32 | // CHECK13-NEXT: [[CONV:%.*]] = sext i8 [[TMP32]] to i32 | ||||
| // CHECK13-NEXT: [[CALL6:%.*]] = invoke noundef i32 @_Z5tmainIcLi5EEiv() | // CHECK13-NEXT: [[CALL6:%.*]] = invoke noundef i32 @_Z5tmainIcLi5EEiv() | ||||
| // CHECK13-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[LPAD]] | // CHECK13-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[LPAD]] | ||||
| // CHECK13: invoke.cont5: | // CHECK13: invoke.cont5: | ||||
| // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], [[CALL6]] | // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], [[CALL6]] | ||||
| // CHECK13-NEXT: [[CALL8:%.*]] = invoke noundef i32 @_Z5tmainI1SLi1EEiv() | // CHECK13-NEXT: [[CALL8:%.*]] = invoke noundef i32 @_Z5tmainI1SLi1EEiv() | ||||
| // CHECK13-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD]] | // CHECK13-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD]] | ||||
| // CHECK13: invoke.cont7: | // CHECK13: invoke.cont7: | ||||
| // CHECK13-NEXT: [[ADD9:%.*]] = add nsw i32 [[ADD]], [[CALL8]] | // CHECK13-NEXT: [[ADD9:%.*]] = add nsw i32 [[ADD]], [[CALL8]] | ||||
| // CHECK13-NEXT: store i32 [[ADD9]], ptr [[RETVAL]], align 4 | // CHECK13-NEXT: store i32 [[ADD9]], ptr [[RETVAL]], align 4 | ||||
| // CHECK13-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR6]] | // CHECK13-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR5]] | ||||
| // CHECK13-NEXT: [[TMP33:%.*]] = load i32, ptr [[RETVAL]], align 4 | // CHECK13-NEXT: [[TMP33:%.*]] = load i32, ptr [[RETVAL]], align 4 | ||||
| // CHECK13-NEXT: ret i32 [[TMP33]] | // CHECK13-NEXT: ret i32 [[TMP33]] | ||||
| // CHECK13: eh.resume: | // CHECK13: eh.resume: | ||||
| // CHECK13-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8 | // CHECK13-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8 | ||||
| // CHECK13-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4 | // CHECK13-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4 | ||||
| // CHECK13-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0 | // CHECK13-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0 | ||||
| // CHECK13-NEXT: [[LPAD_VAL10:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1 | // CHECK13-NEXT: [[LPAD_VAL10:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1 | ||||
| // CHECK13-NEXT: resume { ptr, i32 } [[LPAD_VAL10]] | // CHECK13-NEXT: resume { ptr, i32 } [[LPAD_VAL10]] | ||||
| ▲ Show 20 Lines • Show All 143 Lines • ▼ Show 20 Lines | |||||
| // CHECK13-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 | // CHECK13-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 | ||||
| // CHECK13-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] | // CHECK13-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] | ||||
| // CHECK13-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | // CHECK13-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | ||||
| // CHECK13: omp.inner.for.body: | // CHECK13: omp.inner.for.body: | ||||
| // CHECK13-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | // CHECK13-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | ||||
| // CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 | // CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 | ||||
| // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | ||||
| // CHECK13-NEXT: store i32 [[ADD]], ptr [[I]], align 4 | // CHECK13-NEXT: store i32 [[ADD]], ptr [[I]], align 4 | ||||
| // CHECK13-NEXT: invoke void @_Z3foov() | // CHECK13-NEXT: call unwindabort void @_Z3foov() | ||||
| // CHECK13-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] | |||||
| // CHECK13: invoke.cont: | |||||
| // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | ||||
| // CHECK13: omp.body.continue: | // CHECK13: omp.body.continue: | ||||
| // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | ||||
| // CHECK13: omp.inner.for.inc: | // CHECK13: omp.inner.for.inc: | ||||
| // CHECK13-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | // CHECK13-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | ||||
| // CHECK13-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 | // CHECK13-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 | ||||
| // CHECK13-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4 | // CHECK13-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4 | ||||
| // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] | // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] | ||||
| // CHECK13: omp.inner.for.end: | // CHECK13: omp.inner.for.end: | ||||
| // CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | // CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | ||||
| // CHECK13: omp.loop.exit: | // CHECK13: omp.loop.exit: | ||||
| // CHECK13-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) | // CHECK13-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) | ||||
| // CHECK13-NEXT: ret void | // CHECK13-NEXT: ret void | ||||
| // CHECK13: terminate.lpad: | |||||
| // CHECK13-NEXT: [[TMP11:%.*]] = landingpad { ptr, i32 } | |||||
| // CHECK13-NEXT: catch ptr null | |||||
| // CHECK13-NEXT: [[TMP12:%.*]] = extractvalue { ptr, i32 } [[TMP11]], 0 | |||||
| // CHECK13-NEXT: call void @__clang_call_terminate(ptr [[TMP12]]) #[[ATTR10:[0-9]+]] | |||||
| // CHECK13-NEXT: unreachable | |||||
| // | |||||
| // | |||||
| // CHECK13-LABEL: define {{[^@]+}}@__clang_call_terminate | |||||
| // CHECK13-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR5:[0-9]+]] comdat { | |||||
| // CHECK13-NEXT: [[TMP2:%.*]] = call ptr @__cxa_begin_catch(ptr [[TMP0]]) #[[ATTR6]] | |||||
| // CHECK13-NEXT: call void @_ZSt9terminatev() #[[ATTR10]] | |||||
| // CHECK13-NEXT: unreachable | |||||
| // | // | ||||
| // | // | ||||
| // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74 | // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74 | ||||
| // CHECK13-SAME: (i64 noundef [[A:%.*]]) #[[ATTR3]] { | // CHECK13-SAME: (i64 noundef [[A:%.*]]) #[[ATTR3]] { | ||||
| // CHECK13-NEXT: entry: | // CHECK13-NEXT: entry: | ||||
| // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK13-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 | // CHECK13-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 | ||||
| // CHECK13-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 1, ptr @.omp_outlined..2, ptr [[A_ADDR]]) | // CHECK13-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 1, ptr @.omp_outlined..2, ptr [[A_ADDR]]) | ||||
| ▲ Show 20 Lines • Show All 116 Lines • ▼ Show 20 Lines | |||||
| // CHECK13-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 | // CHECK13-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 | ||||
| // CHECK13-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] | // CHECK13-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] | ||||
| // CHECK13-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | // CHECK13-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | ||||
| // CHECK13: omp.inner.for.body: | // CHECK13: omp.inner.for.body: | ||||
| // CHECK13-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | // CHECK13-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | ||||
| // CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 | // CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 | ||||
| // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | ||||
| // CHECK13-NEXT: store i32 [[ADD]], ptr [[I]], align 4 | // CHECK13-NEXT: store i32 [[ADD]], ptr [[I]], align 4 | ||||
| // CHECK13-NEXT: invoke void @_Z3foov() | // CHECK13-NEXT: call unwindabort void @_Z3foov() | ||||
| // CHECK13-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] | |||||
| // CHECK13: invoke.cont: | |||||
| // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | ||||
| // CHECK13: omp.body.continue: | // CHECK13: omp.body.continue: | ||||
| // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | ||||
| // CHECK13: omp.inner.for.inc: | // CHECK13: omp.inner.for.inc: | ||||
| // CHECK13-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | // CHECK13-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | ||||
| // CHECK13-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 | // CHECK13-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 | ||||
| // CHECK13-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4 | // CHECK13-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4 | ||||
| // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] | // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] | ||||
| // CHECK13: omp.inner.for.end: | // CHECK13: omp.inner.for.end: | ||||
| // CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | // CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | ||||
| // CHECK13: omp.loop.exit: | // CHECK13: omp.loop.exit: | ||||
| // CHECK13-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) | // CHECK13-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) | ||||
| // CHECK13-NEXT: ret void | // CHECK13-NEXT: ret void | ||||
| // CHECK13: terminate.lpad: | |||||
| // CHECK13-NEXT: [[TMP11:%.*]] = landingpad { ptr, i32 } | |||||
| // CHECK13-NEXT: catch ptr null | |||||
| // CHECK13-NEXT: [[TMP12:%.*]] = extractvalue { ptr, i32 } [[TMP11]], 0 | |||||
| // CHECK13-NEXT: call void @__clang_call_terminate(ptr [[TMP12]]) #[[ATTR10]] | |||||
| // CHECK13-NEXT: unreachable | |||||
| // | // | ||||
| // | // | ||||
| // CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIcLi5EEiv | // CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIcLi5EEiv | ||||
| // CHECK13-SAME: () #[[ATTR7:[0-9]+]] comdat { | // CHECK13-SAME: () #[[ATTR6:[0-9]+]] comdat { | ||||
| // CHECK13-NEXT: entry: | // CHECK13-NEXT: entry: | ||||
| // CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 | // CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 | ||||
| // CHECK13-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 | // CHECK13-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 | ||||
| // CHECK13-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 | // CHECK13-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 | ||||
| // CHECK13-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 | // CHECK13-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 | ||||
| // CHECK13-NEXT: store i32 1, ptr [[TMP0]], align 4 | // CHECK13-NEXT: store i32 1, ptr [[TMP0]], align 4 | ||||
| // CHECK13-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 | // CHECK13-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 | ||||
| // CHECK13-NEXT: store i32 0, ptr [[TMP1]], align 4 | // CHECK13-NEXT: store i32 0, ptr [[TMP1]], align 4 | ||||
| Show All 10 Lines | |||||
| // CHECK13-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 | // CHECK13-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 | ||||
| // CHECK13-NEXT: store ptr null, ptr [[TMP7]], align 8 | // CHECK13-NEXT: store ptr null, ptr [[TMP7]], align 8 | ||||
| // CHECK13-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 | // CHECK13-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 | ||||
| // CHECK13-NEXT: store i64 100, ptr [[TMP8]], align 8 | // CHECK13-NEXT: store i64 100, ptr [[TMP8]], align 8 | ||||
| // CHECK13-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l52.region_id, ptr [[KERNEL_ARGS]]) | // CHECK13-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l52.region_id, ptr [[KERNEL_ARGS]]) | ||||
| // CHECK13-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 | // CHECK13-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 | ||||
| // CHECK13-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] | // CHECK13-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] | ||||
| // CHECK13: omp_offload.failed: | // CHECK13: omp_offload.failed: | ||||
| // CHECK13-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l52() #[[ATTR6]] | // CHECK13-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l52() #[[ATTR5]] | ||||
| // CHECK13-NEXT: br label [[OMP_OFFLOAD_CONT]] | // CHECK13-NEXT: br label [[OMP_OFFLOAD_CONT]] | ||||
| // CHECK13: omp_offload.cont: | // CHECK13: omp_offload.cont: | ||||
| // CHECK13-NEXT: [[KERNEL_ARGS2:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 | // CHECK13-NEXT: [[KERNEL_ARGS2:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 | ||||
| // CHECK13-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 0 | // CHECK13-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 0 | ||||
| // CHECK13-NEXT: store i32 1, ptr [[TMP11]], align 4 | // CHECK13-NEXT: store i32 1, ptr [[TMP11]], align 4 | ||||
| // CHECK13-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 1 | // CHECK13-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 1 | ||||
| // CHECK13-NEXT: store i32 0, ptr [[TMP12]], align 4 | // CHECK13-NEXT: store i32 0, ptr [[TMP12]], align 4 | ||||
| // CHECK13-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 2 | // CHECK13-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 2 | ||||
| Show All 9 Lines | |||||
| // CHECK13-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 7 | // CHECK13-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 7 | ||||
| // CHECK13-NEXT: store ptr null, ptr [[TMP18]], align 8 | // CHECK13-NEXT: store ptr null, ptr [[TMP18]], align 8 | ||||
| // CHECK13-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 8 | // CHECK13-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 8 | ||||
| // CHECK13-NEXT: store i64 100, ptr [[TMP19]], align 8 | // CHECK13-NEXT: store i64 100, ptr [[TMP19]], align 8 | ||||
| // CHECK13-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l57.region_id, ptr [[KERNEL_ARGS2]]) | // CHECK13-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l57.region_id, ptr [[KERNEL_ARGS2]]) | ||||
| // CHECK13-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 | // CHECK13-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 | ||||
| // CHECK13-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]] | // CHECK13-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]] | ||||
| // CHECK13: omp_offload.failed3: | // CHECK13: omp_offload.failed3: | ||||
| // CHECK13-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l57() #[[ATTR6]] | // CHECK13-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l57() #[[ATTR5]] | ||||
| // CHECK13-NEXT: br label [[OMP_OFFLOAD_CONT4]] | // CHECK13-NEXT: br label [[OMP_OFFLOAD_CONT4]] | ||||
| // CHECK13: omp_offload.cont4: | // CHECK13: omp_offload.cont4: | ||||
| // CHECK13-NEXT: ret i32 0 | // CHECK13-NEXT: ret i32 0 | ||||
| // | // | ||||
| // | // | ||||
| // CHECK13-LABEL: define {{[^@]+}}@_Z5tmainI1SLi1EEiv | // CHECK13-LABEL: define {{[^@]+}}@_Z5tmainI1SLi1EEiv | ||||
| // CHECK13-SAME: () #[[ATTR7]] comdat { | // CHECK13-SAME: () #[[ATTR6]] comdat { | ||||
| // CHECK13-NEXT: entry: | // CHECK13-NEXT: entry: | ||||
| // CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 | // CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 | ||||
| // CHECK13-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 | // CHECK13-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 | ||||
| // CHECK13-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 | // CHECK13-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 | ||||
| // CHECK13-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 | // CHECK13-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 | ||||
| // CHECK13-NEXT: store i32 1, ptr [[TMP0]], align 4 | // CHECK13-NEXT: store i32 1, ptr [[TMP0]], align 4 | ||||
| // CHECK13-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 | // CHECK13-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 | ||||
| // CHECK13-NEXT: store i32 0, ptr [[TMP1]], align 4 | // CHECK13-NEXT: store i32 0, ptr [[TMP1]], align 4 | ||||
| Show All 10 Lines | |||||
| // CHECK13-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 | // CHECK13-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 | ||||
| // CHECK13-NEXT: store ptr null, ptr [[TMP7]], align 8 | // CHECK13-NEXT: store ptr null, ptr [[TMP7]], align 8 | ||||
| // CHECK13-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 | // CHECK13-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 | ||||
| // CHECK13-NEXT: store i64 100, ptr [[TMP8]], align 8 | // CHECK13-NEXT: store i64 100, ptr [[TMP8]], align 8 | ||||
| // CHECK13-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l52.region_id, ptr [[KERNEL_ARGS]]) | // CHECK13-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l52.region_id, ptr [[KERNEL_ARGS]]) | ||||
| // CHECK13-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 | // CHECK13-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 | ||||
| // CHECK13-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] | // CHECK13-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] | ||||
| // CHECK13: omp_offload.failed: | // CHECK13: omp_offload.failed: | ||||
| // CHECK13-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l52() #[[ATTR6]] | // CHECK13-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l52() #[[ATTR5]] | ||||
| // CHECK13-NEXT: br label [[OMP_OFFLOAD_CONT]] | // CHECK13-NEXT: br label [[OMP_OFFLOAD_CONT]] | ||||
| // CHECK13: omp_offload.cont: | // CHECK13: omp_offload.cont: | ||||
| // CHECK13-NEXT: [[KERNEL_ARGS2:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 | // CHECK13-NEXT: [[KERNEL_ARGS2:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 | ||||
| // CHECK13-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 0 | // CHECK13-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 0 | ||||
| // CHECK13-NEXT: store i32 1, ptr [[TMP11]], align 4 | // CHECK13-NEXT: store i32 1, ptr [[TMP11]], align 4 | ||||
| // CHECK13-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 1 | // CHECK13-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 1 | ||||
| // CHECK13-NEXT: store i32 0, ptr [[TMP12]], align 4 | // CHECK13-NEXT: store i32 0, ptr [[TMP12]], align 4 | ||||
| // CHECK13-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 2 | // CHECK13-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 2 | ||||
| Show All 9 Lines | |||||
| // CHECK13-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 7 | // CHECK13-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 7 | ||||
| // CHECK13-NEXT: store ptr null, ptr [[TMP18]], align 8 | // CHECK13-NEXT: store ptr null, ptr [[TMP18]], align 8 | ||||
| // CHECK13-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 8 | // CHECK13-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 8 | ||||
| // CHECK13-NEXT: store i64 100, ptr [[TMP19]], align 8 | // CHECK13-NEXT: store i64 100, ptr [[TMP19]], align 8 | ||||
| // CHECK13-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l57.region_id, ptr [[KERNEL_ARGS2]]) | // CHECK13-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l57.region_id, ptr [[KERNEL_ARGS2]]) | ||||
| // CHECK13-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 | // CHECK13-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 | ||||
| // CHECK13-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]] | // CHECK13-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]] | ||||
| // CHECK13: omp_offload.failed3: | // CHECK13: omp_offload.failed3: | ||||
| // CHECK13-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l57() #[[ATTR6]] | // CHECK13-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l57() #[[ATTR5]] | ||||
| // CHECK13-NEXT: br label [[OMP_OFFLOAD_CONT4]] | // CHECK13-NEXT: br label [[OMP_OFFLOAD_CONT4]] | ||||
| // CHECK13: omp_offload.cont4: | // CHECK13: omp_offload.cont4: | ||||
| // CHECK13-NEXT: ret i32 0 | // CHECK13-NEXT: ret i32 0 | ||||
| // | // | ||||
| // | // | ||||
| // CHECK13-LABEL: define {{[^@]+}}@_ZN1SD1Ev | // CHECK13-LABEL: define {{[^@]+}}@_ZN1SD1Ev | ||||
| // CHECK13-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR8:[0-9]+]] comdat align 2 { | // CHECK13-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR7:[0-9]+]] comdat align 2 { | ||||
| // CHECK13-NEXT: entry: | // CHECK13-NEXT: entry: | ||||
| // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 | // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 | ||||
| // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 | // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 | ||||
| // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 | // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 | ||||
| // CHECK13-NEXT: call void @_ZN1SD2Ev(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR6]] | // CHECK13-NEXT: call void @_ZN1SD2Ev(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR5]] | ||||
| // CHECK13-NEXT: ret void | // CHECK13-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK13-LABEL: define {{[^@]+}}@_ZN1SC2El | // CHECK13-LABEL: define {{[^@]+}}@_ZN1SC2El | ||||
| // CHECK13-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR8]] comdat align 2 { | // CHECK13-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR7]] comdat align 2 { | ||||
| // CHECK13-NEXT: entry: | // CHECK13-NEXT: entry: | ||||
| // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 | // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 | ||||
| // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 | ||||
| // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 | // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 | ||||
| // CHECK13-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 | // CHECK13-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 | ||||
| // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 | // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 | ||||
| // CHECK13-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 | // CHECK13-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 | ||||
| // CHECK13-NEXT: [[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8 | // CHECK13-NEXT: [[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8 | ||||
| ▲ Show 20 Lines • Show All 119 Lines • ▼ Show 20 Lines | |||||
| // CHECK13-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 | // CHECK13-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 | ||||
| // CHECK13-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] | // CHECK13-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] | ||||
| // CHECK13-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | // CHECK13-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | ||||
| // CHECK13: omp.inner.for.body: | // CHECK13: omp.inner.for.body: | ||||
| // CHECK13-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | // CHECK13-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | ||||
| // CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 | // CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 | ||||
| // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | ||||
| // CHECK13-NEXT: store i32 [[ADD]], ptr [[I]], align 4 | // CHECK13-NEXT: store i32 [[ADD]], ptr [[I]], align 4 | ||||
| // CHECK13-NEXT: invoke void @_Z3foov() | // CHECK13-NEXT: call unwindabort void @_Z3foov() | ||||
| // CHECK13-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] | |||||
| // CHECK13: invoke.cont: | |||||
| // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | ||||
| // CHECK13: omp.body.continue: | // CHECK13: omp.body.continue: | ||||
| // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | ||||
| // CHECK13: omp.inner.for.inc: | // CHECK13: omp.inner.for.inc: | ||||
| // CHECK13-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | // CHECK13-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | ||||
| // CHECK13-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 | // CHECK13-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 | ||||
| // CHECK13-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4 | // CHECK13-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4 | ||||
| // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] | // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] | ||||
| // CHECK13: omp.inner.for.end: | // CHECK13: omp.inner.for.end: | ||||
| // CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | // CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | ||||
| // CHECK13: omp.loop.exit: | // CHECK13: omp.loop.exit: | ||||
| // CHECK13-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) | // CHECK13-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) | ||||
| // CHECK13-NEXT: ret void | // CHECK13-NEXT: ret void | ||||
| // CHECK13: terminate.lpad: | |||||
| // CHECK13-NEXT: [[TMP11:%.*]] = landingpad { ptr, i32 } | |||||
| // CHECK13-NEXT: catch ptr null | |||||
| // CHECK13-NEXT: [[TMP12:%.*]] = extractvalue { ptr, i32 } [[TMP11]], 0 | |||||
| // CHECK13-NEXT: call void @__clang_call_terminate(ptr [[TMP12]]) #[[ATTR10]] | |||||
| // CHECK13-NEXT: unreachable | |||||
| // | // | ||||
| // | // | ||||
| // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l57 | // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l57 | ||||
| // CHECK13-SAME: () #[[ATTR3]] { | // CHECK13-SAME: () #[[ATTR3]] { | ||||
| // CHECK13-NEXT: entry: | // CHECK13-NEXT: entry: | ||||
| // CHECK13-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @.omp_outlined..6) | // CHECK13-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @.omp_outlined..6) | ||||
| // CHECK13-NEXT: ret void | // CHECK13-NEXT: ret void | ||||
| // | // | ||||
| ▲ Show 20 Lines • Show All 109 Lines • ▼ Show 20 Lines | |||||
| // CHECK13-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 | // CHECK13-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 | ||||
| // CHECK13-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] | // CHECK13-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] | ||||
| // CHECK13-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | // CHECK13-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | ||||
| // CHECK13: omp.inner.for.body: | // CHECK13: omp.inner.for.body: | ||||
| // CHECK13-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | // CHECK13-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | ||||
| // CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 | // CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 | ||||
| // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | ||||
| // CHECK13-NEXT: store i32 [[ADD]], ptr [[I]], align 4 | // CHECK13-NEXT: store i32 [[ADD]], ptr [[I]], align 4 | ||||
| // CHECK13-NEXT: invoke void @_Z3foov() | // CHECK13-NEXT: call unwindabort void @_Z3foov() | ||||
| // CHECK13-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] | |||||
| // CHECK13: invoke.cont: | |||||
| // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | ||||
| // CHECK13: omp.body.continue: | // CHECK13: omp.body.continue: | ||||
| // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | ||||
| // CHECK13: omp.inner.for.inc: | // CHECK13: omp.inner.for.inc: | ||||
| // CHECK13-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | // CHECK13-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | ||||
| // CHECK13-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 | // CHECK13-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 | ||||
| // CHECK13-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4 | // CHECK13-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4 | ||||
| // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] | // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] | ||||
| // CHECK13: omp.inner.for.end: | // CHECK13: omp.inner.for.end: | ||||
| // CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | // CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | ||||
| // CHECK13: omp.loop.exit: | // CHECK13: omp.loop.exit: | ||||
| // CHECK13-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) | // CHECK13-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) | ||||
| // CHECK13-NEXT: ret void | // CHECK13-NEXT: ret void | ||||
| // CHECK13: terminate.lpad: | |||||
| // CHECK13-NEXT: [[TMP11:%.*]] = landingpad { ptr, i32 } | |||||
| // CHECK13-NEXT: catch ptr null | |||||
| // CHECK13-NEXT: [[TMP12:%.*]] = extractvalue { ptr, i32 } [[TMP11]], 0 | |||||
| // CHECK13-NEXT: call void @__clang_call_terminate(ptr [[TMP12]]) #[[ATTR10]] | |||||
| // CHECK13-NEXT: unreachable | |||||
| // | // | ||||
| // | // | ||||
| // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l52 | // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l52 | ||||
| // CHECK13-SAME: () #[[ATTR3]] { | // CHECK13-SAME: () #[[ATTR3]] { | ||||
| // CHECK13-NEXT: entry: | // CHECK13-NEXT: entry: | ||||
| // CHECK13-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @.omp_outlined..8) | // CHECK13-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @.omp_outlined..8) | ||||
| // CHECK13-NEXT: ret void | // CHECK13-NEXT: ret void | ||||
| // | // | ||||
| ▲ Show 20 Lines • Show All 109 Lines • ▼ Show 20 Lines | |||||
| // CHECK13-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 | // CHECK13-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 | ||||
| // CHECK13-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] | // CHECK13-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] | ||||
| // CHECK13-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | // CHECK13-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | ||||
| // CHECK13: omp.inner.for.body: | // CHECK13: omp.inner.for.body: | ||||
| // CHECK13-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | // CHECK13-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | ||||
| // CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 | // CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 | ||||
| // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | ||||
| // CHECK13-NEXT: store i32 [[ADD]], ptr [[I]], align 4 | // CHECK13-NEXT: store i32 [[ADD]], ptr [[I]], align 4 | ||||
| // CHECK13-NEXT: invoke void @_Z3foov() | // CHECK13-NEXT: call unwindabort void @_Z3foov() | ||||
| // CHECK13-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] | |||||
| // CHECK13: invoke.cont: | |||||
| // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | ||||
| // CHECK13: omp.body.continue: | // CHECK13: omp.body.continue: | ||||
| // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | ||||
| // CHECK13: omp.inner.for.inc: | // CHECK13: omp.inner.for.inc: | ||||
| // CHECK13-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | // CHECK13-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | ||||
| // CHECK13-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 | // CHECK13-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 | ||||
| // CHECK13-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4 | // CHECK13-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4 | ||||
| // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] | // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] | ||||
| // CHECK13: omp.inner.for.end: | // CHECK13: omp.inner.for.end: | ||||
| // CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | // CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | ||||
| // CHECK13: omp.loop.exit: | // CHECK13: omp.loop.exit: | ||||
| // CHECK13-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) | // CHECK13-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) | ||||
| // CHECK13-NEXT: ret void | // CHECK13-NEXT: ret void | ||||
| // CHECK13: terminate.lpad: | |||||
| // CHECK13-NEXT: [[TMP11:%.*]] = landingpad { ptr, i32 } | |||||
| // CHECK13-NEXT: catch ptr null | |||||
| // CHECK13-NEXT: [[TMP12:%.*]] = extractvalue { ptr, i32 } [[TMP11]], 0 | |||||
| // CHECK13-NEXT: call void @__clang_call_terminate(ptr [[TMP12]]) #[[ATTR10]] | |||||
| // CHECK13-NEXT: unreachable | |||||
| // | // | ||||
| // | // | ||||
| // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l57 | // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l57 | ||||
| // CHECK13-SAME: () #[[ATTR3]] { | // CHECK13-SAME: () #[[ATTR3]] { | ||||
| // CHECK13-NEXT: entry: | // CHECK13-NEXT: entry: | ||||
| // CHECK13-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @.omp_outlined..10) | // CHECK13-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @.omp_outlined..10) | ||||
| // CHECK13-NEXT: ret void | // CHECK13-NEXT: ret void | ||||
| // | // | ||||
| Show All 35 Lines | |||||
| // CHECK13-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 | // CHECK13-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 | ||||
| // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] | // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] | ||||
| // CHECK13: omp.inner.for.cond: | // CHECK13: omp.inner.for.cond: | ||||
| // CHECK13-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | // CHECK13-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | ||||
| // CHECK13-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 | // CHECK13-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 | ||||
| // CHECK13-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] | // CHECK13-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] | ||||
| // CHECK13-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | // CHECK13-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | ||||
| // CHECK13: omp.inner.for.body: | // CHECK13: omp.inner.for.body: | ||||
| // CHECK13-NEXT: invoke void @_ZN1SC1El(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]], i64 noundef 23) | // CHECK13-NEXT: call unwindabort void @_ZN1SC1El(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]], i64 noundef 23) | ||||
| // CHECK13-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] | // CHECK13-NEXT: [[CALL:%.*]] = call unwindabort noundef i8 @_ZN1ScvcEv(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) | ||||
| // CHECK13: invoke.cont: | |||||
| // CHECK13-NEXT: [[CALL:%.*]] = invoke noundef i8 @_ZN1ScvcEv(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) | |||||
| // CHECK13-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[TERMINATE_LPAD]] | |||||
| // CHECK13: invoke.cont2: | |||||
| // CHECK13-NEXT: [[TMP7:%.*]] = sext i8 [[CALL]] to i32 | // CHECK13-NEXT: [[TMP7:%.*]] = sext i8 [[CALL]] to i32 | ||||
| // CHECK13-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP1]], i32 [[TMP7]]) | // CHECK13-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP1]], i32 [[TMP7]]) | ||||
| // CHECK13-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR6]] | // CHECK13-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR5]] | ||||
| // CHECK13-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 | // CHECK13-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 | ||||
| // CHECK13-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 | // CHECK13-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 | ||||
| // CHECK13-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 | // CHECK13-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 | ||||
| // CHECK13-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 | // CHECK13-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 | ||||
| // CHECK13-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @.omp_outlined..11, i64 [[TMP9]], i64 [[TMP11]]) | // CHECK13-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @.omp_outlined..11, i64 [[TMP9]], i64 [[TMP11]]) | ||||
| // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | ||||
| // CHECK13: omp.inner.for.inc: | // CHECK13: omp.inner.for.inc: | ||||
| // CHECK13-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | // CHECK13-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | ||||
| // CHECK13-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 | // CHECK13-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 | ||||
| // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] | // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] | ||||
| // CHECK13-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 | // CHECK13-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 | ||||
| // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] | // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] | ||||
| // CHECK13: omp.inner.for.end: | // CHECK13: omp.inner.for.end: | ||||
| // CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | // CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | ||||
| // CHECK13: omp.loop.exit: | // CHECK13: omp.loop.exit: | ||||
| // CHECK13-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) | // CHECK13-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) | ||||
| // CHECK13-NEXT: ret void | // CHECK13-NEXT: ret void | ||||
| // CHECK13: terminate.lpad: | |||||
| // CHECK13-NEXT: [[TMP14:%.*]] = landingpad { ptr, i32 } | |||||
| // CHECK13-NEXT: catch ptr null | |||||
| // CHECK13-NEXT: [[TMP15:%.*]] = extractvalue { ptr, i32 } [[TMP14]], 0 | |||||
| // CHECK13-NEXT: call void @__clang_call_terminate(ptr [[TMP15]]) #[[ATTR10]] | |||||
| // CHECK13-NEXT: unreachable | |||||
| // | // | ||||
| // | // | ||||
| // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..11 | // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..11 | ||||
| // CHECK13-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality ptr @__gxx_personality_v0 { | // CHECK13-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] personality ptr @__gxx_personality_v0 { | ||||
| // CHECK13-NEXT: entry: | // CHECK13-NEXT: entry: | ||||
| // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 | // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 | ||||
| // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 | // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 | ||||
| // CHECK13-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 | // CHECK13-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 | ||||
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| // CHECK13-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 | // CHECK13-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 | ||||
| // CHECK13-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] | // CHECK13-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] | ||||
| // CHECK13-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | // CHECK13-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] | ||||
| // CHECK13: omp.inner.for.body: | // CHECK13: omp.inner.for.body: | ||||
| // CHECK13-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | // CHECK13-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | ||||
| // CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 | // CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 | ||||
| // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] | ||||
| // CHECK13-NEXT: store i32 [[ADD]], ptr [[I]], align 4 | // CHECK13-NEXT: store i32 [[ADD]], ptr [[I]], align 4 | ||||
| // CHECK13-NEXT: invoke void @_Z3foov() | // CHECK13-NEXT: call unwindabort void @_Z3foov() | ||||
| // CHECK13-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] | |||||
| // CHECK13: invoke.cont: | |||||
| // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] | ||||
| // CHECK13: omp.body.continue: | // CHECK13: omp.body.continue: | ||||
| // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] | ||||
| // CHECK13: omp.inner.for.inc: | // CHECK13: omp.inner.for.inc: | ||||
| // CHECK13-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | // CHECK13-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 | ||||
| // CHECK13-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 | // CHECK13-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 | ||||
| // CHECK13-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4 | // CHECK13-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4 | ||||
| // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] | // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] | ||||
| // CHECK13: omp.inner.for.end: | // CHECK13: omp.inner.for.end: | ||||
| // CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | // CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] | ||||
| // CHECK13: omp.loop.exit: | // CHECK13: omp.loop.exit: | ||||
| // CHECK13-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) | // CHECK13-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) | ||||
| // CHECK13-NEXT: ret void | // CHECK13-NEXT: ret void | ||||
| // CHECK13: terminate.lpad: | |||||
| // CHECK13-NEXT: [[TMP11:%.*]] = landingpad { ptr, i32 } | |||||
| // CHECK13-NEXT: catch ptr null | |||||
| // CHECK13-NEXT: [[TMP12:%.*]] = extractvalue { ptr, i32 } [[TMP11]], 0 | |||||
| // CHECK13-NEXT: call void @__clang_call_terminate(ptr [[TMP12]]) #[[ATTR10]] | |||||
| // CHECK13-NEXT: unreachable | |||||
| // | // | ||||
| // | // | ||||
| // CHECK13-LABEL: define {{[^@]+}}@_ZN1SD2Ev | // CHECK13-LABEL: define {{[^@]+}}@_ZN1SD2Ev | ||||
| // CHECK13-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR8]] comdat align 2 { | // CHECK13-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR7]] comdat align 2 { | ||||
| // CHECK13-NEXT: entry: | // CHECK13-NEXT: entry: | ||||
| // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 | // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 | ||||
| // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 | // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 | ||||
| // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 | // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 | ||||
| // CHECK13-NEXT: ret void | // CHECK13-NEXT: ret void | ||||
| // | // | ||||
| // | // | ||||
| // CHECK13-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg | // CHECK13-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg | ||||
| // CHECK13-SAME: () #[[ATTR9:[0-9]+]] { | // CHECK13-SAME: () #[[ATTR8:[0-9]+]] { | ||||
| // CHECK13-NEXT: entry: | // CHECK13-NEXT: entry: | ||||
| // CHECK13-NEXT: call void @__tgt_register_requires(i64 1) | // CHECK13-NEXT: call void @__tgt_register_requires(i64 1) | ||||
| // CHECK13-NEXT: ret void | // CHECK13-NEXT: ret void | ||||
| // | // | ||||