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llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
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| Show First 20 Lines • Show All 1,475 Lines • ▼ Show 20 Lines | case 20: | ||||
| return AMDGPU::SI_SPILL_V160_SAVE; | return AMDGPU::SI_SPILL_V160_SAVE; | ||||
| case 24: | case 24: | ||||
| return AMDGPU::SI_SPILL_V192_SAVE; | return AMDGPU::SI_SPILL_V192_SAVE; | ||||
| case 28: | case 28: | ||||
| return AMDGPU::SI_SPILL_V224_SAVE; | return AMDGPU::SI_SPILL_V224_SAVE; | ||||
| case 32: | case 32: | ||||
| return AMDGPU::SI_SPILL_V256_SAVE; | return AMDGPU::SI_SPILL_V256_SAVE; | ||||
| case 36: | case 36: | ||||
| return AMDGPU::SI_SPILL_S288_SAVE; | return AMDGPU::SI_SPILL_V288_SAVE; | ||||
| case 40: | case 40: | ||||
| return AMDGPU::SI_SPILL_S320_SAVE; | return AMDGPU::SI_SPILL_V320_SAVE; | ||||
| case 44: | case 44: | ||||
| return AMDGPU::SI_SPILL_S352_SAVE; | return AMDGPU::SI_SPILL_V352_SAVE; | ||||
| case 48: | case 48: | ||||
| return AMDGPU::SI_SPILL_S384_SAVE; | return AMDGPU::SI_SPILL_V384_SAVE; | ||||
| case 64: | case 64: | ||||
| return AMDGPU::SI_SPILL_V512_SAVE; | return AMDGPU::SI_SPILL_V512_SAVE; | ||||
| case 128: | case 128: | ||||
| return AMDGPU::SI_SPILL_V1024_SAVE; | return AMDGPU::SI_SPILL_V1024_SAVE; | ||||
| default: | default: | ||||
| llvm_unreachable("unknown register size"); | llvm_unreachable("unknown register size"); | ||||
| } | } | ||||
| } | } | ||||
| Show All 11 Lines | static unsigned getAGPRSpillSaveOpcode(unsigned Size) { | ||||
| case 20: | case 20: | ||||
| return AMDGPU::SI_SPILL_A160_SAVE; | return AMDGPU::SI_SPILL_A160_SAVE; | ||||
| case 24: | case 24: | ||||
| return AMDGPU::SI_SPILL_A192_SAVE; | return AMDGPU::SI_SPILL_A192_SAVE; | ||||
| case 28: | case 28: | ||||
| return AMDGPU::SI_SPILL_A224_SAVE; | return AMDGPU::SI_SPILL_A224_SAVE; | ||||
| case 32: | case 32: | ||||
| return AMDGPU::SI_SPILL_A256_SAVE; | return AMDGPU::SI_SPILL_A256_SAVE; | ||||
| case 36: | |||||
| return AMDGPU::SI_SPILL_A288_SAVE; | |||||
| case 40: | |||||
| return AMDGPU::SI_SPILL_A320_SAVE; | |||||
| case 44: | |||||
| return AMDGPU::SI_SPILL_A352_SAVE; | |||||
| case 48: | |||||
| return AMDGPU::SI_SPILL_A384_SAVE; | |||||
| case 64: | case 64: | ||||
| return AMDGPU::SI_SPILL_A512_SAVE; | return AMDGPU::SI_SPILL_A512_SAVE; | ||||
| case 128: | case 128: | ||||
| return AMDGPU::SI_SPILL_A1024_SAVE; | return AMDGPU::SI_SPILL_A1024_SAVE; | ||||
| default: | default: | ||||
| llvm_unreachable("unknown register size"); | llvm_unreachable("unknown register size"); | ||||
| } | } | ||||
| } | } | ||||
| Show All 11 Lines | static unsigned getAVSpillSaveOpcode(unsigned Size) { | ||||
| case 20: | case 20: | ||||
| return AMDGPU::SI_SPILL_AV160_SAVE; | return AMDGPU::SI_SPILL_AV160_SAVE; | ||||
| case 24: | case 24: | ||||
| return AMDGPU::SI_SPILL_AV192_SAVE; | return AMDGPU::SI_SPILL_AV192_SAVE; | ||||
| case 28: | case 28: | ||||
| return AMDGPU::SI_SPILL_AV224_SAVE; | return AMDGPU::SI_SPILL_AV224_SAVE; | ||||
| case 32: | case 32: | ||||
| return AMDGPU::SI_SPILL_AV256_SAVE; | return AMDGPU::SI_SPILL_AV256_SAVE; | ||||
| case 36: | |||||
| return AMDGPU::SI_SPILL_AV288_SAVE; | |||||
| case 40: | |||||
| return AMDGPU::SI_SPILL_AV320_SAVE; | |||||
| case 44: | |||||
| return AMDGPU::SI_SPILL_AV352_SAVE; | |||||
| case 48: | |||||
| return AMDGPU::SI_SPILL_AV384_SAVE; | |||||
| case 64: | case 64: | ||||
| return AMDGPU::SI_SPILL_AV512_SAVE; | return AMDGPU::SI_SPILL_AV512_SAVE; | ||||
| case 128: | case 128: | ||||
| return AMDGPU::SI_SPILL_AV1024_SAVE; | return AMDGPU::SI_SPILL_AV1024_SAVE; | ||||
| default: | default: | ||||
| llvm_unreachable("unknown register size"); | llvm_unreachable("unknown register size"); | ||||
| } | } | ||||
| } | } | ||||
| ▲ Show 20 Lines • Show All 7,047 Lines • Show Last 20 Lines | |||||