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llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
Show First 20 Lines • Show All 524 Lines • ▼ Show 20 Lines | static const CostTblEntry VectorIntrinsicCostTable[]{ | ||||
{Intrinsic::vp_bswap, MVT::v2i64, 31}, | {Intrinsic::vp_bswap, MVT::v2i64, 31}, | ||||
{Intrinsic::vp_bswap, MVT::v4i64, 31}, | {Intrinsic::vp_bswap, MVT::v4i64, 31}, | ||||
{Intrinsic::vp_bswap, MVT::v8i64, 31}, | {Intrinsic::vp_bswap, MVT::v8i64, 31}, | ||||
{Intrinsic::vp_bswap, MVT::v16i64, 31}, | {Intrinsic::vp_bswap, MVT::v16i64, 31}, | ||||
{Intrinsic::vp_bswap, MVT::nxv1i64, 31}, | {Intrinsic::vp_bswap, MVT::nxv1i64, 31}, | ||||
{Intrinsic::vp_bswap, MVT::nxv2i64, 31}, | {Intrinsic::vp_bswap, MVT::nxv2i64, 31}, | ||||
{Intrinsic::vp_bswap, MVT::nxv4i64, 31}, | {Intrinsic::vp_bswap, MVT::nxv4i64, 31}, | ||||
{Intrinsic::vp_bswap, MVT::nxv8i64, 31}, | {Intrinsic::vp_bswap, MVT::nxv8i64, 31}, | ||||
{Intrinsic::vp_fshl, MVT::v2i8, 7}, | |||||
{Intrinsic::vp_fshl, MVT::v4i8, 7}, | |||||
{Intrinsic::vp_fshl, MVT::v8i8, 7}, | |||||
{Intrinsic::vp_fshl, MVT::v16i8, 7}, | |||||
{Intrinsic::vp_fshl, MVT::nxv1i8, 7}, | |||||
{Intrinsic::vp_fshl, MVT::nxv2i8, 7}, | |||||
{Intrinsic::vp_fshl, MVT::nxv4i8, 7}, | |||||
{Intrinsic::vp_fshl, MVT::nxv8i8, 7}, | |||||
{Intrinsic::vp_fshl, MVT::nxv16i8, 7}, | |||||
{Intrinsic::vp_fshl, MVT::nxv32i8, 7}, | |||||
{Intrinsic::vp_fshl, MVT::nxv64i8, 7}, | |||||
{Intrinsic::vp_fshl, MVT::v2i16, 7}, | |||||
{Intrinsic::vp_fshl, MVT::v4i16, 7}, | |||||
{Intrinsic::vp_fshl, MVT::v8i16, 7}, | |||||
{Intrinsic::vp_fshl, MVT::v16i16, 7}, | |||||
{Intrinsic::vp_fshl, MVT::nxv1i16, 7}, | |||||
{Intrinsic::vp_fshl, MVT::nxv2i16, 7}, | |||||
{Intrinsic::vp_fshl, MVT::nxv4i16, 7}, | |||||
{Intrinsic::vp_fshl, MVT::nxv8i16, 7}, | |||||
{Intrinsic::vp_fshl, MVT::nxv16i16, 7}, | |||||
{Intrinsic::vp_fshl, MVT::nxv32i16, 7}, | |||||
{Intrinsic::vp_fshl, MVT::v2i32, 7}, | |||||
{Intrinsic::vp_fshl, MVT::v4i32, 7}, | |||||
{Intrinsic::vp_fshl, MVT::v8i32, 7}, | |||||
{Intrinsic::vp_fshl, MVT::v16i32, 7}, | |||||
{Intrinsic::vp_fshl, MVT::nxv1i32, 7}, | |||||
{Intrinsic::vp_fshl, MVT::nxv2i32, 7}, | |||||
{Intrinsic::vp_fshl, MVT::nxv4i32, 7}, | |||||
{Intrinsic::vp_fshl, MVT::nxv8i32, 7}, | |||||
{Intrinsic::vp_fshl, MVT::nxv16i32, 7}, | |||||
{Intrinsic::vp_fshl, MVT::v2i64, 7}, | |||||
{Intrinsic::vp_fshl, MVT::v4i64, 7}, | |||||
{Intrinsic::vp_fshl, MVT::v8i64, 7}, | |||||
{Intrinsic::vp_fshl, MVT::v16i64, 7}, | |||||
{Intrinsic::vp_fshl, MVT::nxv1i64, 7}, | |||||
{Intrinsic::vp_fshl, MVT::nxv2i64, 7}, | |||||
{Intrinsic::vp_fshl, MVT::nxv4i64, 7}, | |||||
{Intrinsic::vp_fshl, MVT::nxv8i64, 7}, | |||||
{Intrinsic::vp_fshr, MVT::v2i8, 7}, | |||||
{Intrinsic::vp_fshr, MVT::v4i8, 7}, | |||||
{Intrinsic::vp_fshr, MVT::v8i8, 7}, | |||||
{Intrinsic::vp_fshr, MVT::v16i8, 7}, | |||||
{Intrinsic::vp_fshr, MVT::nxv1i8, 7}, | |||||
{Intrinsic::vp_fshr, MVT::nxv2i8, 7}, | |||||
{Intrinsic::vp_fshr, MVT::nxv4i8, 7}, | |||||
{Intrinsic::vp_fshr, MVT::nxv8i8, 7}, | |||||
{Intrinsic::vp_fshr, MVT::nxv16i8, 7}, | |||||
{Intrinsic::vp_fshr, MVT::nxv32i8, 7}, | |||||
{Intrinsic::vp_fshr, MVT::nxv64i8, 7}, | |||||
{Intrinsic::vp_fshr, MVT::v2i16, 7}, | |||||
{Intrinsic::vp_fshr, MVT::v4i16, 7}, | |||||
{Intrinsic::vp_fshr, MVT::v8i16, 7}, | |||||
{Intrinsic::vp_fshr, MVT::v16i16, 7}, | |||||
{Intrinsic::vp_fshr, MVT::nxv1i16, 7}, | |||||
{Intrinsic::vp_fshr, MVT::nxv2i16, 7}, | |||||
{Intrinsic::vp_fshr, MVT::nxv4i16, 7}, | |||||
{Intrinsic::vp_fshr, MVT::nxv8i16, 7}, | |||||
{Intrinsic::vp_fshr, MVT::nxv16i16, 7}, | |||||
{Intrinsic::vp_fshr, MVT::nxv32i16, 7}, | |||||
{Intrinsic::vp_fshr, MVT::v2i32, 7}, | |||||
{Intrinsic::vp_fshr, MVT::v4i32, 7}, | |||||
{Intrinsic::vp_fshr, MVT::v8i32, 7}, | |||||
{Intrinsic::vp_fshr, MVT::v16i32, 7}, | |||||
{Intrinsic::vp_fshr, MVT::nxv1i32, 7}, | |||||
{Intrinsic::vp_fshr, MVT::nxv2i32, 7}, | |||||
{Intrinsic::vp_fshr, MVT::nxv4i32, 7}, | |||||
{Intrinsic::vp_fshr, MVT::nxv8i32, 7}, | |||||
{Intrinsic::vp_fshr, MVT::nxv16i32, 7}, | |||||
{Intrinsic::vp_fshr, MVT::v2i64, 7}, | |||||
{Intrinsic::vp_fshr, MVT::v4i64, 7}, | |||||
{Intrinsic::vp_fshr, MVT::v8i64, 7}, | |||||
{Intrinsic::vp_fshr, MVT::v16i64, 7}, | |||||
{Intrinsic::vp_fshr, MVT::nxv1i64, 7}, | |||||
{Intrinsic::vp_fshr, MVT::nxv2i64, 7}, | |||||
{Intrinsic::vp_fshr, MVT::nxv4i64, 7}, | |||||
{Intrinsic::vp_fshr, MVT::nxv8i64, 7}, | |||||
{Intrinsic::bitreverse, MVT::v2i8, 17}, | {Intrinsic::bitreverse, MVT::v2i8, 17}, | ||||
{Intrinsic::bitreverse, MVT::v4i8, 17}, | {Intrinsic::bitreverse, MVT::v4i8, 17}, | ||||
{Intrinsic::bitreverse, MVT::v8i8, 17}, | {Intrinsic::bitreverse, MVT::v8i8, 17}, | ||||
{Intrinsic::bitreverse, MVT::v16i8, 17}, | {Intrinsic::bitreverse, MVT::v16i8, 17}, | ||||
{Intrinsic::bitreverse, MVT::nxv1i8, 17}, | {Intrinsic::bitreverse, MVT::nxv1i8, 17}, | ||||
{Intrinsic::bitreverse, MVT::nxv2i8, 17}, | {Intrinsic::bitreverse, MVT::nxv2i8, 17}, | ||||
{Intrinsic::bitreverse, MVT::nxv4i8, 17}, | {Intrinsic::bitreverse, MVT::nxv4i8, 17}, | ||||
{Intrinsic::bitreverse, MVT::nxv8i8, 17}, | {Intrinsic::bitreverse, MVT::nxv8i8, 17}, | ||||
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