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llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
| Show First 20 Lines • Show All 803 Lines • ▼ Show 20 Lines | void VectorLegalizer::Expand(SDNode *Node, SmallVectorImpl<SDValue> &Results) { | ||||
| case ISD::CTTZ: | case ISD::CTTZ: | ||||
| case ISD::CTTZ_ZERO_UNDEF: | case ISD::CTTZ_ZERO_UNDEF: | ||||
| if (SDValue Expanded = TLI.expandCTTZ(Node, DAG)) { | if (SDValue Expanded = TLI.expandCTTZ(Node, DAG)) { | ||||
| Results.push_back(Expanded); | Results.push_back(Expanded); | ||||
| return; | return; | ||||
| } | } | ||||
| break; | break; | ||||
| case ISD::FSHL: | case ISD::FSHL: | ||||
| case ISD::VP_FSHL: | |||||
| case ISD::FSHR: | case ISD::FSHR: | ||||
| case ISD::VP_FSHR: | |||||
| if (SDValue Expanded = TLI.expandFunnelShift(Node, DAG)) { | if (SDValue Expanded = TLI.expandFunnelShift(Node, DAG)) { | ||||
| Results.push_back(Expanded); | Results.push_back(Expanded); | ||||
| return; | return; | ||||
| } | } | ||||
| break; | break; | ||||
| case ISD::ROTL: | case ISD::ROTL: | ||||
| case ISD::ROTR: | case ISD::ROTR: | ||||
| if (SDValue Expanded = TLI.expandROT(Node, false /*AllowVectorOps*/, DAG)) { | if (SDValue Expanded = TLI.expandROT(Node, false /*AllowVectorOps*/, DAG)) { | ||||
| ▲ Show 20 Lines • Show All 874 Lines • Show Last 20 Lines | |||||