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Differential D139119 Diff 480490 llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-permute-rev.ll

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llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-permute-rev.ll

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; CHECK-NEXT: add sp, sp, #32 ; CHECK-NEXT: add sp, sp, #32
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp1 = load <4 x i64>, ptr %a %tmp1 = load <4 x i64>, ptr %a
%tmp2 = shufflevector <4 x i64> %tmp1, <4 x i64> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2> %tmp2 = shufflevector <4 x i64> %tmp1, <4 x i64> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
store <4 x i64> %tmp2, ptr %a store <4 x i64> %tmp2, ptr %a
ret void ret void
} }
; This is the same test as above, but with sve2p1 it can use the REVD instruction to reverse
; the double-words within quard-words.
define void @test_revdv4i64_sve2p1(ptr %a) #1 {
; CHECK-LABEL: test_revdv4i64_sve2p1:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q0, q1, [x0]
; CHECK-NEXT: ptrue p0.d, vl2
; CHECK-NEXT: revd z0.q, p0/m, z0.q
; CHECK-NEXT: revd z1.q, p0/m, z1.q
; CHECK-NEXT: stp q0, q1, [x0]
; CHECK-NEXT: ret
%tmp1 = load <4 x i64>, ptr %a
%tmp2 = shufflevector <4 x i64> %tmp1, <4 x i64> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
store <4 x i64> %tmp2, ptr %a
ret void
}
define void @test_revdv4f64_sve2p1(ptr %a) #1 {
; CHECK-LABEL: test_revdv4f64_sve2p1:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q0, q1, [x0]
; CHECK-NEXT: ptrue p0.d
; CHECK-NEXT: revd z0.q, p0/m, z0.q
; CHECK-NEXT: revd z1.q, p0/m, z1.q
; CHECK-NEXT: stp q0, q1, [x0]
; CHECK-NEXT: ret
%tmp1 = load <4 x double>, ptr %a
%tmp2 = shufflevector <4 x double> %tmp1, <4 x double> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
store <4 x double> %tmp2, ptr %a
ret void
}
define void @test_revv8i32(ptr %a) #0 { define void @test_revv8i32(ptr %a) #0 {
; CHECK-LABEL: test_revv8i32: ; CHECK-LABEL: test_revv8i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #32 ; CHECK-NEXT: sub sp, sp, #32
; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: ldp q0, q1, [x0] ; CHECK-NEXT: ldp q0, q1, [x0]
; CHECK-NEXT: mov z2.s, z0.s[1] ; CHECK-NEXT: mov z2.s, z0.s[1]
; CHECK-NEXT: mov z3.s, z0.s[2] ; CHECK-NEXT: mov z3.s, z0.s[2]
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; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp1 = load <8 x i32>, ptr %a %tmp1 = load <8 x i32>, ptr %a
%tmp2 = shufflevector <8 x i32> %tmp1, <8 x i32> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0> %tmp2 = shufflevector <8 x i32> %tmp1, <8 x i32> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
store <8 x i32> %tmp2, ptr %a store <8 x i32> %tmp2, ptr %a
ret void ret void
} }
attributes #0 = { "target-features"="+sve" } attributes #0 = { "target-features"="+sve" }
attributes #1 = { "target-features"="+sve2p1" }