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Differential D139119 Diff 480490 llvm/test/CodeGen/AArch64/sve-fixed-length-permute-rev.ll

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llvm/test/CodeGen/AArch64/sve-fixed-length-permute-rev.ll

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; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload ; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp1 = load <4 x i64>, ptr %a %tmp1 = load <4 x i64>, ptr %a
%tmp2 = shufflevector <4 x i64> %tmp1, <4 x i64> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2> %tmp2 = shufflevector <4 x i64> %tmp1, <4 x i64> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
store <4 x i64> %tmp2, ptr %a store <4 x i64> %tmp2, ptr %a
ret void ret void
} }
; This is the same test as above, but with sve2p1 it can use the REVD instruction to reverse
; the double-words within quard-words.
define void @test_revdv4i64_sve2p1(ptr %a) #2 {
; CHECK-LABEL: test_revdv4i64_sve2p1:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.d, vl4
; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]
; CHECK-NEXT: revd z0.q, p0/m, z0.q
; CHECK-NEXT: st1d { z0.d }, p0, [x0]
; CHECK-NEXT: ret
%tmp1 = load <4 x i64>, ptr %a
%tmp2 = shufflevector <4 x i64> %tmp1, <4 x i64> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
store <4 x i64> %tmp2, ptr %a
ret void
}
define void @test_revdv4f64_sve2p1(ptr %a) #2 {
; CHECK-LABEL: test_revdv4f64_sve2p1:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.d, vl4
; CHECK-NEXT: ptrue p1.d
; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]
; CHECK-NEXT: revd z0.q, p1/m, z0.q
; CHECK-NEXT: st1d { z0.d }, p0, [x0]
; CHECK-NEXT: ret
%tmp1 = load <4 x double>, ptr %a
%tmp2 = shufflevector <4 x double> %tmp1, <4 x double> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
store <4 x double> %tmp2, ptr %a
ret void
}
; REV instruction will reverse the order of all elements in the vector. ; REV instruction will reverse the order of all elements in the vector.
; When the vector length and the target register size are inconsistent, ; When the vector length and the target register size are inconsistent,
; the correctness of generated REV instruction for shuffle pattern cannot be guaranteed. ; the correctness of generated REV instruction for shuffle pattern cannot be guaranteed.
; sve-vector-bits-min=256, sve-vector-bits-max is not set, REV inst can't be generated. ; sve-vector-bits-min=256, sve-vector-bits-max is not set, REV inst can't be generated.
define void @test_revv8i32(ptr %a) #0 { define void @test_revv8i32(ptr %a) #0 {
; CHECK-LABEL: test_revv8i32: ; CHECK-LABEL: test_revv8i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
▲ Show 20 Lines • Show All 233 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
%tmp2 = load <8 x i16>, ptr %b %tmp2 = load <8 x i16>, ptr %b
%tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <16 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4, i32 11, i32 10, i32 9, i32 8, i32 15, i32 14, i32 13, i32 12> %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <16 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4, i32 11, i32 10, i32 9, i32 8, i32 15, i32 14, i32 13, i32 12>
store <16 x i16> %tmp3, ptr %c store <16 x i16> %tmp3, ptr %c
ret void ret void
} }
attributes #0 = { "target-features"="+sve" } attributes #0 = { "target-features"="+sve" }
attributes #1 = { "target-features"="+sve" vscale_range(2,2) } attributes #1 = { "target-features"="+sve" vscale_range(2,2) }
attributes #2 = { "target-features"="+sve2p1" }