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llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
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Show First 20 Lines • Show All 10,641 Lines • ▼ Show 20 Lines | static bool isEXTMask(ArrayRef<int> M, EVT VT, bool &ReverseEXT, | ||||
return true; | return true; | ||||
} | } | ||||
/// isREVMask - Check if a vector shuffle corresponds to a REV | /// isREVMask - Check if a vector shuffle corresponds to a REV | ||||
/// instruction with the specified blocksize. (The order of the elements | /// instruction with the specified blocksize. (The order of the elements | ||||
/// within each block of the vector is reversed.) | /// within each block of the vector is reversed.) | ||||
static bool isREVMask(ArrayRef<int> M, EVT VT, unsigned BlockSize) { | static bool isREVMask(ArrayRef<int> M, EVT VT, unsigned BlockSize) { | ||||
assert((BlockSize == 16 || BlockSize == 32 || BlockSize == 64) && | assert((BlockSize == 16 || BlockSize == 32 || BlockSize == 64 || | ||||
"Only possible block sizes for REV are: 16, 32, 64"); | BlockSize == 128) && | ||||
"Only possible block sizes for REV are: 16, 32, 64, 128"); | |||||
paulwalker-arm: Please update the string to include the new block size. | |||||
unsigned EltSz = VT.getScalarSizeInBits(); | unsigned EltSz = VT.getScalarSizeInBits(); | ||||
if (EltSz == 64) | |||||
return false; | |||||
unsigned NumElts = VT.getVectorNumElements(); | unsigned NumElts = VT.getVectorNumElements(); | ||||
Perhaps this block can be removed? There's the BlockSize <= EltSz check just below which seems to handle this? paulwalker-arm: Perhaps this block can be removed? There's the `BlockSize <= EltSz` check just below which… | |||||
unsigned BlockElts = M[0] + 1; | unsigned BlockElts = M[0] + 1; | ||||
// If the first shuffle index is UNDEF, be optimistic. | // If the first shuffle index is UNDEF, be optimistic. | ||||
if (M[0] < 0) | if (M[0] < 0) | ||||
BlockElts = BlockSize / EltSz; | BlockElts = BlockSize / EltSz; | ||||
if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz) | if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz) | ||||
return false; | return false; | ||||
▲ Show 20 Lines • Show All 12,584 Lines • ▼ Show 20 Lines | if (isREVMask(ShuffleMask, VT, LaneSize)) { | ||||
Op = DAG.getNode(ISD::BITCAST, DL, NewVT, Op1); | Op = DAG.getNode(ISD::BITCAST, DL, NewVT, Op1); | ||||
Op = LowerToPredicatedOp(Op, DAG, RevOp); | Op = LowerToPredicatedOp(Op, DAG, RevOp); | ||||
Op = DAG.getNode(ISD::BITCAST, DL, ContainerVT, Op); | Op = DAG.getNode(ISD::BITCAST, DL, ContainerVT, Op); | ||||
return convertFromScalableVector(DAG, VT, Op); | return convertFromScalableVector(DAG, VT, Op); | ||||
} | } | ||||
} | } | ||||
if (Subtarget->hasSVE2p1() && VT.getScalarSizeInBits() == 64 && | |||||
isREVMask(ShuffleMask, VT, 128)) { | |||||
Not Done ReplyInline ActionsPerhaps worth putting VT.getScalarSizeInBits() == 64 before the called to isREVMask so we bail out earlier. paulwalker-arm: Perhaps worth putting `VT.getScalarSizeInBits() == 64` before the called to `isREVMask` so we… | |||||
good point, I've done that before committing! sdesmalen: good point, I've done that before committing! | |||||
if (!VT.isFloatingPoint()) | |||||
return LowerToPredicatedOp(Op, DAG, AArch64ISD::REVD_MERGE_PASSTHRU); | |||||
EVT NewVT = getPackedSVEVectorVT(EVT::getIntegerVT(*DAG.getContext(), 64)); | |||||
Op = DAG.getNode(ISD::BITCAST, DL, NewVT, Op1); | |||||
Op = LowerToPredicatedOp(Op, DAG, AArch64ISD::REVD_MERGE_PASSTHRU); | |||||
Op = DAG.getNode(ISD::BITCAST, DL, ContainerVT, Op); | |||||
return convertFromScalableVector(DAG, VT, Op); | |||||
} | |||||
unsigned WhichResult; | unsigned WhichResult; | ||||
if (isZIPMask(ShuffleMask, VT, WhichResult) && WhichResult == 0) | if (isZIPMask(ShuffleMask, VT, WhichResult) && WhichResult == 0) | ||||
return convertFromScalableVector( | return convertFromScalableVector( | ||||
DAG, VT, DAG.getNode(AArch64ISD::ZIP1, DL, ContainerVT, Op1, Op2)); | DAG, VT, DAG.getNode(AArch64ISD::ZIP1, DL, ContainerVT, Op1, Op2)); | ||||
if (isTRNMask(ShuffleMask, VT, WhichResult)) { | if (isTRNMask(ShuffleMask, VT, WhichResult)) { | ||||
unsigned Opc = (WhichResult == 0) ? AArch64ISD::TRN1 : AArch64ISD::TRN2; | unsigned Opc = (WhichResult == 0) ? AArch64ISD::TRN1 : AArch64ISD::TRN2; | ||||
return convertFromScalableVector( | return convertFromScalableVector( | ||||
▲ Show 20 Lines • Show All 279 Lines • Show Last 20 Lines |
Please update the string to include the new block size.