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Differential D136263 Diff 480389 llvm/test/CodeGen/RISCV/rvv/vpscatter-sdnode.ll

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llvm/test/CodeGen/RISCV/rvv/vpscatter-sdnode.ll

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; ;
; RV64-LABEL: vpscatter_nxv16f64: ; RV64-LABEL: vpscatter_nxv16f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: addi sp, sp, -16 ; RV64-NEXT: addi sp, sp, -16
; RV64-NEXT: .cfi_def_cfa_offset 16 ; RV64-NEXT: .cfi_def_cfa_offset 16
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: slli a1, a1, 3 ; RV64-NEXT: slli a1, a1, 3
; RV64-NEXT: sub sp, sp, a1 ; RV64-NEXT: sub sp, sp, a1
; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: slli a3, a1, 3 ; RV64-NEXT: slli a3, a1, 3
; RV64-NEXT: add a3, a0, a3 ; RV64-NEXT: add a3, a0, a3
; RV64-NEXT: vl8re64.v v24, (a3) ; RV64-NEXT: vl8re64.v v24, (a3)
; RV64-NEXT: addi a3, sp, 16 ; RV64-NEXT: addi a3, sp, 16
; RV64-NEXT: vs8r.v v24, (a3) # Unknown-size Folded Spill ; RV64-NEXT: vs8r.v v24, (a3) # Unknown-size Folded Spill
; RV64-NEXT: vl8re64.v v24, (a0) ; RV64-NEXT: vl8re64.v v24, (a0)
; RV64-NEXT: mv a0, a2 ; RV64-NEXT: mv a0, a2
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; ;
; RV64-LABEL: vpscatter_baseidx_nxv16i16_nxv16f64: ; RV64-LABEL: vpscatter_baseidx_nxv16i16_nxv16f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: addi sp, sp, -16 ; RV64-NEXT: addi sp, sp, -16
; RV64-NEXT: .cfi_def_cfa_offset 16 ; RV64-NEXT: .cfi_def_cfa_offset 16
; RV64-NEXT: csrr a3, vlenb ; RV64-NEXT: csrr a3, vlenb
; RV64-NEXT: slli a3, a3, 4 ; RV64-NEXT: slli a3, a3, 4
; RV64-NEXT: sub sp, sp, a3 ; RV64-NEXT: sub sp, sp, a3
; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
; RV64-NEXT: vl4re16.v v24, (a1) ; RV64-NEXT: vl4re16.v v24, (a1)
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: slli a1, a1, 3 ; RV64-NEXT: slli a1, a1, 3
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill ; RV64-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma
; RV64-NEXT: vsext.vf4 v16, v26 ; RV64-NEXT: vsext.vf4 v16, v26
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; ;
; RV64-LABEL: vpscatter_baseidx_sext_nxv16i16_nxv16f64: ; RV64-LABEL: vpscatter_baseidx_sext_nxv16i16_nxv16f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: addi sp, sp, -16 ; RV64-NEXT: addi sp, sp, -16
; RV64-NEXT: .cfi_def_cfa_offset 16 ; RV64-NEXT: .cfi_def_cfa_offset 16
; RV64-NEXT: csrr a3, vlenb ; RV64-NEXT: csrr a3, vlenb
; RV64-NEXT: slli a3, a3, 4 ; RV64-NEXT: slli a3, a3, 4
; RV64-NEXT: sub sp, sp, a3 ; RV64-NEXT: sub sp, sp, a3
; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
; RV64-NEXT: vl4re16.v v24, (a1) ; RV64-NEXT: vl4re16.v v24, (a1)
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: slli a1, a1, 3 ; RV64-NEXT: slli a1, a1, 3
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill ; RV64-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma
; RV64-NEXT: vsext.vf4 v16, v26 ; RV64-NEXT: vsext.vf4 v16, v26
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; ;
; RV64-LABEL: vpscatter_baseidx_zext_nxv16i16_nxv16f64: ; RV64-LABEL: vpscatter_baseidx_zext_nxv16i16_nxv16f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: addi sp, sp, -16 ; RV64-NEXT: addi sp, sp, -16
; RV64-NEXT: .cfi_def_cfa_offset 16 ; RV64-NEXT: .cfi_def_cfa_offset 16
; RV64-NEXT: csrr a3, vlenb ; RV64-NEXT: csrr a3, vlenb
; RV64-NEXT: slli a3, a3, 4 ; RV64-NEXT: slli a3, a3, 4
; RV64-NEXT: sub sp, sp, a3 ; RV64-NEXT: sub sp, sp, a3
; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
; RV64-NEXT: vl4re16.v v24, (a1) ; RV64-NEXT: vl4re16.v v24, (a1)
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: slli a1, a1, 3 ; RV64-NEXT: slli a1, a1, 3
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill ; RV64-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma
; RV64-NEXT: vzext.vf4 v16, v26 ; RV64-NEXT: vzext.vf4 v16, v26
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