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Differential D136263 Diff 480389 llvm/test/CodeGen/RISCV/rvv/strided-vpstore.ll

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llvm/test/CodeGen/RISCV/rvv/strided-vpstore.ll

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; CHECK-RV32-NEXT: # %bb.3: ; CHECK-RV32-NEXT: # %bb.3:
; CHECK-RV32-NEXT: mv a7, a4 ; CHECK-RV32-NEXT: mv a7, a4
; CHECK-RV32-NEXT: .LBB36_4: ; CHECK-RV32-NEXT: .LBB36_4:
; CHECK-RV32-NEXT: addi sp, sp, -16 ; CHECK-RV32-NEXT: addi sp, sp, -16
; CHECK-RV32-NEXT: .cfi_def_cfa_offset 16 ; CHECK-RV32-NEXT: .cfi_def_cfa_offset 16
; CHECK-RV32-NEXT: csrr t0, vlenb ; CHECK-RV32-NEXT: csrr t0, vlenb
; CHECK-RV32-NEXT: slli t0, t0, 3 ; CHECK-RV32-NEXT: slli t0, t0, 3
; CHECK-RV32-NEXT: sub sp, sp, t0 ; CHECK-RV32-NEXT: sub sp, sp, t0
; CHECK-RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; CHECK-RV32-NEXT: vl8re64.v v0, (a0) ; CHECK-RV32-NEXT: vl8re64.v v0, (a0)
; CHECK-RV32-NEXT: addi a0, sp, 16 ; CHECK-RV32-NEXT: addi a0, sp, 16
; CHECK-RV32-NEXT: vs8r.v v0, (a0) # Unknown-size Folded Spill ; CHECK-RV32-NEXT: vs8r.v v0, (a0) # Unknown-size Folded Spill
; CHECK-RV32-NEXT: vsetvli zero, a7, e64, m8, ta, ma ; CHECK-RV32-NEXT: vsetvli zero, a7, e64, m8, ta, ma
; CHECK-RV32-NEXT: vmv1r.v v0, v24 ; CHECK-RV32-NEXT: vmv1r.v v0, v24
; CHECK-RV32-NEXT: vsse64.v v8, (a1), a2, v0.t ; CHECK-RV32-NEXT: vsse64.v v8, (a1), a2, v0.t
; CHECK-RV32-NEXT: sub a0, a5, a4 ; CHECK-RV32-NEXT: sub a0, a5, a4
; CHECK-RV32-NEXT: sltu t0, a5, a0 ; CHECK-RV32-NEXT: sltu t0, a5, a0
▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
; CHECK-RV64-NEXT: # %bb.3: ; CHECK-RV64-NEXT: # %bb.3:
; CHECK-RV64-NEXT: mv a7, a4 ; CHECK-RV64-NEXT: mv a7, a4
; CHECK-RV64-NEXT: .LBB36_4: ; CHECK-RV64-NEXT: .LBB36_4:
; CHECK-RV64-NEXT: addi sp, sp, -16 ; CHECK-RV64-NEXT: addi sp, sp, -16
; CHECK-RV64-NEXT: .cfi_def_cfa_offset 16 ; CHECK-RV64-NEXT: .cfi_def_cfa_offset 16
; CHECK-RV64-NEXT: csrr t0, vlenb ; CHECK-RV64-NEXT: csrr t0, vlenb
; CHECK-RV64-NEXT: slli t0, t0, 3 ; CHECK-RV64-NEXT: slli t0, t0, 3
; CHECK-RV64-NEXT: sub sp, sp, t0 ; CHECK-RV64-NEXT: sub sp, sp, t0
; CHECK-RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; CHECK-RV64-NEXT: vl8re64.v v0, (a0) ; CHECK-RV64-NEXT: vl8re64.v v0, (a0)
; CHECK-RV64-NEXT: addi a0, sp, 16 ; CHECK-RV64-NEXT: addi a0, sp, 16
; CHECK-RV64-NEXT: vs8r.v v0, (a0) # Unknown-size Folded Spill ; CHECK-RV64-NEXT: vs8r.v v0, (a0) # Unknown-size Folded Spill
; CHECK-RV64-NEXT: vsetvli zero, a7, e64, m8, ta, ma ; CHECK-RV64-NEXT: vsetvli zero, a7, e64, m8, ta, ma
; CHECK-RV64-NEXT: vmv1r.v v0, v24 ; CHECK-RV64-NEXT: vmv1r.v v0, v24
; CHECK-RV64-NEXT: vsse64.v v8, (a1), a2, v0.t ; CHECK-RV64-NEXT: vsse64.v v8, (a1), a2, v0.t
; CHECK-RV64-NEXT: sub a0, a5, a4 ; CHECK-RV64-NEXT: sub a0, a5, a4
; CHECK-RV64-NEXT: sltu t0, a5, a0 ; CHECK-RV64-NEXT: sltu t0, a5, a0
Show All 36 Lines