Page MenuHomePhabricator
Differential D136263 Diff 480389 llvm/test/CodeGen/RISCV/rvv/localvar.ll

Changeset View

Standalone View

View Options

llvm/test/CodeGen/RISCV/rvv/localvar.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+v < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+v < %s \
; RUN: | FileCheck %s -check-prefix=RV64IV ; RUN: | FileCheck %s -check-prefix=RV64IV
define void @local_var_mf8() { define void @local_var_mf8() {
; RV64IV-LABEL: local_var_mf8: ; RV64IV-LABEL: local_var_mf8:
; RV64IV: # %bb.0: ; RV64IV: # %bb.0:
; RV64IV-NEXT: addi sp, sp, -16 ; RV64IV-NEXT: addi sp, sp, -16
; RV64IV-NEXT: .cfi_def_cfa_offset 16 ; RV64IV-NEXT: .cfi_def_cfa_offset 16
; RV64IV-NEXT: csrr a0, vlenb ; RV64IV-NEXT: csrr a0, vlenb
; RV64IV-NEXT: slli a0, a0, 1 ; RV64IV-NEXT: slli a0, a0, 1
; RV64IV-NEXT: sub sp, sp, a0 ; RV64IV-NEXT: sub sp, sp, a0
; RV64IV-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 2 * vlenb
; RV64IV-NEXT: csrr a0, vlenb ; RV64IV-NEXT: csrr a0, vlenb
; RV64IV-NEXT: add a0, sp, a0 ; RV64IV-NEXT: add a0, sp, a0
; RV64IV-NEXT: addi a0, a0, 16 ; RV64IV-NEXT: addi a0, a0, 16
; RV64IV-NEXT: vsetvli a1, zero, e8, mf8, ta, ma ; RV64IV-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
; RV64IV-NEXT: vle8.v v8, (a0) ; RV64IV-NEXT: vle8.v v8, (a0)
; RV64IV-NEXT: addi a0, sp, 16 ; RV64IV-NEXT: addi a0, sp, 16
; RV64IV-NEXT: vle8.v v8, (a0) ; RV64IV-NEXT: vle8.v v8, (a0)
; RV64IV-NEXT: csrr a0, vlenb ; RV64IV-NEXT: csrr a0, vlenb
Show All 11 Lines
define void @local_var_m1() { define void @local_var_m1() {
; RV64IV-LABEL: local_var_m1: ; RV64IV-LABEL: local_var_m1:
; RV64IV: # %bb.0: ; RV64IV: # %bb.0:
; RV64IV-NEXT: addi sp, sp, -16 ; RV64IV-NEXT: addi sp, sp, -16
; RV64IV-NEXT: .cfi_def_cfa_offset 16 ; RV64IV-NEXT: .cfi_def_cfa_offset 16
; RV64IV-NEXT: csrr a0, vlenb ; RV64IV-NEXT: csrr a0, vlenb
; RV64IV-NEXT: slli a0, a0, 1 ; RV64IV-NEXT: slli a0, a0, 1
; RV64IV-NEXT: sub sp, sp, a0 ; RV64IV-NEXT: sub sp, sp, a0
; RV64IV-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 2 * vlenb
; RV64IV-NEXT: csrr a0, vlenb ; RV64IV-NEXT: csrr a0, vlenb
; RV64IV-NEXT: add a0, sp, a0 ; RV64IV-NEXT: add a0, sp, a0
; RV64IV-NEXT: addi a0, a0, 16 ; RV64IV-NEXT: addi a0, a0, 16
; RV64IV-NEXT: vl1r.v v8, (a0) ; RV64IV-NEXT: vl1r.v v8, (a0)
; RV64IV-NEXT: addi a0, sp, 16 ; RV64IV-NEXT: addi a0, sp, 16
; RV64IV-NEXT: vl1r.v v8, (a0) ; RV64IV-NEXT: vl1r.v v8, (a0)
; RV64IV-NEXT: csrr a0, vlenb ; RV64IV-NEXT: csrr a0, vlenb
; RV64IV-NEXT: slli a0, a0, 1 ; RV64IV-NEXT: slli a0, a0, 1
Show All 10 Lines
define void @local_var_m2() { define void @local_var_m2() {
; RV64IV-LABEL: local_var_m2: ; RV64IV-LABEL: local_var_m2:
; RV64IV: # %bb.0: ; RV64IV: # %bb.0:
; RV64IV-NEXT: addi sp, sp, -16 ; RV64IV-NEXT: addi sp, sp, -16
; RV64IV-NEXT: .cfi_def_cfa_offset 16 ; RV64IV-NEXT: .cfi_def_cfa_offset 16
; RV64IV-NEXT: csrr a0, vlenb ; RV64IV-NEXT: csrr a0, vlenb
; RV64IV-NEXT: slli a0, a0, 2 ; RV64IV-NEXT: slli a0, a0, 2
; RV64IV-NEXT: sub sp, sp, a0 ; RV64IV-NEXT: sub sp, sp, a0
; RV64IV-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x04, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 4 * vlenb
; RV64IV-NEXT: csrr a0, vlenb ; RV64IV-NEXT: csrr a0, vlenb
; RV64IV-NEXT: slli a0, a0, 1 ; RV64IV-NEXT: slli a0, a0, 1
; RV64IV-NEXT: add a0, sp, a0 ; RV64IV-NEXT: add a0, sp, a0
; RV64IV-NEXT: addi a0, a0, 16 ; RV64IV-NEXT: addi a0, a0, 16
; RV64IV-NEXT: vl2r.v v8, (a0) ; RV64IV-NEXT: vl2r.v v8, (a0)
; RV64IV-NEXT: addi a0, sp, 16 ; RV64IV-NEXT: addi a0, sp, 16
; RV64IV-NEXT: vl2r.v v8, (a0) ; RV64IV-NEXT: vl2r.v v8, (a0)
; RV64IV-NEXT: csrr a0, vlenb ; RV64IV-NEXT: csrr a0, vlenb
▲ Show 20 Lines • Show All 79 Lines • ▼ Show 20 Lines
define void @local_var_m2_mix_local_scalar() { define void @local_var_m2_mix_local_scalar() {
; RV64IV-LABEL: local_var_m2_mix_local_scalar: ; RV64IV-LABEL: local_var_m2_mix_local_scalar:
; RV64IV: # %bb.0: ; RV64IV: # %bb.0:
; RV64IV-NEXT: addi sp, sp, -16 ; RV64IV-NEXT: addi sp, sp, -16
; RV64IV-NEXT: .cfi_def_cfa_offset 16 ; RV64IV-NEXT: .cfi_def_cfa_offset 16
; RV64IV-NEXT: csrr a0, vlenb ; RV64IV-NEXT: csrr a0, vlenb
; RV64IV-NEXT: slli a0, a0, 2 ; RV64IV-NEXT: slli a0, a0, 2
; RV64IV-NEXT: sub sp, sp, a0 ; RV64IV-NEXT: sub sp, sp, a0
; RV64IV-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x04, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 4 * vlenb
; RV64IV-NEXT: lw a0, 12(sp) ; RV64IV-NEXT: lw a0, 12(sp)
; RV64IV-NEXT: csrr a0, vlenb ; RV64IV-NEXT: csrr a0, vlenb
; RV64IV-NEXT: slli a0, a0, 1 ; RV64IV-NEXT: slli a0, a0, 1
; RV64IV-NEXT: add a0, sp, a0 ; RV64IV-NEXT: add a0, sp, a0
; RV64IV-NEXT: addi a0, a0, 16 ; RV64IV-NEXT: addi a0, a0, 16
; RV64IV-NEXT: vl2r.v v8, (a0) ; RV64IV-NEXT: vl2r.v v8, (a0)
; RV64IV-NEXT: addi a0, sp, 16 ; RV64IV-NEXT: addi a0, sp, 16
; RV64IV-NEXT: vl2r.v v8, (a0) ; RV64IV-NEXT: vl2r.v v8, (a0)
▲ Show 20 Lines • Show All 150 Lines • Show Last 20 Lines