Page MenuHomePhabricator
Differential D136263 Diff 480389 llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll

Changeset View

Standalone View

View Options

llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll

Show First 20 Lines • Show All 1,037 Lines • ▼ Show 20 Lines
; RV32-LABEL: vp_bswap_nxv7i64: ; RV32-LABEL: vp_bswap_nxv7i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: csrr a1, vlenb ; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: li a2, 24 ; RV32-NEXT: li a2, 24
; RV32-NEXT: mul a1, a1, a2 ; RV32-NEXT: mul a1, a1, a2
; RV32-NEXT: sub sp, sp, a1 ; RV32-NEXT: sub sp, sp, a1
; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb
; RV32-NEXT: sw zero, 12(sp) ; RV32-NEXT: sw zero, 12(sp)
; RV32-NEXT: lui a1, 1044480 ; RV32-NEXT: lui a1, 1044480
; RV32-NEXT: sw a1, 8(sp) ; RV32-NEXT: sw a1, 8(sp)
; RV32-NEXT: li a1, 56 ; RV32-NEXT: li a1, 56
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vsll.vx v16, v8, a1, v0.t ; RV32-NEXT: vsll.vx v16, v8, a1, v0.t
; RV32-NEXT: lui a2, 16 ; RV32-NEXT: lui a2, 16
; RV32-NEXT: addi a2, a2, -256 ; RV32-NEXT: addi a2, a2, -256
▲ Show 20 Lines • Show All 70 Lines • ▼ Show 20 Lines
; ;
; RV64-LABEL: vp_bswap_nxv7i64: ; RV64-LABEL: vp_bswap_nxv7i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: addi sp, sp, -16 ; RV64-NEXT: addi sp, sp, -16
; RV64-NEXT: .cfi_def_cfa_offset 16 ; RV64-NEXT: .cfi_def_cfa_offset 16
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: slli a1, a1, 3 ; RV64-NEXT: slli a1, a1, 3
; RV64-NEXT: sub sp, sp, a1 ; RV64-NEXT: sub sp, sp, a1
; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; RV64-NEXT: lui a1, 4080 ; RV64-NEXT: lui a1, 4080
; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV64-NEXT: vand.vx v16, v8, a1, v0.t ; RV64-NEXT: vand.vx v16, v8, a1, v0.t
; RV64-NEXT: vsll.vi v16, v16, 24, v0.t ; RV64-NEXT: vsll.vi v16, v16, 24, v0.t
; RV64-NEXT: li a0, 255 ; RV64-NEXT: li a0, 255
; RV64-NEXT: slli a0, a0, 24 ; RV64-NEXT: slli a0, a0, 24
; RV64-NEXT: vand.vx v24, v8, a0, v0.t ; RV64-NEXT: vand.vx v24, v8, a0, v0.t
; RV64-NEXT: vsll.vi v24, v24, 8, v0.t ; RV64-NEXT: vsll.vi v24, v24, 8, v0.t
Show All 38 Lines
define <vscale x 7 x i64> @vp_bswap_nxv7i64_unmasked(<vscale x 7 x i64> %va, i32 zeroext %evl) { define <vscale x 7 x i64> @vp_bswap_nxv7i64_unmasked(<vscale x 7 x i64> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_bswap_nxv7i64_unmasked: ; RV32-LABEL: vp_bswap_nxv7i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: csrr a1, vlenb ; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: slli a1, a1, 3 ; RV32-NEXT: slli a1, a1, 3
; RV32-NEXT: sub sp, sp, a1 ; RV32-NEXT: sub sp, sp, a1
; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; RV32-NEXT: sw zero, 12(sp) ; RV32-NEXT: sw zero, 12(sp)
; RV32-NEXT: lui a1, 1044480 ; RV32-NEXT: lui a1, 1044480
; RV32-NEXT: sw a1, 8(sp) ; RV32-NEXT: sw a1, 8(sp)
; RV32-NEXT: li a1, 56 ; RV32-NEXT: li a1, 56
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vsll.vx v16, v8, a1 ; RV32-NEXT: vsll.vx v16, v8, a1
; RV32-NEXT: lui a2, 16 ; RV32-NEXT: lui a2, 16
; RV32-NEXT: addi a2, a2, -256 ; RV32-NEXT: addi a2, a2, -256
▲ Show 20 Lines • Show All 81 Lines • ▼ Show 20 Lines
; RV32-LABEL: vp_bswap_nxv8i64: ; RV32-LABEL: vp_bswap_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: csrr a1, vlenb ; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: li a2, 24 ; RV32-NEXT: li a2, 24
; RV32-NEXT: mul a1, a1, a2 ; RV32-NEXT: mul a1, a1, a2
; RV32-NEXT: sub sp, sp, a1 ; RV32-NEXT: sub sp, sp, a1
; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb
; RV32-NEXT: sw zero, 12(sp) ; RV32-NEXT: sw zero, 12(sp)
; RV32-NEXT: lui a1, 1044480 ; RV32-NEXT: lui a1, 1044480
; RV32-NEXT: sw a1, 8(sp) ; RV32-NEXT: sw a1, 8(sp)
; RV32-NEXT: li a1, 56 ; RV32-NEXT: li a1, 56
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vsll.vx v16, v8, a1, v0.t ; RV32-NEXT: vsll.vx v16, v8, a1, v0.t
; RV32-NEXT: lui a2, 16 ; RV32-NEXT: lui a2, 16
; RV32-NEXT: addi a2, a2, -256 ; RV32-NEXT: addi a2, a2, -256
▲ Show 20 Lines • Show All 70 Lines • ▼ Show 20 Lines
; ;
; RV64-LABEL: vp_bswap_nxv8i64: ; RV64-LABEL: vp_bswap_nxv8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: addi sp, sp, -16 ; RV64-NEXT: addi sp, sp, -16
; RV64-NEXT: .cfi_def_cfa_offset 16 ; RV64-NEXT: .cfi_def_cfa_offset 16
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: slli a1, a1, 3 ; RV64-NEXT: slli a1, a1, 3
; RV64-NEXT: sub sp, sp, a1 ; RV64-NEXT: sub sp, sp, a1
; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; RV64-NEXT: lui a1, 4080 ; RV64-NEXT: lui a1, 4080
; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV64-NEXT: vand.vx v16, v8, a1, v0.t ; RV64-NEXT: vand.vx v16, v8, a1, v0.t
; RV64-NEXT: vsll.vi v16, v16, 24, v0.t ; RV64-NEXT: vsll.vi v16, v16, 24, v0.t
; RV64-NEXT: li a0, 255 ; RV64-NEXT: li a0, 255
; RV64-NEXT: slli a0, a0, 24 ; RV64-NEXT: slli a0, a0, 24
; RV64-NEXT: vand.vx v24, v8, a0, v0.t ; RV64-NEXT: vand.vx v24, v8, a0, v0.t
; RV64-NEXT: vsll.vi v24, v24, 8, v0.t ; RV64-NEXT: vsll.vi v24, v24, 8, v0.t
Show All 38 Lines
define <vscale x 8 x i64> @vp_bswap_nxv8i64_unmasked(<vscale x 8 x i64> %va, i32 zeroext %evl) { define <vscale x 8 x i64> @vp_bswap_nxv8i64_unmasked(<vscale x 8 x i64> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_bswap_nxv8i64_unmasked: ; RV32-LABEL: vp_bswap_nxv8i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: csrr a1, vlenb ; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: slli a1, a1, 3 ; RV32-NEXT: slli a1, a1, 3
; RV32-NEXT: sub sp, sp, a1 ; RV32-NEXT: sub sp, sp, a1
; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; RV32-NEXT: sw zero, 12(sp) ; RV32-NEXT: sw zero, 12(sp)
; RV32-NEXT: lui a1, 1044480 ; RV32-NEXT: lui a1, 1044480
; RV32-NEXT: sw a1, 8(sp) ; RV32-NEXT: sw a1, 8(sp)
; RV32-NEXT: li a1, 56 ; RV32-NEXT: li a1, 56
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vsll.vx v16, v8, a1 ; RV32-NEXT: vsll.vx v16, v8, a1
; RV32-NEXT: lui a2, 16 ; RV32-NEXT: lui a2, 16
; RV32-NEXT: addi a2, a2, -256 ; RV32-NEXT: addi a2, a2, -256
▲ Show 20 Lines • Show All 81 Lines • ▼ Show 20 Lines
define <vscale x 64 x i16> @vp_bswap_nxv64i16(<vscale x 64 x i16> %va, <vscale x 64 x i1> %m, i32 zeroext %evl) { define <vscale x 64 x i16> @vp_bswap_nxv64i16(<vscale x 64 x i16> %va, <vscale x 64 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_bswap_nxv64i16: ; CHECK-LABEL: vp_bswap_nxv64i16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 4 ; CHECK-NEXT: slli a1, a1, 4
; CHECK-NEXT: sub sp, sp, a1 ; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
; CHECK-NEXT: vmv1r.v v24, v0 ; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 3 ; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: add a1, sp, a1 ; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16 ; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: srli a2, a1, 1 ; CHECK-NEXT: srli a2, a1, 1
▲ Show 20 Lines • Show All 65 Lines • Show Last 20 Lines