Differential D136263 Diff 480389 llvm/test/CodeGen/RISCV/rvv/access-fixed-objects-by-rvv.ll

Changeset View

Standalone View

	Show All 30 Lines
	define <vscale x 1 x i64> @access_fixed_and_vector_objects(i64 *%val) {			define <vscale x 1 x i64> @access_fixed_and_vector_objects(i64 *%val) {
	; RV64IV-LABEL: access_fixed_and_vector_objects:			; RV64IV-LABEL: access_fixed_and_vector_objects:
	; RV64IV: # %bb.0:			; RV64IV: # %bb.0:
	; RV64IV-NEXT: addi sp, sp, -528			; RV64IV-NEXT: addi sp, sp, -528
	; RV64IV-NEXT: .cfi_def_cfa_offset 528			; RV64IV-NEXT: .cfi_def_cfa_offset 528
	; RV64IV-NEXT: csrr a0, vlenb			; RV64IV-NEXT: csrr a0, vlenb
	; RV64IV-NEXT: slli a0, a0, 1			; RV64IV-NEXT: slli a0, a0, 1
	; RV64IV-NEXT: sub sp, sp, a0			; RV64IV-NEXT: sub sp, sp, a0
				; RV64IV-NEXT: .cfi_escape 0x0f, 0x0e, 0x72, 0x00, 0x11, 0x90, 0x04, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 528 + 2 * vlenb
	; RV64IV-NEXT: addi a0, sp, 8			; RV64IV-NEXT: addi a0, sp, 8
	; RV64IV-NEXT: vl1re64.v v8, (a0)			; RV64IV-NEXT: vl1re64.v v8, (a0)
	; RV64IV-NEXT: addi a0, sp, 528			; RV64IV-NEXT: addi a0, sp, 528
	; RV64IV-NEXT: ld a1, 520(sp)			; RV64IV-NEXT: ld a1, 520(sp)
	; RV64IV-NEXT: vl1re64.v v9, (a0)			; RV64IV-NEXT: vl1re64.v v9, (a0)
	; RV64IV-NEXT: vsetvli zero, a1, e64, m1, ta, ma			; RV64IV-NEXT: vsetvli zero, a1, e64, m1, ta, ma
	; RV64IV-NEXT: vadd.vv v8, v8, v9			; RV64IV-NEXT: vadd.vv v8, v8, v9
	; RV64IV-NEXT: csrr a0, vlenb			; RV64IV-NEXT: csrr a0, vlenb
	Show All 20 Lines