Differential D136263 Diff 480389 llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll

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llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll

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	; CHECK-NEXT: sd ra, 24(sp) # 8-byte Folded Spill			; CHECK-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
	; CHECK-NEXT: sd s0, 16(sp) # 8-byte Folded Spill			; CHECK-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
	; CHECK-NEXT: .cfi_offset ra, -8			; CHECK-NEXT: .cfi_offset ra, -8
	; CHECK-NEXT: .cfi_offset s0, -16			; CHECK-NEXT: .cfi_offset s0, -16
	; CHECK-NEXT: csrr a0, vlenb			; CHECK-NEXT: csrr a0, vlenb
	; CHECK-NEXT: li a1, 24			; CHECK-NEXT: li a1, 24
	; CHECK-NEXT: mul a0, a0, a1			; CHECK-NEXT: mul a0, a0, a1
	; CHECK-NEXT: sub sp, sp, a0			; CHECK-NEXT: sub sp, sp, a0
				; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x20, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 32 + 24 * vlenb
	; CHECK-NEXT: li a0, 55			; CHECK-NEXT: li a0, 55
	; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma			; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
	; CHECK-NEXT: vloxseg2ei32.v v8, (a0), v8			; CHECK-NEXT: vloxseg2ei32.v v8, (a0), v8
	; CHECK-NEXT: csrr a0, vlenb			; CHECK-NEXT: csrr a0, vlenb
	; CHECK-NEXT: slli a0, a0, 3			; CHECK-NEXT: slli a0, a0, 3
	; CHECK-NEXT: add a0, sp, a0			; CHECK-NEXT: add a0, sp, a0
	; CHECK-NEXT: addi a0, a0, 16			; CHECK-NEXT: addi a0, a0, 16
	; CHECK-NEXT: csrr a1, vlenb			; CHECK-NEXT: csrr a1, vlenb
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	; SUBREGLIVENESS-NEXT: .cfi_def_cfa_offset 32			; SUBREGLIVENESS-NEXT: .cfi_def_cfa_offset 32
	; SUBREGLIVENESS-NEXT: sd ra, 24(sp) # 8-byte Folded Spill			; SUBREGLIVENESS-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
	; SUBREGLIVENESS-NEXT: sd s0, 16(sp) # 8-byte Folded Spill			; SUBREGLIVENESS-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
	; SUBREGLIVENESS-NEXT: .cfi_offset ra, -8			; SUBREGLIVENESS-NEXT: .cfi_offset ra, -8
	; SUBREGLIVENESS-NEXT: .cfi_offset s0, -16			; SUBREGLIVENESS-NEXT: .cfi_offset s0, -16
	; SUBREGLIVENESS-NEXT: csrr a0, vlenb			; SUBREGLIVENESS-NEXT: csrr a0, vlenb
	; SUBREGLIVENESS-NEXT: slli a0, a0, 4			; SUBREGLIVENESS-NEXT: slli a0, a0, 4
	; SUBREGLIVENESS-NEXT: sub sp, sp, a0			; SUBREGLIVENESS-NEXT: sub sp, sp, a0
				; SUBREGLIVENESS-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x20, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 32 + 16 * vlenb
	; SUBREGLIVENESS-NEXT: li a0, 55			; SUBREGLIVENESS-NEXT: li a0, 55
	; SUBREGLIVENESS-NEXT: vsetvli zero, a0, e16, m4, ta, ma			; SUBREGLIVENESS-NEXT: vsetvli zero, a0, e16, m4, ta, ma
	; SUBREGLIVENESS-NEXT: vloxseg2ei32.v v8, (a0), v8			; SUBREGLIVENESS-NEXT: vloxseg2ei32.v v8, (a0), v8
	; SUBREGLIVENESS-NEXT: csrr a0, vlenb			; SUBREGLIVENESS-NEXT: csrr a0, vlenb
	; SUBREGLIVENESS-NEXT: slli a0, a0, 3			; SUBREGLIVENESS-NEXT: slli a0, a0, 3
	; SUBREGLIVENESS-NEXT: add a0, sp, a0			; SUBREGLIVENESS-NEXT: add a0, sp, a0
	; SUBREGLIVENESS-NEXT: addi a0, a0, 16			; SUBREGLIVENESS-NEXT: addi a0, a0, 16
	; SUBREGLIVENESS-NEXT: csrr a1, vlenb			; SUBREGLIVENESS-NEXT: csrr a1, vlenb
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