Differential D136263 Diff 480389 llvm/lib/Target/RISCV/RISCVFrameLowering.cpp

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llvm/lib/Target/RISCV/RISCVFrameLowering.cpp

//===-- RISCVFrameLowering.cpp - RISCV Frame Information ------------------===//		//===-- RISCVFrameLowering.cpp - RISCV Frame Information ------------------===//
//		//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.		// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.		// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception		// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//		//
//===----------------------------------------------------------------------===//		//===----------------------------------------------------------------------===//
//		//
// This file contains the RISCV implementation of TargetFrameLowering class.		// This file contains the RISCV implementation of TargetFrameLowering class.
//		//
//===----------------------------------------------------------------------===//		//===----------------------------------------------------------------------===//

#include "RISCVFrameLowering.h"		#include "RISCVFrameLowering.h"
#include "RISCVMachineFunctionInfo.h"		#include "RISCVMachineFunctionInfo.h"
#include "RISCVSubtarget.h"		#include "RISCVSubtarget.h"
		#include "llvm/BinaryFormat/Dwarf.h"
#include "llvm/CodeGen/MachineFrameInfo.h"		#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"		#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"		#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"		#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/RegisterScavenging.h"		#include "llvm/CodeGen/RegisterScavenging.h"
#include "llvm/IR/DiagnosticInfo.h"		#include "llvm/IR/DiagnosticInfo.h"
#include "llvm/MC/MCDwarf.h"		#include "llvm/MC/MCDwarf.h"
		#include "llvm/Support/LEB128.h"

#include <algorithm>		#include <algorithm>

using namespace llvm;		using namespace llvm;

// For now we use x18, a.k.a s2, as pointer to shadow call stack.		// For now we use x18, a.k.a s2, as pointer to shadow call stack.
// User should explicitly set -ffixed-x18 and not use x18 in their asm.		// User should explicitly set -ffixed-x18 and not use x18 in their asm.
static void emitSCSPrologue(MachineFunction &MF, MachineBasicBlock &MBB,		static void emitSCSPrologue(MachineFunction &MF, MachineBasicBlock &MBB,
▲ Show 20 Lines • Show All 306 Lines • ▼ Show 20 Lines	void RISCVFrameLowering::adjustStackForRVV(MachineFunction &MF,

const RISCVRegisterInfo &RI = *STI.getRegisterInfo();		const RISCVRegisterInfo &RI = *STI.getRegisterInfo();
// We must keep the stack pointer aligned through any intermediate		// We must keep the stack pointer aligned through any intermediate
// updates.		// updates.
RI.adjustReg(MBB, MBBI, DL, SPReg, SPReg, Offset,		RI.adjustReg(MBB, MBBI, DL, SPReg, SPReg, Offset,
Flag, getStackAlign());		Flag, getStackAlign());
}		}

		static MCCFIInstruction createDefCFAExpression(const TargetRegisterInfo &TRI,
		Register Reg,
		kito-chengUnsubmitted Not Done Reply Inline Actions `Register Reg` rather than `unsigned Reg` kito-cheng: `Register Reg` rather than `unsigned Reg`
		uint64_t FixedOffset,
		uint64_t ScalableOffset) {
		kito-chengUnsubmitted Not Done Reply Inline Actions `uint64_t` rather than `unsigned` here, since `RVVStackSize` and `getStackSizeWithRVVPadding` are both `uint64_t` kito-cheng: `uint64_t` rather than `unsigned` here, since `RVVStackSize` and `getStackSizeWithRVVPadding`…
		assert(ScalableOffset != 0 && "Did not need to adjust CFA for RVV");
		SmallString<64> Expr;
		std::string CommentBuffer;
		llvm::raw_string_ostream Comment(CommentBuffer);
		// Build up the expression (Reg + FixedOffset + ScalableOffset * VLENB).
		unsigned DwarfReg = TRI.getDwarfRegNum(Reg, true);
		Expr.push_back((uint8_t)(dwarf::DW_OP_breg0 + DwarfReg));
		Expr.push_back(0);
		if (Reg == RISCV::X2)
		Comment << "sp";
		else
		Comment << printReg(Reg, &TRI);

		uint8_t buffer[16];
		if (FixedOffset) {
		Expr.push_back(dwarf::DW_OP_consts);
		Expr.append(buffer, buffer + encodeSLEB128(FixedOffset, buffer));
		Expr.push_back((uint8_t)dwarf::DW_OP_plus);
		Comment << " + " << FixedOffset;
		}

		Expr.push_back((uint8_t)dwarf::DW_OP_consts);
		Expr.append(buffer, buffer + encodeSLEB128(ScalableOffset, buffer));

		unsigned DwarfVlenb = TRI.getDwarfRegNum(RISCV::VLENB, true);
		Expr.push_back((uint8_t)dwarf::DW_OP_bregx);
		Expr.append(buffer, buffer + encodeULEB128(DwarfVlenb, buffer));
		Expr.push_back(0);

		Expr.push_back((uint8_t)dwarf::DW_OP_mul);
		Expr.push_back((uint8_t)dwarf::DW_OP_plus);

		Comment << " + " << ScalableOffset << " * vlenb";

		SmallString<64> DefCfaExpr;
		DefCfaExpr.push_back(dwarf::DW_CFA_def_cfa_expression);
		DefCfaExpr.append(buffer, buffer + encodeULEB128(Expr.size(), buffer));
		DefCfaExpr.append(Expr.str());

		return MCCFIInstruction::createEscape(nullptr, DefCfaExpr.str(),
		Comment.str());
		}

void RISCVFrameLowering::emitPrologue(MachineFunction &MF,		void RISCVFrameLowering::emitPrologue(MachineFunction &MF,
		kito-chengUnsubmitted Not Done Reply Inline Actions nit: one empty line between functions. kito-cheng: nit: one empty line between functions.
MachineBasicBlock &MBB) const {		MachineBasicBlock &MBB) const {
MachineFrameInfo &MFI = MF.getFrameInfo();		MachineFrameInfo &MFI = MF.getFrameInfo();
auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();		auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
const RISCVRegisterInfo *RI = STI.getRegisterInfo();		const RISCVRegisterInfo *RI = STI.getRegisterInfo();
const RISCVInstrInfo *TII = STI.getInstrInfo();		const RISCVInstrInfo *TII = STI.getInstrInfo();
MachineBasicBlock::iterator MBBI = MBB.begin();		MachineBasicBlock::iterator MBBI = MBB.begin();

Register FPReg = getFPReg(STI);		Register FPReg = getFPReg(STI);
▲ Show 20 Lines • Show All 146 Lines • ▼ Show 20 Lines	if (!hasFP(MF)) {
unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::cfiDefCfaOffset(		unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::cfiDefCfaOffset(
nullptr, getStackSizeWithRVVPadding(MF)));		nullptr, getStackSizeWithRVVPadding(MF)));
BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))		BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
.addCFIIndex(CFIIndex)		.addCFIIndex(CFIIndex)
.setMIFlag(MachineInstr::FrameSetup);		.setMIFlag(MachineInstr::FrameSetup);
}		}
}		}

if (RVVStackSize)		if (RVVStackSize) {
adjustStackForRVV(MF, MBB, MBBI, DL, -RVVStackSize,		adjustStackForRVV(MF, MBB, MBBI, DL, -RVVStackSize,
MachineInstr::FrameSetup);		MachineInstr::FrameSetup);
		if (!hasFP(MF)) {
		// Emit .cfi_def_cfa_expression "sp + StackSize + RVVStackSize * vlenb".
		unsigned CFIIndex = MF.addFrameInst(createDefCFAExpression(
		*RI, SPReg, getStackSizeWithRVVPadding(MF), RVVStackSize / 8));
		BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
		.addCFIIndex(CFIIndex)
		.setMIFlag(MachineInstr::FrameSetup);
		}
		}

if (hasFP(MF)) {		if (hasFP(MF)) {
// Realign Stack		// Realign Stack
const RISCVRegisterInfo *RI = STI.getRegisterInfo();		const RISCVRegisterInfo *RI = STI.getRegisterInfo();
if (RI->hasStackRealignment(MF)) {		if (RI->hasStackRealignment(MF)) {
Align MaxAlignment = MFI.getMaxAlign();		Align MaxAlignment = MFI.getMaxAlign();

const RISCVInstrInfo *TII = STI.getInstrInfo();		const RISCVInstrInfo *TII = STI.getInstrInfo();
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