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Differential D138949 Diff 478865 llvm/lib/Target/AMDGPU/SIISelLowering.cpp

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llvm/lib/Target/AMDGPU/SIISelLowering.cpp

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Show First 20 Lines • Show All 981 Lines • ▼ Show 20 Lines if (const AMDGPU::RsrcIntrinsic *RsrcIntr =
if (ME.doesNotAccessMemory()) if (ME.doesNotAccessMemory())
return false; return false;
SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>(); SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
const GCNTargetMachine &TM = const GCNTargetMachine &TM =
static_cast<const GCNTargetMachine &>(getTargetMachine()); static_cast<const GCNTargetMachine &>(getTargetMachine());
if (RsrcIntr->IsImage) { // TODO: Should images get their own address space?
Info.ptrVal = MFI->getImagePSV(TM);
Info.align.reset();
} else {
Info.fallbackAddressSpace = AMDGPUAS::BUFFER_FAT_POINTER; Info.fallbackAddressSpace = AMDGPUAS::BUFFER_FAT_POINTER;
}
if (RsrcIntr->IsImage)
Info.align.reset();
foadUnsubmitted
Not Done
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The braces are no longer needed.

foad: The braces are no longer needed.
nhaehnleAuthorUnsubmitted
Done
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Sure.

nhaehnle: Sure.
Info.flags |= MachineMemOperand::MODereferenceable; Info.flags |= MachineMemOperand::MODereferenceable;
if (ME.onlyReadsMemory()) { if (ME.onlyReadsMemory()) {
unsigned MaxNumLanes = 4; unsigned MaxNumLanes = 4;
if (RsrcIntr->IsImage) { if (RsrcIntr->IsImage) {
const AMDGPU::ImageDimIntrinsicInfo *Intr const AMDGPU::ImageDimIntrinsicInfo *Intr
= AMDGPU::getImageDimIntrinsicInfo(IntrID); = AMDGPU::getImageDimIntrinsicInfo(IntrID);
const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode = const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode =
▲ Show 20 Lines • Show All 111 Lines • ▼ Show 20 Linesbool SITargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
case Intrinsic::amdgcn_image_bvh_intersect_ray: { case Intrinsic::amdgcn_image_bvh_intersect_ray: {
SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>(); SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
Info.opc = ISD::INTRINSIC_W_CHAIN; Info.opc = ISD::INTRINSIC_W_CHAIN;
Info.memVT = MVT::getVT(CI.getType()); // XXX: what is correct VT? Info.memVT = MVT::getVT(CI.getType()); // XXX: what is correct VT?
const GCNTargetMachine &TM = const GCNTargetMachine &TM =
static_cast<const GCNTargetMachine &>(getTargetMachine()); static_cast<const GCNTargetMachine &>(getTargetMachine());
Info.ptrVal = MFI->getImagePSV(TM); Info.fallbackAddressSpace = AMDGPUAS::BUFFER_FAT_POINTER;
Info.align.reset(); Info.align.reset();
Info.flags |= MachineMemOperand::MOLoad | Info.flags |= MachineMemOperand::MOLoad |
MachineMemOperand::MODereferenceable; MachineMemOperand::MODereferenceable;
return true; return true;
} }
case Intrinsic::amdgcn_global_atomic_fadd: case Intrinsic::amdgcn_global_atomic_fadd:
case Intrinsic::amdgcn_global_atomic_fmin: case Intrinsic::amdgcn_global_atomic_fmin:
case Intrinsic::amdgcn_global_atomic_fmax: case Intrinsic::amdgcn_global_atomic_fmax:
▲ Show 20 Lines • Show All 12,157 Lines • Show Last 20 Lines