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Differential D138736 Diff 478716 llvm/test/CodeGen/PowerPC/v16i8_scalar_to_vector_shuffle.ll

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llvm/test/CodeGen/PowerPC/v16i8_scalar_to_vector_shuffle.ll

Show First 20 Lines • Show All 178 Lines • ▼ Show 20 Linesentry:
%vecins = insertelement <16 x i8> %a, i8 %b, i32 0 %vecins = insertelement <16 x i8> %a, i8 %b, i32 0
ret <16 x i8> %vecins ret <16 x i8> %vecins
} }
define <16 x i8> @test_none_v16i8(i8 %arg, ptr nocapture noundef readonly %b) { define <16 x i8> @test_none_v16i8(i8 %arg, ptr nocapture noundef readonly %b) {
; CHECK-LE-P8-LABEL: test_none_v16i8: ; CHECK-LE-P8-LABEL: test_none_v16i8:
; CHECK-LE-P8: # %bb.0: # %entry ; CHECK-LE-P8: # %bb.0: # %entry
; CHECK-LE-P8-NEXT: addis r5, r2, .LCPI2_0@toc@ha ; CHECK-LE-P8-NEXT: addis r5, r2, .LCPI2_0@toc@ha
; CHECK-LE-P8-NEXT: lxvd2x v2, 0, r4 ; CHECK-LE-P8-NEXT: lxvd2x vs0, 0, r4
; CHECK-LE-P8-NEXT: mtvsrd v4, r3 ; CHECK-LE-P8-NEXT: mtvsrd v4, r3
; CHECK-LE-P8-NEXT: addi r5, r5, .LCPI2_0@toc@l ; CHECK-LE-P8-NEXT: addi r5, r5, .LCPI2_0@toc@l
; CHECK-LE-P8-NEXT: lxvd2x vs0, 0, r5 ; CHECK-LE-P8-NEXT: lxvd2x vs1, 0, r5
; CHECK-LE-P8-NEXT: xxswapd v3, vs0 ; CHECK-LE-P8-NEXT: xxswapd v2, vs0
; CHECK-LE-P8-NEXT: xxswapd v3, vs1
; CHECK-LE-P8-NEXT: vperm v2, v4, v2, v3 ; CHECK-LE-P8-NEXT: vperm v2, v4, v2, v3
; CHECK-LE-P8-NEXT: blr ; CHECK-LE-P8-NEXT: blr
; ;
; CHECK-LE-P9-LABEL: test_none_v16i8: ; CHECK-LE-P9-LABEL: test_none_v16i8:
; CHECK-LE-P9: # %bb.0: # %entry ; CHECK-LE-P9: # %bb.0: # %entry
; CHECK-LE-P9-NEXT: mtfprd f0, r3 ; CHECK-LE-P9-NEXT: mtfprd f0, r3
; CHECK-LE-P9-NEXT: addis r3, r2, .LCPI2_0@toc@ha ; CHECK-LE-P9-NEXT: addis r3, r2, .LCPI2_0@toc@ha
; CHECK-LE-P9-NEXT: lxv v2, 0(r4) ; CHECK-LE-P9-NEXT: lxv v2, 0(r4)
▲ Show 20 Lines • Show All 226 Lines • ▼ Show 20 Linesentry:
%shuffle = shufflevector <16 x i8> %lhs, <16 x i8> %rhs, <16 x i32> <i32 0, i32 1, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> %shuffle = shufflevector <16 x i8> %lhs, <16 x i8> %rhs, <16 x i32> <i32 0, i32 1, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
ret <16 x i8> %shuffle ret <16 x i8> %shuffle
} }
define <16 x i8> @test_none_v8i16(i16 %arg, ptr nocapture noundef readonly %b) { define <16 x i8> @test_none_v8i16(i16 %arg, ptr nocapture noundef readonly %b) {
; CHECK-LE-P8-LABEL: test_none_v8i16: ; CHECK-LE-P8-LABEL: test_none_v8i16:
; CHECK-LE-P8: # %bb.0: # %entry ; CHECK-LE-P8: # %bb.0: # %entry
; CHECK-LE-P8-NEXT: addis r5, r2, .LCPI5_0@toc@ha ; CHECK-LE-P8-NEXT: addis r5, r2, .LCPI5_0@toc@ha
; CHECK-LE-P8-NEXT: lxvd2x v2, 0, r4 ; CHECK-LE-P8-NEXT: lxvd2x vs0, 0, r4
; CHECK-LE-P8-NEXT: mtvsrd v4, r3 ; CHECK-LE-P8-NEXT: mtvsrd v4, r3
; CHECK-LE-P8-NEXT: addi r5, r5, .LCPI5_0@toc@l ; CHECK-LE-P8-NEXT: addi r5, r5, .LCPI5_0@toc@l
; CHECK-LE-P8-NEXT: lxvd2x vs0, 0, r5 ; CHECK-LE-P8-NEXT: lxvd2x vs1, 0, r5
; CHECK-LE-P8-NEXT: xxswapd v3, vs0 ; CHECK-LE-P8-NEXT: xxswapd v2, vs0
; CHECK-LE-P8-NEXT: xxswapd v3, vs1
; CHECK-LE-P8-NEXT: vperm v2, v4, v2, v3 ; CHECK-LE-P8-NEXT: vperm v2, v4, v2, v3
; CHECK-LE-P8-NEXT: blr ; CHECK-LE-P8-NEXT: blr
; ;
; CHECK-LE-P9-LABEL: test_none_v8i16: ; CHECK-LE-P9-LABEL: test_none_v8i16:
; CHECK-LE-P9: # %bb.0: # %entry ; CHECK-LE-P9: # %bb.0: # %entry
; CHECK-LE-P9-NEXT: mtfprd f0, r3 ; CHECK-LE-P9-NEXT: mtfprd f0, r3
; CHECK-LE-P9-NEXT: addis r3, r2, .LCPI5_0@toc@ha ; CHECK-LE-P9-NEXT: addis r3, r2, .LCPI5_0@toc@ha
; CHECK-LE-P9-NEXT: lxv v2, 0(r4) ; CHECK-LE-P9-NEXT: lxv v2, 0(r4)
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