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Differential D136059 Diff 468128 llvm/test/CodeGen/AMDGPU/partial-shift-shrink.ll

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	; GCN-NEXT: v_and_b32_e32 v2, 31, v2			; GCN-NEXT: v_and_b32_e32 v2, 31, v2
	; GCN-NEXT: v_lshrrev_b64 v[0:1], v2, v[0:1]			; GCN-NEXT: v_lshrrev_b64 v[0:1], v2, v[0:1]
	; GCN-NEXT: s_setpc_b64 s[30:31]			; GCN-NEXT: s_setpc_b64 s[30:31]
	%amt.masked = and i64 %amt, 31			%amt.masked = and i64 %amt, 31
	%shift = lshr i64 %x, %amt.masked			%shift = lshr i64 %x, %amt.masked
	%trunc = trunc i64 %shift to i16			%trunc = trunc i64 %shift to i16
	ret i16 %trunc			ret i16 %trunc
	}			}

				define i32 @trunc_srl_i64_25_to_i26(i64 %x) {
				; GCN-LABEL: trunc_srl_i64_25_to_i26:
				; GCN: ; %bb.0:
				; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
				; GCN-NEXT: v_and_b32_e32 v0, 0xa000000, v0
				; GCN-NEXT: v_alignbit_b32 v0, 0, v0, 25
				; GCN-NEXT: v_add_u32_e32 v0, 55, v0
				; GCN-NEXT: s_setpc_b64 s[30:31]
				%value.knownbits2 = and i64 %x, 167772160 ; 0xA000000
				%shift = lshr i64 %value.knownbits2, 25
				%trunc = trunc i64 %shift to i26
				%add = add i26 %trunc, 55
				%ext = zext i26 %add to i32
				ret i32 %ext
				}