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Differential D135147 Diff 465666 llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp

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llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp

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bool CombinerHelper::matchExtractVecEltBuildVec(MachineInstr &MI, bool CombinerHelper::matchExtractVecEltBuildVec(MachineInstr &MI,
Register &Reg) { Register &Reg) {
assert(MI.getOpcode() == TargetOpcode::G_EXTRACT_VECTOR_ELT); assert(MI.getOpcode() == TargetOpcode::G_EXTRACT_VECTOR_ELT);
// If we have a constant index, look for a G_BUILD_VECTOR source // If we have a constant index, look for a G_BUILD_VECTOR source
// and find the source register that the index maps to. // and find the source register that the index maps to.
Register SrcVec = MI.getOperand(1).getReg(); Register SrcVec = MI.getOperand(1).getReg();
LLT SrcTy = MRI.getType(SrcVec); LLT SrcTy = MRI.getType(SrcVec);
if (!isLegalOrBeforeLegalizer( if (!isLegalOrBeforeLegalizer(
{TargetOpcode::G_BUILD_VECTOR, {SrcTy, SrcTy.getElementType()}})) {TargetOpcode::G_BUILD_VECTOR, {SrcTy, SrcTy.getElementType()}}))
return false; return false;
arsenmUnsubmitted
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I don't see why this legality check (or the one below for build_vector_trunc) are here. The equivalent DAG combine does not check for the legality, and you're not creating a new one in the apply

arsenm: I don't see why this legality check (or the one below for build_vector_trunc) are here. The…
Pierre-vhAuthorUnsubmitted
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@aemerson I see you implemented this one, is it okay to remove the legalizer checks?

Pierre-vh: @aemerson I see you implemented this one, is it okay to remove the legalizer checks?
aemersonUnsubmitted
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Sure, I don’t remember why it’s there either.

aemerson: Sure, I don’t remember why it’s there either.
auto Cst = getIConstantVRegValWithLookThrough(MI.getOperand(2).getReg(), MRI); auto Cst = getIConstantVRegValWithLookThrough(MI.getOperand(2).getReg(), MRI);
if (!Cst || Cst->Value.getZExtValue() >= SrcTy.getNumElements()) if (!Cst || Cst->Value.getZExtValue() >= SrcTy.getNumElements())
return false; return false;
unsigned VecIdx = Cst->Value.getZExtValue(); unsigned VecIdx = Cst->Value.getZExtValue();
MachineInstr *BuildVecMI =
getOpcodeDef(TargetOpcode::G_BUILD_VECTOR, SrcVec, MRI); MachineInstr *SrcVecMI = MRI.getVRegDef(SrcVec);
arsenmUnsubmitted
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getVRegDef should be adequate here

arsenm: getVRegDef should be adequate here
if (!BuildVecMI) {
BuildVecMI = getOpcodeDef(TargetOpcode::G_BUILD_VECTOR_TRUNC, SrcVec, MRI); // Check if we have a (trunc (build_vector)) ..
if (!BuildVecMI) if (SrcVecMI->getOpcode() == TargetOpcode::G_TRUNC) {
return false; SrcVecMI = MRI.getVRegDef(SrcVecMI->getOperand(1).getReg());
LLT ScalarTy = MRI.getType(BuildVecMI->getOperand(1).getReg()); }
// Need a build_vector or build_vector_trunc
switch (SrcVecMI->getOpcode()) {
case TargetOpcode::G_BUILD_VECTOR:
break;
case TargetOpcode::G_BUILD_VECTOR_TRUNC: {
LLT ScalarTy = MRI.getType(SrcVecMI->getOperand(1).getReg());
if (!isLegalOrBeforeLegalizer( if (!isLegalOrBeforeLegalizer(
{TargetOpcode::G_BUILD_VECTOR_TRUNC, {SrcTy, ScalarTy}})) {TargetOpcode::G_BUILD_VECTOR_TRUNC, {SrcTy, ScalarTy}}))
return false; return false;
break;
}
default:
return false;
} }
EVT Ty(getMVTForLLT(SrcTy)); EVT Ty(getMVTForLLT(SrcTy));
if (!MRI.hasOneNonDBGUse(SrcVec) && if (!MRI.hasOneNonDBGUse(SrcVec) &&
!getTargetLowering().aggressivelyPreferBuildVectorSources(Ty)) !getTargetLowering().aggressivelyPreferBuildVectorSources(Ty))
return false; return false;
Reg = BuildVecMI->getOperand(VecIdx + 1).getReg(); Reg = SrcVecMI->getOperand(VecIdx + 1).getReg();
return true; return true;
} }
void CombinerHelper::applyExtractVecEltBuildVec(MachineInstr &MI, void CombinerHelper::applyExtractVecEltBuildVec(MachineInstr &MI,
Register &Reg) { Register &Reg) {
// Check the type of the register, since it may have come from a // Check the type of the register, since it may have come from a
// G_BUILD_VECTOR_TRUNC. // G_BUILD_VECTOR_TRUNC.
LLT ScalarTy = MRI.getType(Reg); LLT ScalarTy = MRI.getType(Reg);
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