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Differential D132839 Diff 464635 llvm/lib/Target/RISCV/RISCVInstrInfo.td

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llvm/lib/Target/RISCV/RISCVInstrInfo.td

Show First 20 Lines • Show All 231 Lines • ▼ Show 20 Lines let MCOperandPredicate = [{
if (MCOp.evaluateAsConstantImm(Imm)) if (MCOp.evaluateAsConstantImm(Imm))
return isInt<12>(Imm); return isInt<12>(Imm);
return MCOp.isBareSymbolRef(); return MCOp.isBareSymbolRef();
}]; }];
let OperandType = "OPERAND_SIMM12"; let OperandType = "OPERAND_SIMM12";
let OperandNamespace = "RISCVOp"; let OperandNamespace = "RISCVOp";
} }
// A 12-bit signed immediate which cannot fit in 6-bit signed immediate,
// but even negative value fit in 12-bit.
def simm12_no6 : ImmLeaf<XLenVT, [{
return isInt<12>(Imm) && !isInt<6>(Imm) && isInt<12>(-Imm);}]>;
// A 13-bit signed immediate where the least significant bit is zero. // A 13-bit signed immediate where the least significant bit is zero.
def simm13_lsb0 : Operand<OtherVT> { def simm13_lsb0 : Operand<OtherVT> {
let ParserMatchClass = SImmAsmOperand<13, "Lsb0">; let ParserMatchClass = SImmAsmOperand<13, "Lsb0">;
let PrintMethod = "printBranchOperand"; let PrintMethod = "printBranchOperand";
let EncoderMethod = "getImmOpValueAsr1"; let EncoderMethod = "getImmOpValueAsr1";
let DecoderMethod = "decodeSImmOperandAndLsl1<13>"; let DecoderMethod = "decodeSImmOperandAndLsl1<13>";
let MCOperandPredicate = [{ let MCOperandPredicate = [{
int64_t Imm; int64_t Imm;
▲ Show 20 Lines • Show All 1,073 Lines • ▼ Show 20 Linesmulticlass SelectCC_GPR_rrirr<RegisterClass valty> {
def : Pat<(riscv_selectcc_frag:$cc GPR:$lhs, 0, cond, valty:$truev, def : Pat<(riscv_selectcc_frag:$cc GPR:$lhs, 0, cond, valty:$truev,
valty:$falsev), valty:$falsev),
(!cast<Instruction>(NAME#"_Using_CC_GPR") GPR:$lhs, X0, (!cast<Instruction>(NAME#"_Using_CC_GPR") GPR:$lhs, X0,
(IntCCtoRISCVCC $cc), valty:$truev, valty:$falsev)>; (IntCCtoRISCVCC $cc), valty:$truev, valty:$falsev)>;
} }
defm Select_GPR : SelectCC_GPR_rrirr<GPR>; defm Select_GPR : SelectCC_GPR_rrirr<GPR>;
class SelectCompressOpt<CondCode Cond>: Pat<(riscv_selectcc_frag:$select GPR:$lhs, simm12_no6:$Constant, Cond,
craig.topperUnsubmitted
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Please put the branch related code in the branch section of this file.

craig.topper: Please put the branch related code in the branch section of this file.
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Done

ita-sc: Done
GPR:$truev, GPR:$falsev),
(Select_GPR_Using_CC_GPR (ADDI GPR:$lhs, (NegImm simm12:$Constant)), X0,
(IntCCtoRISCVCC $select), GPR:$truev, GPR:$falsev)>;
def OptForMinSize : Predicate<"MF ? MF->getFunction().hasMinSize() : false">;
let Predicates = [HasStdExtC, OptForMinSize] in {
craig.topperUnsubmitted
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When wouldn't we have a valid MF?

craig.topper: When wouldn't we have a valid MF?
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I guess It happens when we run LLVM IR pass that needs SubTargetImpl.
For example, pass Expand Atomic instructions tries to get SubTargetImpl.
It calls createRISCVInstructionSelector during initialization. In it there is an initialization of predicates for globalISel (see GET_GLOBALISEL_PREDICATES_INIT).
Internally it calls computeAvailableModuleFeatures, where all predicates initilized (usially they use subtarget, that is already initialized), but MF is uninitialized there so there will be error.

ita-sc: I guess It happens when we run LLVM IR pass that needs SubTargetImpl. For example, pass Expand…
def : SelectCompressOpt<SETEQ>;
def : SelectCompressOpt<SETNE>;
}
/// Branches and jumps /// Branches and jumps
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Blank line before this comment.

craig.topper: Blank line before this comment.
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Done

ita-sc: Done
// Match `riscv_brcc` and lower to the appropriate RISC-V branch instruction. // Match `riscv_brcc` and lower to the appropriate RISC-V branch instruction.
multiclass BccPat<CondCode Cond, RVInstB Inst> { multiclass BccPat<CondCode Cond, RVInstB Inst> {
def : Pat<(riscv_brcc GPR:$rs1, GPR:$rs2, Cond, bb:$imm12), def : Pat<(riscv_brcc GPR:$rs1, GPR:$rs2, Cond, bb:$imm12),
(Inst GPR:$rs1, GPR:$rs2, simm13_lsb0:$imm12)>; (Inst GPR:$rs1, GPR:$rs2, simm13_lsb0:$imm12)>;
// Explicitly select 0 to X0. The register coalescer doesn't always do it. // Explicitly select 0 to X0. The register coalescer doesn't always do it.
def : Pat<(riscv_brcc GPR:$rs1, 0, Cond, bb:$imm12), def : Pat<(riscv_brcc GPR:$rs1, 0, Cond, bb:$imm12),
(Inst GPR:$rs1, X0, simm13_lsb0:$imm12)>; (Inst GPR:$rs1, X0, simm13_lsb0:$imm12)>;
} }
class BrccCompessOpt<CondCode Cond, RVInstB Inst> : Pat<(riscv_brcc GPR:$lhs, simm12_no6:$Constant, Cond, bb:$place),
(Inst (ADDI GPR:$lhs, (NegImm simm12:$Constant)), X0, bb:$place)>;
defm : BccPat<SETEQ, BEQ>; defm : BccPat<SETEQ, BEQ>;
defm : BccPat<SETNE, BNE>; defm : BccPat<SETNE, BNE>;
defm : BccPat<SETLT, BLT>; defm : BccPat<SETLT, BLT>;
defm : BccPat<SETGE, BGE>; defm : BccPat<SETGE, BGE>;
defm : BccPat<SETULT, BLTU>; defm : BccPat<SETULT, BLTU>;
defm : BccPat<SETUGE, BGEU>; defm : BccPat<SETUGE, BGEU>;
let Predicates = [HasStdExtC, OptForMinSize] in {
def : BrccCompessOpt<SETEQ, BEQ>;
def : BrccCompessOpt<SETNE, BNE>;
}
let isBarrier = 1, isBranch = 1, isTerminator = 1 in let isBarrier = 1, isBranch = 1, isTerminator = 1 in
def PseudoBR : Pseudo<(outs), (ins simm21_lsb0_jal:$imm20), [(br bb:$imm20)]>, def PseudoBR : Pseudo<(outs), (ins simm21_lsb0_jal:$imm20), [(br bb:$imm20)]>,
PseudoInstExpansion<(JAL X0, simm21_lsb0_jal:$imm20)>; PseudoInstExpansion<(JAL X0, simm21_lsb0_jal:$imm20)>;
let isBarrier = 1, isBranch = 1, isIndirectBranch = 1, isTerminator = 1 in let isBarrier = 1, isBranch = 1, isIndirectBranch = 1, isTerminator = 1 in
def PseudoBRIND : Pseudo<(outs), (ins GPRJALR:$rs1, simm12:$imm12), []>, def PseudoBRIND : Pseudo<(outs), (ins GPRJALR:$rs1, simm12:$imm12), []>,
PseudoInstExpansion<(JALR X0, GPR:$rs1, simm12:$imm12)>; PseudoInstExpansion<(JALR X0, GPR:$rs1, simm12:$imm12)>;
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