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Differential D134745 Diff 463299 llvm/test/Transforms/LoopVectorize/explicit_outer_detection.ll

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llvm/test/Transforms/LoopVectorize/explicit_outer_detection.ll

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; a[i*M+j] = b[i*M+j] * b[i*M+j]; ; a[i*M+j] = b[i*M+j] * b[i*M+j];
; } ; }
; } ; }
; } ; }
; Case 1: Annotated outer loop WITH vector width information must be collected. ; Case 1: Annotated outer loop WITH vector width information must be collected.
; CHECK-LABEL: vector_width ; CHECK-LABEL: vector_width
; CHECK: LV: Loop hints: force=enabled width=4 interleave=0 ; CHECK: LV: Loop hints: force_vectorization=enabled width=4 force_interleave=disabled interleave=0
; CHECK: LV: We can vectorize this outer loop! ; CHECK: LV: We can vectorize this outer loop!
; CHECK: LV: Using user VF 4 to build VPlans. ; CHECK: LV: Using user VF 4 to build VPlans.
; CHECK-NOT: LV: Loop hints: force=? ; CHECK-NOT: LV: Loop hints: force_vectorization=? width=0 force_interleave=? interleave=0
; CHECK-NOT: LV: Found a loop: inner.body ; CHECK-NOT: LV: Found a loop: inner.body
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
define void @vector_width(i32* nocapture %a, i32* nocapture readonly %b, i32 %N, i32 %M) local_unnamed_addr { define void @vector_width(i32* nocapture %a, i32* nocapture readonly %b, i32 %N, i32 %M) local_unnamed_addr {
entry: entry:
%cmp32 = icmp sgt i32 %N, 0 %cmp32 = icmp sgt i32 %N, 0
br i1 %cmp32, label %outer.ph, label %for.end15 br i1 %cmp32, label %outer.ph, label %for.end15
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for.end15: ; preds = %outer.inc, %entry for.end15: ; preds = %outer.inc, %entry
ret void ret void
} }
; Case 2: Annotated outer loop WITHOUT vector width information must be collected. ; Case 2: Annotated outer loop WITHOUT vector width information must be collected.
; CHECK-LABEL: case2 ; CHECK-LABEL: case2
; CHECK: LV: Loop hints: force=enabled width=0 interleave=0 ; CHECK: LV: Loop hints: force_vectorization=enabled width=0 force_interleave=disabled interleave=0
; CHECK: LV: We can vectorize this outer loop! ; CHECK: LV: We can vectorize this outer loop!
; CHECK: LV: Using VF 1 to build VPlans. ; CHECK: LV: Using VF 1 to build VPlans.
define void @case2(i32* nocapture %a, i32* nocapture readonly %b, i32 %N, i32 %M) local_unnamed_addr { define void @case2(i32* nocapture %a, i32* nocapture readonly %b, i32 %N, i32 %M) local_unnamed_addr {
entry: entry:
%cmp32 = icmp sgt i32 %N, 0 %cmp32 = icmp sgt i32 %N, 0
br i1 %cmp32, label %outer.ph, label %for.end15 br i1 %cmp32, label %outer.ph, label %for.end15
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} }
; Case 3: Annotated outer loop WITH vector width and interleave information ; Case 3: Annotated outer loop WITH vector width and interleave information
; doesn't have to be collected. ; doesn't have to be collected.
; CHECK-LABEL: case3 ; CHECK-LABEL: case3
; CHECK-NOT: LV: Loop hints: force=enabled ; CHECK-NOT: LV: Loop hints: force=enabled
; CHECK-NOT: LV: We can vectorize this outer loop! ; CHECK-NOT: LV: We can vectorize this outer loop!
; CHECK: LV: Loop hints: force=? ; CHECK: LV: Loop hints: force_vectorization=? width=0 force_interleave=? interleave=0
; CHECK: LV: Found a loop: inner.body ; CHECK: LV: Found a loop: inner.body
define void @case3(i32* nocapture %a, i32* nocapture readonly %b, i32 %N, i32 %M) local_unnamed_addr { define void @case3(i32* nocapture %a, i32* nocapture readonly %b, i32 %N, i32 %M) local_unnamed_addr {
entry: entry:
%cmp32 = icmp sgt i32 %N, 0 %cmp32 = icmp sgt i32 %N, 0
br i1 %cmp32, label %outer.ph, label %for.end15 br i1 %cmp32, label %outer.ph, label %for.end15
outer.ph: ; preds = %entry outer.ph: ; preds = %entry
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} }
; Case 4: Outer loop without any explicit vectorization annotation doesn't have ; Case 4: Outer loop without any explicit vectorization annotation doesn't have
; to be collected. ; to be collected.
; CHECK-LABEL: case4 ; CHECK-LABEL: case4
; CHECK-NOT: LV: Loop hints: force=enabled ; CHECK-NOT: LV: Loop hints: force=enabled
; CHECK-NOT: LV: We can vectorize this outer loop! ; CHECK-NOT: LV: We can vectorize this outer loop!
; CHECK: LV: Loop hints: force=? ; CHECK: LV: Loop hints: force_vectorization=? width=0 force_interleave=? interleave=0
; CHECK: LV: Found a loop: inner.body ; CHECK: LV: Found a loop: inner.body
define void @case4(i32* nocapture %a, i32* nocapture readonly %b, i32 %N, i32 %M) local_unnamed_addr { define void @case4(i32* nocapture %a, i32* nocapture readonly %b, i32 %N, i32 %M) local_unnamed_addr {
entry: entry:
%cmp32 = icmp sgt i32 %N, 0 %cmp32 = icmp sgt i32 %N, 0
br i1 %cmp32, label %outer.ph, label %for.end15 br i1 %cmp32, label %outer.ph, label %for.end15
outer.ph: ; preds = %entry outer.ph: ; preds = %entry
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!0 = !{i32 1, !"wchar_size", i32 4} !0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{!"clang version 6.0.0"} !1 = !{!"clang version 6.0.0"}
!2 = !{!3, !3, i64 0} !2 = !{!3, !3, i64 0}
!3 = !{!"int", !4, i64 0} !3 = !{!"int", !4, i64 0}
!4 = !{!"omnipotent char", !5, i64 0} !4 = !{!"omnipotent char", !5, i64 0}
!5 = !{!"Simple C/C++ TBAA"} !5 = !{!"Simple C/C++ TBAA"}
; Case 1 ; Case 1
!6 = distinct !{!6, !7, !8} !6 = distinct !{!6, !7, !8, !12}
!7 = !{!"llvm.loop.vectorize.width", i32 4} !7 = !{!"llvm.loop.vectorize.width", i32 4}
!8 = !{!"llvm.loop.vectorize.enable", i1 true} !8 = !{!"llvm.loop.vectorize.enable", i1 true}
; Case 2 ; Case 2
!9 = distinct !{!9, !8} !9 = distinct !{!9, !8, !12}
; Case 3 ; Case 3
!10 = !{!"llvm.loop.interleave.count", i32 2} !10 = !{!"llvm.loop.interleave.count", i32 2}
!11 = distinct !{!11, !7, !10, !8} !11 = distinct !{!11, !7, !10, !8, !13}
!12 = !{!"llvm.loop.interleave.enable", i1 false}
!13 = !{!"llvm.loop.interleave.enable", i1 true}