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llvm/test/Transforms/SLPVectorizer/X86/revectorized_rdx_crash.ll
| Show All 16 Lines | |||||
| ; CHECK-NEXT: entry: | ; CHECK-NEXT: entry: | ||||
| ; CHECK-NEXT: br i1 undef, label [[IF_END:%.*]], label [[FOR_COND_PREHEADER:%.*]] | ; CHECK-NEXT: br i1 undef, label [[IF_END:%.*]], label [[FOR_COND_PREHEADER:%.*]] | ||||
| ; CHECK: for.cond.preheader: | ; CHECK: for.cond.preheader: | ||||
| ; CHECK-NEXT: [[I:%.*]] = getelementptr inbounds [100 x i32], [100 x i32]* undef, i64 0, i64 2 | ; CHECK-NEXT: [[I:%.*]] = getelementptr inbounds [100 x i32], [100 x i32]* undef, i64 0, i64 2 | ||||
| ; CHECK-NEXT: [[I1:%.*]] = getelementptr inbounds [100 x i32], [100 x i32]* undef, i64 0, i64 3 | ; CHECK-NEXT: [[I1:%.*]] = getelementptr inbounds [100 x i32], [100 x i32]* undef, i64 0, i64 3 | ||||
| ; CHECK-NEXT: [[TMP0:%.*]] = bitcast i32* [[I]] to <4 x i32>* | ; CHECK-NEXT: [[TMP0:%.*]] = bitcast i32* [[I]] to <4 x i32>* | ||||
| ; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, <4 x i32>* [[TMP0]], align 8 | ; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, <4 x i32>* [[TMP0]], align 8 | ||||
| ; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP1]]) | ; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP1]]) | ||||
| ; CHECK-NEXT: [[OP_RDX7:%.*]] = add i32 [[TMP2]], undef | ; CHECK-NEXT: [[OP_RDX3:%.*]] = add i32 [[TMP2]], undef | ||||
| ; CHECK-NEXT: [[OP_RDX8:%.*]] = add i32 [[OP_RDX7]], undef | |||||
| ; CHECK-NEXT: [[TMP3:%.*]] = bitcast i32* [[I1]] to <4 x i32>* | ; CHECK-NEXT: [[TMP3:%.*]] = bitcast i32* [[I1]] to <4 x i32>* | ||||
| ; CHECK-NEXT: [[TMP4:%.*]] = load <4 x i32>, <4 x i32>* [[TMP3]], align 4 | ; CHECK-NEXT: [[TMP4:%.*]] = load <4 x i32>, <4 x i32>* [[TMP3]], align 4 | ||||
| ; CHECK-NEXT: [[TMP5:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP4]]) | ; CHECK-NEXT: [[TMP5:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP4]]) | ||||
| ; CHECK-NEXT: [[OP_RDX5:%.*]] = add i32 [[TMP5]], undef | ; CHECK-NEXT: [[OP_RDX2:%.*]] = add i32 [[TMP5]], undef | ||||
| ; CHECK-NEXT: [[OP_RDX6:%.*]] = add i32 [[OP_RDX5]], undef | ; CHECK-NEXT: [[TMP6:%.*]] = mul i32 [[OP_RDX3]], 2 | ||||
| ; CHECK-NEXT: [[TMP6:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> undef) | ; CHECK-NEXT: [[OP_RDX:%.*]] = add i32 undef, [[TMP6]] | ||||
| ; CHECK-NEXT: [[OP_RDX:%.*]] = add i32 [[TMP6]], undef | ; CHECK-NEXT: [[TMP7:%.*]] = mul i32 [[OP_RDX2]], 2 | ||||
| ; CHECK-NEXT: [[OP_RDX1:%.*]] = add i32 [[OP_RDX8]], [[OP_RDX8]] | ; CHECK-NEXT: [[OP_RDX1:%.*]] = add i32 [[OP_RDX]], [[TMP7]] | ||||
| ; CHECK-NEXT: [[OP_RDX2:%.*]] = add i32 [[OP_RDX6]], [[OP_RDX6]] | |||||
| ; CHECK-NEXT: [[OP_RDX3:%.*]] = add i32 [[OP_RDX]], [[OP_RDX1]] | |||||
| ; CHECK-NEXT: [[OP_RDX4:%.*]] = add i32 [[OP_RDX3]], [[OP_RDX2]] | |||||
| ; CHECK-NEXT: br label [[IF_END]] | ; CHECK-NEXT: br label [[IF_END]] | ||||
| ; CHECK: if.end: | ; CHECK: if.end: | ||||
| ; CHECK-NEXT: [[R:%.*]] = phi i32 [ [[OP_RDX4]], [[FOR_COND_PREHEADER]] ], [ undef, [[ENTRY:%.*]] ] | ; CHECK-NEXT: [[R:%.*]] = phi i32 [ [[OP_RDX1]], [[FOR_COND_PREHEADER]] ], [ undef, [[ENTRY:%.*]] ] | ||||
| ; CHECK-NEXT: ret void | ; CHECK-NEXT: ret void | ||||
| ; | ; | ||||
| entry: | entry: | ||||
| br i1 undef, label %if.end, label %for.cond.preheader | br i1 undef, label %if.end, label %for.cond.preheader | ||||
| for.cond.preheader: ; preds = %entry | for.cond.preheader: ; preds = %entry | ||||
| %i = getelementptr inbounds [100 x i32], [100 x i32]* undef, i64 0, i64 2 | %i = getelementptr inbounds [100 x i32], [100 x i32]* undef, i64 0, i64 2 | ||||
| %i1 = getelementptr inbounds [100 x i32], [100 x i32]* undef, i64 0, i64 3 | %i1 = getelementptr inbounds [100 x i32], [100 x i32]* undef, i64 0, i64 3 | ||||
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