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llvm/test/Transforms/SLPVectorizer/X86/reorder_repeated_ops.ll
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| ; CHECK: bb1: | ; CHECK: bb1: | ||||
| ; CHECK-NEXT: ret void | ; CHECK-NEXT: ret void | ||||
| ; CHECK: bb2: | ; CHECK: bb2: | ||||
| ; CHECK-NEXT: [[T:%.*]] = select i1 undef, i16 undef, i16 15 | ; CHECK-NEXT: [[T:%.*]] = select i1 undef, i16 undef, i16 15 | ||||
| ; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i16> <i16 undef, i16 poison>, i16 [[T]], i32 1 | ; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i16> <i16 undef, i16 poison>, i16 [[T]], i32 1 | ||||
| ; CHECK-NEXT: [[TMP1:%.*]] = sext <2 x i16> [[TMP0]] to <2 x i32> | ; CHECK-NEXT: [[TMP1:%.*]] = sext <2 x i16> [[TMP0]] to <2 x i32> | ||||
| ; CHECK-NEXT: [[TMP2:%.*]] = sub nsw <2 x i32> <i32 63, i32 undef>, [[TMP1]] | ; CHECK-NEXT: [[TMP2:%.*]] = sub nsw <2 x i32> <i32 63, i32 undef>, [[TMP1]] | ||||
| ; CHECK-NEXT: [[TMP3:%.*]] = sub <2 x i32> [[TMP2]], undef | ; CHECK-NEXT: [[TMP3:%.*]] = sub <2 x i32> [[TMP2]], undef | ||||
| ; CHECK-NEXT: [[SHUFFLE4:%.*]] = shufflevector <2 x i32> [[TMP3]], <2 x i32> poison, <4 x i32> <i32 1, i32 0, i32 1, i32 1> | ; CHECK-NEXT: [[SHUFFLE2:%.*]] = shufflevector <2 x i32> [[TMP3]], <2 x i32> poison, <4 x i32> <i32 1, i32 0, i32 1, i32 1> | ||||
| ; CHECK-NEXT: [[TMP4:%.*]] = add <4 x i32> [[SHUFFLE4]], <i32 15, i32 undef, i32 31, i32 47> | ; CHECK-NEXT: [[TMP4:%.*]] = add <4 x i32> [[SHUFFLE2]], <i32 15, i32 undef, i32 31, i32 47> | ||||
| ; CHECK-NEXT: [[TMP5:%.*]] = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> [[TMP4]]) | ; CHECK-NEXT: [[TMP5:%.*]] = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> [[TMP4]]) | ||||
| ; CHECK-NEXT: [[T19:%.*]] = select i1 undef, i32 [[TMP5]], i32 undef | ; CHECK-NEXT: [[T19:%.*]] = select i1 undef, i32 [[TMP5]], i32 undef | ||||
| ; CHECK-NEXT: [[T20:%.*]] = icmp sgt i32 [[T19]], 63 | ; CHECK-NEXT: [[T20:%.*]] = icmp sgt i32 [[T19]], 63 | ||||
| ; CHECK-NEXT: [[TMP6:%.*]] = sub nsw <2 x i32> undef, [[TMP1]] | ; CHECK-NEXT: [[TMP6:%.*]] = sub nsw <2 x i32> undef, [[TMP1]] | ||||
| ; CHECK-NEXT: [[TMP7:%.*]] = sub <2 x i32> [[TMP6]], undef | ; CHECK-NEXT: [[TMP7:%.*]] = sub <2 x i32> [[TMP6]], undef | ||||
| ; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <2 x i32> [[TMP7]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 0, i32 1> | ; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <2 x i32> [[TMP7]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 0, i32 1> | ||||
| ; CHECK-NEXT: [[TMP8:%.*]] = add nsw <4 x i32> [[SHUFFLE]], <i32 -17, i32 -33, i32 -33, i32 -49> | ; CHECK-NEXT: [[TMP8:%.*]] = add nsw <4 x i32> [[SHUFFLE]], <i32 -17, i32 -33, i32 -33, i32 -49> | ||||
| ; CHECK-NEXT: [[TMP9:%.*]] = call i32 @llvm.vector.reduce.smin.v4i32(<4 x i32> undef) | ; CHECK-NEXT: [[TMP9:%.*]] = call i32 @llvm.vector.reduce.smin.v4i32(<4 x i32> [[TMP8]]) | ||||
| ; CHECK-NEXT: [[TMP10:%.*]] = call i32 @llvm.vector.reduce.smin.v4i32(<4 x i32> [[TMP8]]) | ; CHECK-NEXT: [[OP_RDX:%.*]] = icmp slt i32 undef, [[TMP9]] | ||||
| ; CHECK-NEXT: [[OP_RDX:%.*]] = icmp slt i32 [[TMP9]], [[TMP10]] | ; CHECK-NEXT: [[OP_RDX1:%.*]] = select i1 [[OP_RDX]], i32 undef, i32 [[TMP9]] | ||||
| ; CHECK-NEXT: [[OP_RDX1:%.*]] = select i1 [[OP_RDX]], i32 [[TMP9]], i32 [[TMP10]] | ; CHECK-NEXT: [[T45:%.*]] = icmp sgt i32 undef, [[OP_RDX1]] | ||||
| ; CHECK-NEXT: [[OP_RDX2:%.*]] = icmp slt i32 [[OP_RDX1]], undef | |||||
| ; CHECK-NEXT: [[OP_RDX3:%.*]] = select i1 [[OP_RDX2]], i32 [[OP_RDX1]], i32 undef | |||||
| ; CHECK-NEXT: [[T45:%.*]] = icmp sgt i32 undef, [[OP_RDX3]] | |||||
| ; CHECK-NEXT: unreachable | ; CHECK-NEXT: unreachable | ||||
| ; | ; | ||||
| bb: | bb: | ||||
| br i1 undef, label %bb1, label %bb2 | br i1 undef, label %bb1, label %bb2 | ||||
| bb1: ; preds = %bb | bb1: ; preds = %bb | ||||
| ret void | ret void | ||||
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